SP720

SP720 Data Sheet January 1998 File Number 2791.10 Electronic Protection Array for ESD and Over-Voltage Protection [ /Title (SP720 ) /Subject (Electronic Protection Array for ESD and OverVoltage Protection) /Autho r () /Keywords (TVS, Transient Suppression, Protection, ESD, IEC, EMC, Electromagnet ic ComThe SP720 is an array of SCR/Diode bipolar structures for ESD and over-voltage protection to sensitive input circuits. The SP720 has 2 protection SCR/Diode device structures per input. A total of 14 available inputs can be used to protect up to 14 external signal or bus lines. Over-voltage protection is from the IN (pins 1-7 and 9-15) to V+ or V-. The SCR structures are designed for fast triggering at a threshold of one +VBE diode threshold above V+ (Pin 16) or a -VBE diode threshold below V- (Pin 8). From an IN input, a clamp to V+ is activated if a transient pulse causes the input to be increased to a voltage level greater than one VBE above V+. A similar clamp to V- is activated if a negative pulse, one VBE less than V-, is applied to an IN input. Standard ESD Human Body Model (HBM) Capability is: HBM STANDARD IEC 1000-4-2 Air Direct Direct, Dual Pins MIL-STD-3015.7 Direct, In-circuit MODE R 330Ω 330Ω 330Ω 1.5kΩ C 150pF 150pF 150pF 100pF ESD (V) >15kV >4kV >8kV >15kV Features • ESD Interface Capability for HBM Standards - MIL STD 3015.7 . . . . . . . . . . . . . . . . . . . . . . . . . . .15kV - IEC 1000-4-2, Direct Discharge, Single Input. . . . . . . . . . . . . . . . . . . . . . . . 4kV (Level 2) Two Inputs in Parallel . . . . . . . . . . . . . . . . 8kV (Level 4) - IEC 1000-4-2, Air Discharge. . . . . . . . . . 15kV (Level 4) • High Peak Current Capability - IEC 1000-4-5 (8/20µs) . . . . . . . . . . . . . . . . . . . . . . ±3A - Single Pulse, 100µs Pulse Width . . . . . . . . . . . . . . ±2A - Single Pulse, 4µs Pulse Width . . . . . . . . . . . . . . . . ±5A • Designed to Provide Over-Voltage Protection - Single-Ended Voltage Range to . . . . . . . . . . . . . . .+30V - Differential Voltage Range to . . . . . . . . . . . . . . . . ±15V • Fast Switching . . . . . . . . . . . . . . . . . . . . . . . 2ns Risetime • Low Input Leakages . . . . . . . . . . . . . . . 1nA at 25oC (Typ) • Low Input Capacitance. . . . . . . . . . . . . . . . . . . . 3pF (Typ) • An Array of 14 SCR/Diode Pairs • Operating Temperature Range . . . . . . . . . -40oC to 105oC Refer to Figure 1 and Table 1 for further detail. Refer to Application Note AN9304 and AN9612 for additional information. Applications • Microprocessor/Logic Input Protection • Data Bus Protection • Analog Device Input Protection Ordering Information PART NO. SP720AP SP720AB SP720ABT TEMP. RANGE (oC) -40 to 105 -40 to 105 -40 to 105 PACKAGE 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC Tape and Reel PKG. NO. E16.3 M16.15 M16.15 • Voltage Clamp Functional Block Diagram V+ 16 Pinout SP720 (PDIP, SOIC) TOP VIEW IN IN IN IN IN IN IN V1 2 3 4 5 6 7 8 16 V+ 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 IN V8 IN IN 1 2 3-7 9 - 15 IN 6-3 NOTE: The design of the SP720 SCR/Diode ESD Protection Arrays is covered by Littelfuse patent 4567500. 1-800-999-9445 or 1-847-824-1188 | Copyright © Littelfuse, Inc. 1998 SP720 Absolute Maximum Ratings Continuous Supply Voltage, (V+) - (V-) . . . . . . . . . . . . . . . . . . +35V Forward Peak Current, IIN to VCC, IIN to GND (Refer to Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2A, 100µs ESD Ratings and Capability (Figure 1, Table 1) Load Dump and Reverse Battery (Note 2) Thermal Information Thermal Resistance (Typical, Note 1) . . . . . . . . . . . . . θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Junction Temperature (Plastic Package) . . . . . . . . .150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (SOIC Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications PARAMETER Operating Voltage Range, VSUPPLY = [(V+) - (V-)] Forward Voltage Drop: IN to VIN to V+ Input Leakage Current Quiescent Supply Current Equivalent SCR ON Threshold Equivalent SCR ON Resistance Input Capacitance Input Switching Speed NOTES: TA = -40oC to 105oC; VIN = 0.5VCC , Unless Otherwise Specified SYMBOL VSUPPLY IIN = 1A (Peak Pulse) VFWDL VFWDH I IN IQUIESCENT Note 3 VFWD/IFWD; Note 3 C IN t ON -20 2 2 5 50 1.1 1 3 2 20 200 V V nA nA V Ω pF ns TEST CONDITIONS MIN TYP 2 to 30 MAX UNITS V 2. In automotive and battery operated systems, the power supply lines should be externally protected for load dump and reverse battery. When the V+ and V- pins are connected to the same supply voltage source as the device or control line under protection, a current limiting resistor should be connected in series between the external supply and the SP720 supply pins to limit reverse battery current to within the rated maximum limits. Bypass capacitors of typically 0.01µF or larger from the V+ and V- pins to ground are recommended. 3. Refer to the Figure 3 graph for definitions of equivalent “SCR ON Threshold” and “SCR ON Resistance.” These characteristics are given here for thumb-rule information to determine peak current and dissipation under EOS conditions. ESD Capability ESD capability is dependent on the application and defined test standard. The evaluation results for various test standards and methods based on Figure 1 are shown in Table 1. For the “Modified” MIL-STD-3015.7 condition that is defined as an “in-circuit” method of ESD testing, the V+ and V- pins have a return path to ground and the SP720 ESD capability is typically greater than 15kV from 100pF through 1.5kΩ. By strict definition of MIL-STD-3015.7 using “pin-to-pin” device testing, the ESD voltage capability is greater than 6kV. The MIL-STD-3015.7 results were determined from AT&T ESD Test Lab measurements. The HBM capability to the IEC 1000-4-2 standard is greater than 15kV for air discharge (Level 4) and greater than 4kV for direct discharge (Level 2). Dual pin capability (2 adjacent pins in parallel) is well in excess of 8kV (Level 4). For ESD testing of the SP720 to EIAJ IC121 Machine Model (MM) standard, the results are typically better than 1kV from 200pF with no series resistance. TABLE 1. ESD TEST CONDITIONS STANDARD TYPE/MODE Standard HBM IEC 1000-4-2 HBM, Air Discharge HBM, Direct Discharge HBM, Direct Discharge, Two Parallel Input Pins EIAJ IC121 Machine Model R1 CHARGE SWITCH CD H.V. SUPPLY °±VD IEC 1000-4-2: R1 50 to 100MΩ MIL STD 3015.7: R1 1 to 10MΩ RD DISCHARGE SWITCH IN DUT RD CD ±V D 6kV 4kV 8kV 1kV MIL STD 3015.7 Modified HBM 1.5kΩ 100pF 15kV 1.5kΩ 100pF 330Ω 150pF 330Ω 150pF 0kΩ 200pF 330Ω 150pF 15kV FIGURE 1. ELECTROSTATIC DISCHARGE TEST 6-4 SP720 100 TA = 25oC SINGLE PULSE 2.5 TA = 25oC SINGLE PULSE 80 FORWARD SCR CURRENT (mA) FORWARD SCR CURRENT (A) 2 60 1.5 40 1 IFWD EQUIV. SAT. ON THRESHOLD ~ 1.1V 0.5 VFWD 20 0 600 800 1000 FORWARD SCR VOLTAGE DROP (mV) 1200 0 0 1 2 FORWARD SCR VOLTAGE DROP (V) 3 FIGURE 2. LOW CURRENT SCR FORWARD VOLTAGE DROP CURVE FIGURE 3. HIGH CURRENT SCR FORWARD VOLTAGE DROP CURVE +VCC +VCC INPUT DRIVERS OR SIGNAL SOURCES LINEAR OR DIGITAL IC INTERFACE IN 1-7 IN 9-15 TO +VCC V+ SP720 V- SP720 INPUT PROTECTION CIRCUIT (1 OF 14 ON CHIP) FIGURE 4. TYPICAL APPLICATION OF THE SP720 AS AN INPUT CLAMP FOR OVER-VOLTAGE, GREATER THAN 1V BE ABOVE V+ OR LESS THAN -1VBE BELOW V- 6-5 SP720 Peak Transient Current Capability of the SP720 The peak transient current capability rises sharply as the width of the current pulse narrows. Destructive testing was done to fully evaluate the SP720’s ability to withstand a wide range of transient current pulses. The circuit used to generate current pulses is shown in Figure 5. The test circuit of Figure 5 is shown with a positive pulse input. For a negative pulse input, the (-) current pulse input goes to an SP720 ‘IN’ input pin and the (+) current pulse input goes to the SP720 V- pin. The V+ to V- supply of the SP720 must be allowed to float. (i.e., It is not tied to the ground reference of the current pulse generator.) Figure 6 shows the point of overstress as defined by increased leakage in excess of the data sheet published limits. The maximum peak input current capability is dependent on the V+ to V- voltage supply level, improving as the supply voltage is reduced. Values of 0, 5, 15 and 30 voltages are shown. The safe operating range of the transient peak current should be limited to no more than 75% of the measured overstress level for any given pulse width as shown in Figure 6. When adjacent input pins are paralleled, the sustained peak current capability is increased to nearly twice that of a single pin. For comparison, tests were run using dual pin combinations 1+2, 3+4, 5+6, 7+9, 10+11, 12+13 and 14+15. The overstress curve is shown in Figure 6 for a 15V supply condition. The dual pins are capable of 10A peak current for a 10µs pulse and 4A peak current for a 1ms pulse. The complete for single pulse peak current vs. pulse width time ranging up to 1 second are shown in Figure 6. + VG - R1 VARIABLE TIME DURATION CURRENT PULSE GENERATOR CURRENT SENSE (-) (+) 1 IN 2 IN 3 IN 4 IN SP720 5 IN 6 IN 7 IN V+ 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 C1 + - VOLTAGE PROBE R1 ~ 10Ω TYPICAL VG ADJ. 10V/A TYPICAL C1 ~ 100µF 8 V- FIGURE 5. TYPICAL SP720 PEAK CURRENT TEST CIRCUIT WITH A VARIABLE PULSE WIDTH INPUT 10 9 8 7 PEAK CURRENT (A) 6 5 4 3 2 1 0 0.001 0.01 0.1 1 PULSE WIDTH TIME (ms) 10 100 1000 CAUTION: SAFE OPERATING CONDITIONS LIMIT THE MAXIMUM PEAK CURRENT FOR A GIVEN PULSE WIDTH TO BE NO GREATER THAN 75% OF THE VALUES SHOWN ON EACH CURVE. SINGLE PIN STRESS CURVES DUAL PIN STRESS CURVE 0V 5V 30V V+ TO V- SUPPLY 15V 15V FIGURE 6. SP720 TYPICAL SINGLE PULSE PEAK CURRENT CURVES SHOWING THE MEASURED POINT OF OVER-STRESS IN AMPERES vs PULSE TIME IN MILLISECONDS (TA = 25 oC) 6-6 SP720 Dual-In-Line Plastic Packages (PDIP) N E1 INDEX AREA 12 3 N/2 E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL -B- MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 A E A2 L A C L -AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A1 A2 -C- B B1 C D D1 E eA eC C e C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). E1 e eA eB L N 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 6-7 SP720 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D E α µ A1 0.10(0.004) C e B 0.25(0.010) M C AM BS e H h L N 0.050 BSC 0.2284 0.0099 0.016 16 0o 8o 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0o 6.20 0.50 1.27 NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. α 6-8