2SJ451

2SJ451 Silicon P-Channel MOS FET ADE-208-382 1st. Edition Application Low frequency power switching Features • • • • Low on-resistance. Low drive power 2.5 V gate drive device. Small package (MPAK). Outline MPAK 3 1 2 D 1. Source 2. Gate 3. Drain G S 2SJ451 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Channel dissipation Channel temperature Storage temperature Note: 1. PW ≤ 10 µs, duty cycle ≤ 1% Marking is "ZK–". Symbol VDSS VGSS ID I D(pulse)* Pch Tch Tstg 1 Ratings –20 ±20 –0.2 –0.4 150 150 –55 to +150 Unit V V A A mW °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Symbol V(BR)DSS V(BR)GSS Min –20 ±20 — — –0.5 — — 0.13 — — — — — — — Typ — — — — — 2.3 5.0 0.23 2.4 31 0.6 0.17 0.68 3.0 2.8 Max — — –1.0 ±2.0 –1.5 3.5 9.0 — — — — — — — — Unit V V µA µA V Ω Ω S pF pF pF µs µs µs µs Test conditions I D = –100 µA, VGS = 0 I G = ±100 µA, VDS = 0 VDS = –16 V, VGS = 0 VGS = ±16 V, VDS = 0 I D = –10 µA, VDS = –5 V I D = –100 mA VGS = –4 V*1 I D = –40 mA VGS = –2.5 V*1 I D = –100 mA*1 VDS = –10 V VDS = –10 V VGS = 0 f = 1 MHz VGS = –10 V, ID = –0.1 A RL = 100 Ω Zero gate voltage drain current I DSS Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Static drain to source on state resistance Foward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Note: 1. Pulse Test I GSS VGS(off) RDS(on)1 RDS(on)2 |yfs| Ciss Coss Crss t d(on) tr t d(off) tf 2 2SJ451 Maximum Channel Dissipation Curve 200 Pch (mW) I D (A) –1 –0.3 –0.1 –0.03 –0.01 –0.003 –0.001 Maximum Safe Operation Area 1 ms PW 10 = m s pe ra 150 C D O Channel Dissipation Drain Current 100 Operation in this area is limited by R DS(on) tio n 50 Ta = 25 °C –1 –3 –10 –30 –100 V DS (V) Drain to Source Voltage 0 50 100 150 Ta (°C) 200 –0.1 –0.3 Ambient Temperature –0.20 Typical Output Characteristics –10 V –4 V Pulse Test –2.5 V (A) -0.16 –0.20 Typical Transfer Characteristics V DS = –10 V Pulse Test I D (A) –0.16 –0.12 VGS = –2 V ID Drain Current Drain Current –0.12 Tc = 75°C 25°C –25°C –0.08 –0.08 –0.04 –0.04 0 –2 –4 –6 Drain to Source Voltage –8 –10 V DS (V) 0 –1 –2 –3 Gate to Source Voltage –4 –5 V GS (V) 3 2SJ451 Drain to Source Saturation Voltage vs. Gate to Source Voltage V DS(on) (V) Pulse Test Drain to Source On State Resistance R DS(on) ( Ω ) –1.0 Static Drain to Source on State Resistance vs. Drain Current 100 Pulse Test 50 –0.8 Drain to Source Voltage –0.6 20 10 5 –4 V 2 1 –0.01–0.02 VGS = –2.5 V –0.4 I D = –0.2 A –0.1 A –0.05 A –0.2 0 –4 –2 –6 Gate to Source Voltage –8 V GS (V) –10 –0.05 –0.1 –0.2 –0.5 Drain Current I D (A) –1 Static Drain to Source on State Resistance R DS(on) ( Ω) Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance vs. Temperature 10 Pulse Test 8 V GS = –2.5 V –0.1 A 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0.005 Forward Transfer Admittance vs. Drain Current Tc = –25 °C 75 °C 25 °C 6 I D = –0.05 A 4 –0.2 A 2 –4 V –0.05, –0.1 A 0 –40 0.002 –0.01 –0.03 –0.1 –0.3 V DS = –10 V Pulse Test –1 –3 –10 0 40 80 120 Case Temperature Tc (°C) 160 Drain Current I D (A) 4 2SJ451 Typical Capacitance vs. Drain to Source Voltage Coss Switching Time t (µs) Switching Characteristics V GS = –10 V, V DD = –10 V PW = 50 µs, duty < 1 % tf 2 1 0.5 0.2 t d(on) tr t d(off) 100 30 Capacitance C (pF) 10 3 1 0.3 0.1 0 10 5 Ciss Crss VGS = 0 f = 1 MHz –10 –20 –30 –40 –50 Drain to Source Voltage V DS (V) 0.1 –0.01 –0.02 –0.05 –0.1 –0.2 –0.5 Drain Current I D (A) –1 Reverse Drain Current vs. Source to Drain Voltage –0.5 Pulse Test Reverse Drain Current I DR (A) –0.4 –5 V V GS = 0 –0.3 –0.2 –0.1 0 –0.4 –0.8 –1.2 –1.6 –2.0 Source to Drain Voltage V SD (V) 5 2SJ451 Avalanche Test Circuit and Waveform Vin Monitor D.U.T. RL Vout Monitor Vin 10% 90% Vin 50 Ω –10 V V DD = –10 V Vout td(on) 90% 10% tr td(off) 90% 10% tf 6 Unit: mm 0.65 0.10 3 – 0.4 + 0.05 – 0.16 – 0.06 + 0.10 1.5 ± 0.15 + 0.2 – 0.6 0 – 0.1 0.95 0.95 1.9 ± 0.2 2.95 ± 0.2 0.3 + 0.2 1.1 – 0.1 0.65 2.8 Hitachi Code JEDEC EIAJ Weight (reference value) MPAK — Conforms 0.011 g Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: (2) 2718-3666 Fax: (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: (2) 735 9218 Fax: (2) 730 0281 Telex: 40815 HITEC HX Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.