2SJ518

2SJ518 Silicon P Channel MOS FET High Speed Power Switching ADE-208-580B (Z) 3rd. Edition Jun 1998 Features • Low on-resistance R DS(on) = 0.35 Ω typ. at (V GS = –10V, ID = –1A) • Low drive current • 4 V gete drive devices • High speed switching Outline UPAK 3 D 2 1 4 G S 1. Gate 2. Drain 3. Source 4. Drain 2SJ518 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Avalenche current Avalenche energy Channel dissipation Channel temperature Storage temperature Note: Symbol VDSS VGSS ID I D(pulse) I DR I AP Note2 Note1 Ratings –60 ±20 –2 –4 –2 –2 0.34 Unit V V A A A A mJ W °C °C EAR Pch Tch Tstg Note3 1 150 –55 to +150 1. PW ≤ 10 µs, duty cycle ≤ 1 % 2. value at Tch = 25°C, Rg ≥ 50 Ω 3. Value at when using the aluminaceramic board (12.5x20x0.7mm) Electrical Characteristics (Ta = 25°C) Item Symbol Min –60 ±20 — — –1.0 — — 1.2 — — — — — — — — — Typ — — — — — 0.35 0.45 2.0 220 110 35 10 11 45 30 –1.05 50 Max — — –10 ±10 –2.0 0.46 0.63 — — — — — — — — — — Unit V V µA µA V Ω Ω S pF pF pF ns ns ns ns V ns I D = –2A, VGS = 0 I F = –2A, VGS = 0 diF/ dt = 50A/µs Test Conditions I D = –10mA, VGS = 0 I G = ±100µA, VDS = 0 VDS = –60 V, VGS = 0 VGS = ±16V, VDS = 0 I D = –1mA, VDS = –10V I D = –1A, VGS = –10V Note4 I D = –1A, VGS = –4V Note4 I D = –1A, VDS = –10V VDS = –10V VGS = 0 f = 1MHz VGS = –10V, ID = –1A RL = 30Ω Note4 Drain to source breakdown voltage V(BR)DSS Gate to source breakdown voltage V(BR)GSS Zero gate voltege drain current Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time I DSS I GSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss t d(on) tr t d(off) tf Body–drain diode forward voltage VDF Body–drain diode reverse recovery time Note: 4. Pulse test 5. Marking is “AZ” t rr 2 2SJ518 Main Characteristics Power vs. Temperature Derating 2.0 –100 Maximum Safe Operation Area Pch (W) I D (A) Test Condition : When using the aliminium Ceramic board (12.5 x 20 x 70 mm) 1.5 –30 –10 100 µs –3 –1 –0.3 –0.1 –0.03 –0.01 Channel Dissipation Drain Current 1.0 0.5 1 m s = 10 DC (1 m Op sh s ot) er at Operation in ion this area is limited by R DS(on) PW Ta = 25 °C 0 50 100 150 Ta (°C) 200 Ambient Temperature –0.1 –0.3 –1 –3 –10 –30 –100 Drain to Source Voltage V DS (V) Typical Output Characteristics –5 –10 V –5 –6 V –5 V –4 V –3 Pulse Test Typical Transfer Characteristics V DS = –10 V Pulse Test I D (A) –3.5 V I D (A) Drain Current –4 –4 –3 Drain Current –2 –3 V –1 VGS = –2.5 V 0 –2 –4 –6 Drain to Source Voltage –8 –10 V DS (V) –2 Tc = 75 °C –1 –25 °C 0 –1 –2 –3 Gate to Source Voltage –4 –5 V GS (V) 25 °C 3 2SJ518 Drain to Source Saturation Voltage vs. Gate to Source Voltage Drain to Source Saturation Voltage V DS(on) (V) Pulse Test Drain to Source On State Resistance R DS(on) ( Ω ) –5 Static Drain to Source on State Resistance vs. Drain Current 10 5 –4 –3 2 1 0.5 VGS = –4 V –10 V 0.2 0.1 –0.1 –0.2 Pulse Test –0.5 –1 –2 –5 Drain Current I D (A) –10 –2 –1 –0.5 A I D = –2 A –1 A 0 –4 –8 –12 Gate to Source Voltage –16 –20 V GS (V) Static Drain to Source on State Resistance R DS(on) ( Ω) Forward Transfer Admittance |y fs | (S) Static Drain to Source on State Resistance vs. Temperature 1.0 Pulse Test 0.8 I D = –2 A –0.5, –1 A Forward Transfer Admittance vs. Drain Current 10 5 Ta = –25 °C 2 1 0.5 75 °C 25 °C 0.6 V GS = –4 V 0.4 –10 V –2 A –0.5, –1 A 0.2 0 –40 0.2 0.1 –0.1 –0.2 V DS = –10 V Pulse Test –0.5 –1 –2 –5 Drain Current I D (A) –10 0 40 80 120 160 Case Temperature Tc (°C) 4 2SJ518 Body–Drain Diode Reverse Recovery Time 100 1000 300 100 30 Crss 10 3 1 0 Ciss Coss Typical Capacitance vs. Drain to Source Voltage Reverse Recovery Time trr (ns) 50 20 di / dt = 50 A / µs VGS = 0, Ta = 25 °C Capacitance C (pF) 10 –0.1 –0.2 –0.5 –1 –2 –5 –10 Reverse Drain Current I DR (A) VGS = 0 f = 1 MHz –10 –20 –30 –40 –50 Drain to Source Voltage V DS (V) Dynamic Input Characteristics Switching Characteristics V DS (V) Switching Time t (ns) –20 V DD = –10 V –25 V –50 V V GS (V) 0 0 100 50 t d(off) tf t d(on) 10 5 tr –4 Drain to Source Voltage –40 V DS V GS –80 –60 V DD = –10 V –25 V –50 V –8 –12 –16 –20 20 Gate to Source Voltage 20 2 1 –0.1 –0.2 I = –2 A –100 D 0 16 4 8 12 Gate Charge Qg (nc) V GS = –10 V, V DD = –30 V Ta = 25°C, duty < 1 % –0.5 –1 –2 –5 Drain Current I D (A) –10 5 2SJ518 Reverse Drain Current vs. Source to Drain Voltage Pulse Test Reverse Drain Current I DR (A) Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating 0.5 I AP = –2 A V DD = –25 V duty < 0.1 % Rg > 50 Ω –5 –4 0.4 –3 –10 V –5 V V GS = 0, 5 V 0.3 –2 0.2 –1 0.1 0 25 0 –0.4 –0.8 –1.2 –1.6 –2.0 Source to Drain Voltage V SD (V) 50 75 100 125 150 Channel Temperature Tch (°C) Avalanche Test Circuit EAR = Avalanche Waveform 1 2 • L • I AP • 2 VDSS VDSS – V DD V DS Monitor L I AP Monitor V (BR)DSS I AP VDD ID V DS Rg Vin –15 V D. U. T 50 Ω 0 VDD 6 2SJ518 Switching Time Test Circuit Vin Monitor D.U.T. RL 90% Vin –10 V 50 Ω V DD = –30 V Vout td(on) 90% 10% tr td(off) 90% 10% tf Vout Monitor Vin 10% Waveform 7 2SJ518 Package Dimensions Unit: mm 4.5 ± 0.1 0.4 1.8 max 1.5 ± 0.1 0.44 max f1 1.5 1.5 3.0 0.8 min 0.53 max 0.48 max 1 2 3 2.5 ± 0.1 4.25 max 4 0.44 max Hitachi Code EIAJ JEDEC UPAK SC–62 UPAK 8 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. 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Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. 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Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: (2) 2718-3666 Fax: (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: (2) 735 9218 Fax: (2) 730 0281 Telex: 40815 HITEC HX Copyright ' Hitachi, Ltd., 1999. All rights reserved. Printed in Japan.