2SJ528

2SJ528(L),2SJ528(S) Silicon P Channel MOS FET High Speed Power Switching ADE-208-641A (Z) 2nd. Edition Jun 1998 Features • Low on-resistance RDS(on) = 0.17 Ω typ. • 4 V gete drive devices • High speed switching Outline DPAK–2 4 D 4 12 G 3 12 S 3 1. Gate 2. Drain 3. Source 4. Drain 2SJ528(L),2SJ528(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Avalenche current Avalenche energy Channel dissipation Channel temperature Storage temperature Note: Symbol VDSS VGSS ID I D(pulse) I DR I AP Note3 Note3 Note2 Note1 Ratings –60 ±20 –7 –28 –7 –7 4.2 20 150 –55 to +150 Unit V V A A A A mJ W °C °C EAR Pch Tch Tstg 1. PW ≤ 10 µs, duty cycle ≤ 1 % 2. Value at Tc = 25°C 3. Value at Tch = 25°C, Rg ≥ 50 Ω Electrical Characteristics (Ta = 25°C) Item Symbol Min –60 ±20 — — –1.0 — — 3.0 — — — — — — — — — Typ — — — — — 0.17 0.24 5.0 400 220 75 10 40 75 65 –1.1 65 Max — — –10 ±10 –2.0 0.22 0.37 — — — — — — — — — — Unit V V µA µA V Ω Ω S pF pF pF ns ns ns ns V ns I F = –7A, VGS = 0 I F = –7A, VGS = 0 diF/ dt = 50A/µs Test Conditions I D = –10mA, VGS = 0 I G = ±100µA, VDS = 0 VDS = –60 V, VGS = 0 VGS = ±16V, VDS = 0 I D = –1mA, VDS = –10V I D = –4A, VGS = –10V Note4 I D = –4A, VGS = –4V Note4 I D = –4A, VDS = –10V VDS = –10V VGS = 0 f = 1MHz VGS = –10V, ID = –4A RL = 7.5Ω Note4 Drain to source breakdown voltage V(BR)DSS Gate to source breakdown voltage V(BR)GSS Zero gate voltege drain current Gate to source leak current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time I DSS I GSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss t d(on) tr t d(off) tf Body–drain diode forward voltage VDF Body–drain diode reverse recovery time Note: 4. Pulse test t rr 2 2SJ528(L),2SJ528(S) Main Characteristics Power vs. Temperature Derating 40 Pch (W) I D (A) –100 –30 –10 DC PW = Maximum Safe Operation Area 10 µs 10 10 30 1 0 Channel Dissipation 20 Drain Current –3 –1 –0.3 –0.1 –0.03 –0.01 Op Operation in this area is limited by R DS(on) ms s er (1 ati sh on ot) (T c= 25 ·C ) m µs 10 Ta = 25 °C 0 50 100 Case Temperature 150 Tc (°C) 200 –0.1 –0.3 –1 –3 –10 –30 –100 Drain to Source Voltage V DS (V) Typical Output Characteristics –10 –4 V –10 V –6 V –5 V –10 Pulse Test (A) –8 Typical Transfer Characteristics V DS = –10 V Pulse Test I D (A) –8 –3.5 V ID –3 V Drain Current –6 Drain Current –6 –4 –4 Tc = 75 °C 25 °C –25 °C –2 VGS = –2.5 V –2 0 –2 –4 –6 Drain to Source Voltage –8 –10 V DS (V) 0 –1 –2 –3 Gate to Source Voltage –4 –5 V GS (V) 3 2SJ528(L),2SJ528(S) Drain to Source Saturation Voltage vs. Gate to Source Voltage –2.0 Drain to Source Saturation Voltage V DS(on) (V) Drain to Source On State Resistance R DS(on) ( Ω ) Pulse Test Static Drain to Source on State Resistance vs. Drain Current 1 0.5 VGS = –4 V –1.6 0.2 0.1 0.05 –10 V –1.2 –0.8 –5 A –2 A –1 A –0.4 0.02 0.01 –0.1 –0.3 –1 –3 Pulse Test –10 –30 –100 0 –4 –8 –12 Gate to Source Voltage –16 –20 V GS (V) Drain Current I D (A) Static Drain to Source on State Resistance R DS(on) ( Ω) Forward Transfer Admittance |y fs | (S) Static Drain to Source on State Resistance vs. Temperature 0.5 Pulse Test –2 A 0.4 I D = –5 A –1 A 0.3 V GS = –4 V –5 A -1,–2 A 100 30 10 Forward Transfer Admittance vs. Drain Current Ta = –25 °C 3 1 0.3 0.1 –0.1 –0.3 75 °C V DS = –10 V Pulse Test –1 –3 –10 –30 Drain Current I D (A) –100 25 °C 0.2 –10 V 0.1 0 –40 0 40 80 120 160 Case Temperature Tc (°C) 4 2SJ528(L),2SJ528(S) Body–Drain Diode Reverse Recovery Time Typical Capacitance vs. Drain to Source Voltage VGS = 0 f = 1 MHz 500 5000 Reverse Recovery Time trr (ns) Capacitance C (pF) 200 100 50 1000 Ciss 300 Coss 100 30 Crss 20 10 5 –0.1 di / dt = 50 A / µs VGS = 0, Ta = 25 °C –1 –10 –20 –0.3 –3 Reverse Drain Current I DR (A) 10 0 –10 –20 –30 –40 –50 Drain to Source Voltage V DS (V) Dynamic Input Characteristics Switching Characteristics V DS (V) –20 –4 Switching Time t (ns) V DD = –10 V –25 V –50 V V GS (V) 0 0 I D = –7 A 1000 300 100 30 10 3 1 –0.1 tf tr t d(on) V GS = –10 V, V DD = –30 V Pw = 5 µs, duty < 1 % t d(off) Drain to Source Voltage –40 V DS V GS V DD = –10 V –25 V –50 V –8 –60 –12 –80 –100 0 –16 –20 40 32 8 16 24 Gate Charge Qg (nc) Gate to Source Voltage –0.3 –1 –3 –10 –20 Drain Current I D (A) 5 2SJ528(L),2SJ528(S) Reverse Drain Current vs. Source to Drain Voltage Pulse Test Reverse Drain Current I DR (A) –8 Repetitive Avalanche Energy EAR (mJ) Maximum Avalanche Energy vs. Channel Temperature Derating I AP = –7 A V DD = –25 V duty < 0.1 % Rg ≥ 50 Ω –10 10 8 –6 –10 V –4 –5 V V GS = 0, 5 V 6 4 –2 2 0 25 0 –0.4 –0.8 –1.2 –1.6 –2.0 50 75 100 125 150 Source to Drain Voltage V SD (V) Channel Temperature Tch (°C) Avalanche Test Circuit EAR = Avalanche Waveform 1 2 • L • I AP • 2 VDSS VDSS – V DD V DS Monitor L I AP Monitor V (BR)DSS I AP VDD ID V DS Rg Vin –15 V D. U. T 50 Ω 0 VDD 6 2SJ528(L),2SJ528(S) Normalized Transient Thermal Impedance vs. Pulse Width 3 Normalized Transient Thermal Impedance γ s (t) Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 0.05 0.02 1 0.1 θ ch – c(t) = γ s (t) • θ ch – c θ ch – c = 6.25 °C/W, Tc = 25 °C uls e PDM PW T 0.03 0.0 1s h P ot D= PW T 0.01 10 µ 100 µ 1m 10 m Pulse Width 100 m PW (S) 1 10 Switching Time Test Circuit Vin Monitor D.U.T. RL Vout Monitor Vin 10% Waveform 90% Vin –10 V 50 Ω V DD = –30 V Vout td(on) 90% 10% tr td(off) 90% 10% tf 7 2SJ528(L),2SJ528(S) Package Dimensions Unit: mm 1.7 ± 0.5 6.5 ± 0.5 5.4 ± 0.5 2.3 ± 0.2 0.55 ± 0.1 5.5 ± 0.5 1.7 ± 0.5 1.15 ± 0.1 0.8 ± 0.1 3.1 ± 0.5 16.2 ± 0.5 4.7 ± 0.5 6.5 ± 0.5 5.4 ± 0.5 2.3 ± 0.5 0.55 ± 0.1 5.5 ± 0.5 9.5 ± 0.5 1.2 Max 1.15 ± 0.1 0.8 ± 0.1 2.29 ± 0.5 0.55 ± 0.1 2.5 ± 0.5 0 ~ 0.25 0.55 ± 0.1 2.29 ± 0.5 2.29 ± 0.5 1.2 typ 2.29 ± 0.5 L type S type Hitachi EIAJ ( L type) EIAJ ( S type) JEDEC DPAK–2 SC–63 SC–64 — 8 Cautions 1. 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