HAT1021R

HAT1021R Silicon P Channel Power MOS FET High Speed Power Switching ADE-208-475 D (Z) 5th. Edition February 1999 Features • • • • Low on-resistance Capable of 2.5 V gate drive Low drive current High density mounting Outline SOP–8 8 5 76 56 7 8 DD D D 3 12 4 4 G 1, 2, 3 Source 4 Gate 5, 6, 7, 8 Drain SSS 123 HAT1021R Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Symbol VDSS VGSS ID I D(pulse) Note1 Ratings – 20 ± 10 – 5.5 – 44 – 5.5 Unit V V A A A W °C °C Body–drain diode reverse drain current I DR Channel dissipation Channel temperature Storage temperature Note: Pch Tch Tstg Note2 2.5 150 –55 to +150 1. PW ≤ 10 µs, duty cycle ≤ 1 % 2. When using the glass epoxy board (FR4 40 x 40 x 1.6 mm), PW≤ 10s Electrical Characteristics (Ta = 25°C) Item Symbol Min – 20 ± 10 — — – 0.5 — — 6 — — — — — — — — — Typ — — — — — 0.048 0.065 9.5 1200 630 200 20 120 175 140 – 0.9 65 Max — — ± 10 – 10 – 1.5 0.060 0.085 — — — — — — — — – 1.4 — Unit V V µA µA V Ω Ω S pF pF pF ns ns ns ns V ns IF = – 5.5 A, VGS = 0 Note3 IF = – 5.5 A, VGS = 0 diF/ dt = 20 A/µs Test Conditions I D = – 10 mA, VGS = 0 I G = ± 100 µA, VDS = 0 VGS = ± 8 V, VDS = 0 VDS = – 20 V, VGS = 0 VDS = –10 V, I D = – 1 mA I D = – 3 A, VGS = – 4 V Note3 I D = – 3 A, VGS = – 2.5 V Note3 I D = – 3 A, VDS = – 10 V Note3 VDS = – 10 V VGS = 0 f = 1MHz VGS = – 4 V, ID = – 3 A VDD ≅ – 10 V Drain to source breakdown voltage V(BR)DSS Gate to source breakdown voltage V(BR)GSS Gate to source leak current Zero gate voltege drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Body–drain diode forward voltage Body–drain diode reverse recovery time Note: 3. Pulse test I GSS I DSS VGS(off) RDS(on) RDS(on) |yfs| Ciss Coss Crss t d(on) tr t d(off) tf VDF t rr 2 HAT1021R Main Characteristics Power vs. Temperature Derating 4.0 Pch (W) Test Condition : When using the glass epoxy board (FR4 40x40x1.6 mm), PW < 10 s 3.0 –100 I D (A) –30 –10 –3 –1 Maximum Safe Operation Area 10 µs PW 1 100 µs m s DC Op = Drain Current Channel Dissipation er 10 ati 2.0 on ms 1.0 –0.3 Operation in this area is –0.1 limited by R DS(on) (P No W te