HB56SW3272ESK

HB56SW3272ESK-5/6 256MB Buffered EDO DRAM DIMM 32-Mword × 72-bit, 4k Refresh, 2 Bank Module (36 pcs of 16M × 4 components) ADE-203-872B (Z) Rev. 1.0 June 23, 1998 Description The HB56SW3272ESK belong to 8-byte DIMM (Dual in-line Memory Module) family , and have been developed an optimized main memory solution for 4 and 8-byte processor applications. The HB56SW3272ESK is 32 M × 72 Dynamic RAM Module, mounted 36 pieces of 64-Mbit DRAM (HM5165405) sealed in TCP package and 2 pieces of 16-bit BiCMOS line driver sealed in TSSOP package. The HB56SW3272ESK offer Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56SW3272ESK are 168-pin socket type package (dual lead out). Therefore, the HB56SW3272ESK make high density mounting possible without surface mount technology. The HB56SW3272ESK provide common data inputs and outputs. Decoupling capacitors are mounted beside each TCP on its module board. Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. Features • 168-pin socket type package (Dual lead out)  Lead pitch : 1.27 mm • Single 3.3 V supply (±0.3 V) • High speed  Access time: tRAC = 50 ns/60 ns (max)  Access time: tCAC = 18 ns/20 ns (max) • Low power dissipation  Active mode: 8.78 W/7.49 W (max)  Standby mode (TTL): 295.2 mW (max) • JEDEC standard outline buffered 8-byte DIMM • Buffered input except RAS and DQ HB56SW3272ESK-5/6 • • • • 4-byte interleave enabled, dual address input (A0/B0) EDO page mode capability 4096 refresh cycles: 64 ms 2 variations of refresh  RAS -only refresh  CAS -before-RAS refresh Ordering Information Type No. HB56SW3272ESK-5 HB56SW3272ESK-6 Access time 50 ns 60 ns Package 168-pin dual lead out socket type Contact pad Gold Pin Arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin 2 HB56SW3272ESK-5/6 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal name Pin No. VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC NC VCC WE0 CE 0 NC RE 0 OE0 VSS A0 A2 A4 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 Signal name Pin No. VSS OE2 RE 2 CE 4 NC WE2 VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 Signal name Pin No. VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS NC NC VCC NC CE 1 NC RE 1 NC VSS A1 A3 A5 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 Signal name VSS NC RE 3 CE 5 NC PDE VCC NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 DQ71 3 HB56SW3272ESK-5/6 Pin Arrangement (cont) Pin No. 36 37 38 39 40 41 42 Signal name Pin No. A6 A8 A10 NC VCC NC NC 78 79 80 81 82 83 84 Signal name Pin No. VSS PD1 PD3 PD5 PD7 ID0 (VSS) VCC 120 121 122 123 124 125 126 Signal name Pin No. A7 A9 A11 NC VCC NC B0 162 163 164 165 166 167 168 Signal name VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC Pin Description Pin name A0 to A11, B0 Function Address input Row address (D0 to D35) Column address (D0 to D35) Refresh address (D0 to D35) DQ0 to DQ71 RE 0 to RE 3 CE 0, CE 1, CE 4, CE 5 WE0, WE2 OE0, OE2 PD1 to PD8 ID0 , ID1 PDE VCC VSS NC Data input/output Row address strobe ( RAS ) Column address strobe ( CAS ) Read/Write enable Output enable Presence detect ID bit Presence detect enable Power supply Ground No connection A0 to A11, B0 A0 to A11, B0 A0 to A11, B0 4 HB56SW3272ESK-5/6 Presence Detect Pin Assignment (Controlled by PDE pin) PDE = Low Pin name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Pin No. 79 163 80 164 81 165 82 166 50 ns 1 0 0 0 1 0 0 0 60ns 1 0 0 0 1 1 1 0 PDE = High All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Note: 1: High level (driver output). 0: Low level (driver output) 5 HB56SW3272ESK-5/6 Block Diagram CE1 RE3 RE2 CE4 WE2 OE2 OE DQ36 DQ37 DQ38 DQ39 OE DQ40 DQ41 DQ42 DQ43 OE DQ44 DQ45 DQ46 DQ47 OE DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CE5 RE1 RE0 CE0 WE0 OE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 I/O I/O I/O CAS RAS WE OE D0 I/O I/O I/O I/O I/O I/O I/O CAS RAS WE D18 I/O I/O I/O I/O CAS RAS WE OE I/O I/O D9 I/O I/O CAS RAS WE OE I/O I/O D10 I/O I/O CAS RAS WE OE I/O I/O D11 I/O I/O CAS RAS WE OE I/O I/O D12 I/O I/O CAS RAS WE OE I/O I/O D13 I/O I/O CAS RAS WE OE I/O I/O D14 I/O I/O CAS RAS WE OE I/O I/O D15 I/O I/O CAS RAS WE OE I/O I/O D16 I/O I/O CAS RAS WE OE I/O I/O D17 I/O I/O CAS RAS WE OE I/O I/O D27 I/O I/O CAS RAS WE OE I/O I/O D28 I/O I/O CAS RAS WE OE I/O I/O D29 I/O I/O CAS RAS WE OE I/O I/O D30 I/O I/O CAS RAS WE OE I/O I/O D31 I/O I/O CAS RAS WE OE I/O I/O D32 I/O I/O CAS RAS WE OE I/O I/O D33 I/O I/O CAS RAS WE OE I/O I/O D34 I/O I/O CAS RAS WE OE I/O I/O D35 I/O I/O CAS RAS WE OE D1 CAS RAS WE D19 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE D2 CAS RAS WE D20 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE D3 CAS RAS WE D21 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE D4 CAS RAS WE OE D22 I/O I/O I/O I/O I/O CAS RAS WE OE D5 I/O I/O I/O I/O CAS RAS WE OE I/O DQ56 I/O DQ57 D23 I/O DQ58 I/O I/O I/O I/O DQ59 DQ60 DQ61 DQ62 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 DQ71 CAS RAS WE OE D6 CAS RAS WE OE D24 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE D7 CAS RAS WE OE D25 I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS WE OE D8 CAS RAS WE OE D26 I/O I/O PD1 to PD8 A0 B0 A1 to A11 VCC VSS Capacitor × 20 pcs D0 to D8 , D18 to D26 D9 to D17 , D27 to D35 D0 to D35 D0 to D35, 16-bit driver D0 to D35, 16-bit driver VSS or VCC PD1 to PD8 * D0 to D35 : HM5165405 : 16-bit driver 6 HB56SW3272ESK-5/6 Absolute Maximum Ratings Parameter Terminal voltage on any pin relative to V SS Power supply voltage relative to V SS Short circuit output current Power dissipation Storage temperature range Symbol VT VCC Iout PT Tstg Value –0.5 to +4.6 –0.5 to +4.6 50 19 –55 to +125 Unit V V mA W °C DC Operating Conditions Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Ambient illuminance VIH VIL Ta — Min 3.0 0 2.0 –0.3 0 — Typ 3.3 0 — — — — Max 3.6 0 VCC + 0.3 0.8 70 100 Unit V V V V °C lx Notes 1, 2 2 1 1 Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 7 HB56SW3272ESK-5/6 DC Characteristics 50 ns Parameter Operating current* , * 2 1 60 ns Max 2440 82 Min — — Max 2080 82 Unit mA mA Test conditions t RC = min TTL interface RAS , CAS = VIH Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = tHPC min 0 V ≤ Vin ≤ VCC + 0.3 V 0 V ≤ Vout ≤ VCC Dout = disable High Iout = –2 mA Low Iout = 2 mA Symbol Min I CC1 I CC2 — — Standby current — 28 — 28 mA RAS -only refresh current*2 Standby current* 1 I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL — — — — –10 –10 2.4 0 2440 190 2440 2080 10 10 VCC 0.4 — — — — –10 –10 2.4 0 2080 190 2080 1900 10 10 VCC 0.4 mA mA mA mA µA µA V V CAS -before-RAS refresh current EDO page mode current*1, * 3 Input leakage current Output leakage current Output high voltage Output low voltage Notes : 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC . Capacitance (Ta = 25°C, VCC = 3.3 V ±0.3 V) Parameter Input capacitance (Address) Input capacitance (CAS , WE, OE) Input capacitance (RAS ) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ — — — — Max 20 20 78 27 Unit pF pF pF pF Notes 1 1 1 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 8 HB56SW3272ESK-5/6 AC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ±0.3 V, VSS = 0 V) *1, *2 , *19 Test Conditions • • • • • • Input rise and fall time: 2 ns Input levels: VIL = 0 V, V IH = 3 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Ambient illuminance: Under 100 lx Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) 50 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT 84 30 8 50 8 5 8 0 8 12 10 18 35 10 18 0 0 2 Max — — — 10000 10000 — — — — 32 20 — — — — — — 50 60 ns Min 104 40 10 60 10 5 10 0 10 14 12 20 40 10 20 0 0 2 Max — — — 10000 10000 — — — — 40 25 — — — — — — 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 Notes 9 HB56SW3272ESK-5/6 Read Cycle 50 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol Min t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD — — — — 0 0 50 0 30 15 2 3 3 — — 18 3 — — 18 13 Max 50 18 30 18 — — — — — — — — — 18 18 — — 13 18 — — 60 ns Min — — — — 0 0 60 0 35 18 2 3 3 — — 20 3 — — 20 15 Max 60 20 35 20 — — — — — — — — — 20 20 — — 15 20 — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 21 13 5 21 13, 21 13 21 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 Write Cycle 50 ns Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol Min t WCS t WCH t WP t RWL t CWL t DS t DH 0 8 8 18 8 0 13 Max — — — — — — — 60 ns Min 0 10 10 20 10 0 15 Max — — — — — — — Unit ns ns ns ns ns ns ns 15 15 Notes 14 10 HB56SW3272ESK-5/6 Read-Modify-Write Cycle 50 ns Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol Min t RWC t RWD t CWD t AWD t OEH 116 72 30 42 13 Max — — — — — 60 ns Min 140 84 34 49 15 Max — — — — — Unit ns ns ns ns ns 14 14 14 Notes Refresh Cycle 50 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min t CSR t CHR t WRP t WRH t RPC 10 8 5 10 5 Max — — — — — 60 ns Min 10 10 5 10 5 Max — — — — — Unit ns ns ns ns ns Notes EDO Page Mode Cycle 50 ns Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge Write pulse width during CAS precharge OE precharge time Symbol Min t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC t WPE t OEP 20 — — 33 3 8 5 28 8 8 Max — 60 ns Min 25 Max — Unit ns Notes 20 16 9, 17 100000 — 33 — — — — — — — — 40 3 10 5 35 10 10 100000 ns 40 — — — — — — — ns ns ns ns ns ns ns ns 9, 22 11 HB56SW3272ESK-5/6 EDO Page Mode Read-Modify-Write Cycle 50 ns Parameter EDO page mode read- modify-write cycle time WE delay time from CAS precharge Symbol Min t HPRWC t CPW 57 45 Max — — 60 ns Min 68 54 Max — — Unit ns ns 14 Notes Refresh Parameter Refresh period Symbol t REF Max 64 Unit ms Notes 4096 cycles Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that t RAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 12 HB56SW3272ESK-5/6 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large V CC/V SS line noise, which causes to degrade V IH min/VIL max level. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value. The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS . Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between t OHR and t OH and between tOFR and t OFF. 22. t DOH defines the time at which the output level go cross. V OL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 13 HB56SW3272ESK-5/6 Timing Waveforms*23 Read Cycle tRC tRAS RAS tCSH tT tRCD tRSH tCAS tCRP tRP CAS tRAD tASR tRAH tASC tRAL tCAL tCAH Address Row Column tRRH tRCHR tRCS tRCH WE tDZC tWED tCDD tRDD Din High-Z tDZO tOEA tOED OE tCAC tAA tRAC tCLZ tOEZ tOHO tOFF tOH tOFR tOHR tWEZ Dout Dout 14 HB56SW3272ESK-5/6 Early Write Cycle tRC tRAS tRP RAS tCSH tRCD tT CAS tRSH tCAS tCRP tASR tRAH tASC tCAH Address Row Column tWCS tWCH WE tDS tDH Din Din Dout High-Z* * t WCS t WCS (min) 15 HB56SW3272ESK-5/6 Delayed Write Cycle*18 tRC tRAS tRP RAS tCSH tRCD tT CAS tASR tRAH tASC tCAH tRSH tCAS tCRP Address Row Column tCWL tRCS tRWL tWP WE tDZC tDS tDH Din High-Z Din tOED tOEP tDZO tOEH OE tOEZ tCLZ High-Z Invalid Dout Dout 16 HB56SW3272ESK-5/6 Read-Modify-Write Cycle*18 tRWC tRAS RAS tT tRCD tCAS tCRP tRP CAS tRAD tASR tRAH tASC tCAH Address Row tRCS Column tCWD tAWD tRWD tCWL tRWL tWP WE tDZC tDH tDS High-Z Din Din tOED tOEH  tDZO tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ 17 HB56SW3272ESK-5/6 RAS-Only Refresh Cycle tRC tRAS RAS tRP tT tCRP CAS tRPC tCRP tASR Address tRAH Row tOFR tOFF Dout High-Z 
18 HB56SW3272ESK-5/6 CAS-Before-RAS Refresh Cycle tRC tRP tRAS tRP tRAS tRC tRP RAS tT tRPC tCP tCSR tCHR tRPC tCP tCSR tCHR tCRP CAS tWRP WE tWRH tWRP tWRH Address tOFR tOFF Dout High-Z 
19 HB56SW3272ESK-5/6 EDO Page Mode Read Cycle (1) t RP RAS t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC t HPC t CPRH t CP t t CRP RSH CAS tCAS t RRH t RCH WE tASR Address tRAH tASC Row tCAH t WPE t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED Column 1 t CAL tDZC t CAL tRDD tCDD Din High-Z tDZO tCOL t OEP tOEP tCOP tOED OE tOEA tCAC tAA tCPA tAA tCAC tOEZ tOHO tOEA tCPA tCPA tAA tCAC tAA tOEZ tCAC tOFR tOHR tOEZ tOHO tOFF tOH
tWEZ tRAC tDOH tOHO tOEA Dout Dout 1 Dout 2 Dout 2 Dout 3 Dout 4 20 HB56SW3272ESK-5/6 EDO Page Mode Read Cycle (2) t RP RAS t RASP t HPC t CAS tHPC t CP t CAS t RCHC t RCS t CP t HPC tRSH tCAS t RRH t RCH t CRP tT CAS t CSH t CAS t CP WE tASR Address tRAH tASC Row tCAH t ASC t CAH Column 2 t CAL t ASC t CAH Column 3 t CAL tASC t RAL t CAH Column 4 t WED Column 1 t CAL tDZC t CAL tRDD tCDD Din High-Z tDZO tCOL t OEP tOEP tCOP tOED OE tOEA tCAC tAA tCPA tAA tCAC tOEZ tOHO
 tOEZ tRAC tDOH tOEA tCAC tDOH tOHO tOEA Dout tCPA tAA tCAC tCPA tAA tOFR tOHR tOEZ tOHO tOFF tOH Dout 1 Dout 2 Dout 2 Dout 3 Dout 4 21 HB56SW3272ESK-5/6 EDO Page Mode Early Write Cycle tRASP tRP RAS tT tRCD CAS tCSH tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP tASR tRAH tASC tCAH tASC tCAH tASC tCAH Address Row Column 1 Column 2 Column N tWCS tWCH tWCS tWCH tWCS tWCH WE tDS tDH tDS tDH tDS tDH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) 22 HB56SW3272ESK-5/6 EDO Page Mode Delayed Write Cycle*18 tRASP tRP RAS tT tCSH tRCD CAS tRAD tASR tRAH Address Row tASC tCAH Column 1 tCWL tRCS WE tWP tDZC tDS tDH Din tDZO tOED tOEP tOEH OE Din 1 tDZO tWP tDZC tDS tDH Din 2 tOED tOEP tOEH tDZO tWP tDZC tDS tDH Din N tOED tOEP tOEH tRCS tASC tCAH Column 2 tCWL tRCS tASC tCAH Column N tCWL tRWL tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP
 tCLZ tCLZ tCLZ tOEZ tOEZ Dout Invalid Dout Invalid Dout Invalid Dout tOEZ High-Z 23 HB56SW3272ESK-5/6 EDO Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t CP t RCD CAS t HPRWC t CP t CAS t CAS t RSH t CAS t CRP t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DS t DZC t DH Din t DZO t OED t OEP t OEH Din 1 t DZO t OED t OEP t OEH t WP t DS t DZC t DH Din 2 t DZO t OED t OEP t OEH t WP t DS t DZC t DH Din N t CWL t RCS t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL Address OE t OHO t OHO t OHO t OEA t CAC t OEA t CAC t OEA t CAC

 t AA t RAC t AA t CPA t AA t CPA t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z Dout Dout 1 Dout 2 Dout N 24 HB56SW3272ESK-5/6 EDO Page Mode Mix Cycle (1)*20 t RP RAS t RASP t CRP tCAS tCWL t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL t DS t DH Din 1 High-Z tOED t DS t DH Din 3 tOEP tWED tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS tRSH t RRH t RCH tT CAS t CAS t CSH t RCD t WCS WE t CP t CAS t CP tCAS t CP t WCH tASR Address tASC Column 1 Din  OE tCPA tAA tOEA tCPA tCPA tAA t OEZ tAA tOFR tWEZ tOEZ tCAC tOHO tOFF tOH tCAC t DOH tCAC t OHO tOEA Dout Dout 2 Dout 3 Dout 4 25 HB56SW3272ESK-5/6 EDO Page Mode Mix Cycle (2) * 20 t RP RAS t RASP tT CAS t CSH t CAS t RCD t RCS t RCHR t CP t CAS t CP tCAS tCWL t RCS tCPW t CP tCAS t RCS tWP t RAL tASC t CAH Column 4 t CAL t DS tRSH t CRP t RCH tWCS t WCH t RRH t RCH WE tASR Address t ASC tRAH Row tCAH t ASC t CAH Column 2 t ASC t CAH Column 3 Column 1 t CAL t DS Din t DH Din 2 t DH Din 3 t OEP tOED tCOL tCOP tRDD tCDD High-Z t OEP tOED OE tWED tAA tOEA tCAC tRAC t OHO Dout t OEA tOEZ tCPA tAA tCAC tOEZ t OHO Dout 3 tCPA tAA tCAC tOEA tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4 Dout 1 26 HB56SW3272ESK-5/6 Physical Outline HB56SW3272ESK Series Unit: mm inch 133.35 5.250 3.00 0.118 127.35 5.014 Front side 4.80 0.189 3.00 0.118 Component area (Front) 1 C B 36.83 1.450 54.61 2.150 A 84 8.89 0.350 11.43 0.450 1.27 ± 0.10 0.050 ±0.004 Back side 2 – φ 3.00 2 – φ 0.118 4.00 0.157 17.80 0.701 168 85 Component area (Back) Detail A 2.50 ± 0.20 0.098 ± 0.0079 0.20 ± 0.15 0.0079 ± 0.0059 1.27 0.050 Detail B and C 3.175 0.125 1.00 ± 0.05 0.039 ± 0.002 3.125 ± 0.125 0.123 ± 0.005 6.35 0.250 2.00 ± 0.10 0.079 ± 0.004 38.10 1.500 4.00 min 0.157 min 27 HB56SW3272ESK-5/6 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA. 94005-1897 USA Tel: 800-285-1601 Fax:303-297-0447 Hitachi Europe GmbH Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30-00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 01628-585000 Fax: 01628-585160 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 28 HB56SW3272ESK-5/6 Revision Record Rev. Date 0.0 Contents of Modification (referred to HM5164405/HM5165405 Series Rev. 0.1) 0.1 1.0 Mar. 16, 1998 Change of Block Diagram Change of Physical Outline Jun. 23, 1998 (referred to HM5164405/HM5165405 Series rev. 1.0) General Description Addition of Notes about protection from mechanical defects AC Test condition Addition of Ambient illuminance S. Tsukui K. Tsuneda Drawn by S. Tsukui Approved by K. Tsuneda Jan. 30, 1998 Initial issue 29