HM514170DJ-7

HM514170D, HM514270D Series HM51S4170D, HM51S4270D Series 262,144-word × 16-bit Dynamic RAM ADE-203-672 (Z) Preliminary Rev. 0.0 Oct. 18, 1996 Description The Hitachi HM51(S)4170D, HM51(S)4270D Series are CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51(S)4170D, HM51(S)4270D Series have realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4170D, HM51(S)4270D Series offer fast page mode as a high speed access mode. They have the package variations of standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4170D, HM51S4270D Series self refresh operation. Features • Single 5 V supply: 5 V ± 10% • Access time: 60 ns/70 ns/80 ns (max) • Low power dissipation  Active mode: 825 mW/660 mW/578 mW (max) (HM51(S)4170D Series) 825 mW/770 mW/688 mW (max) (HM51(S)4270D Series)  Standby mode: 11 mW (max) 1.1 mW (max) (L-version) • Fast page mode capability • Refresh cycles  1024 refresh cycles: 16 ms (HM51(S)4170D Series) 128 ms (L-version) (HM51(S)4170DL Series)  512 refresh cycles: 8 ms (HM51(S)4270D Series) 128 ms (L-version) (HM51(S)4270DL Series) • 2 variations of refresh  RAS -only refresh  CAS -before-RAS refresh Preliminary: This document contains information on a new product. Specifications and information contained herein are subject to change without notice. HM51(S)4170D Series, HM51(S)4270D Series • 2 WE -byte control • Self refresh operation (HM51S4170D, HM51S4270D) • Battery backup operation (L-version) Ordering Information Type No. HM514170DJ-6 HM514170DJ-7 HM514170DJ-8 HM514170DLJ-6 HM514170DLJ-7 HM514170DLJ-8 HM514270DJ-6 HM514270DJ-7 HM514270DJ-8 HM514270DLJ-6 HM514270DLJ-7 HM514270DLJ-8 HM51S4170DJ-6 HM51S4170DJ-7 HM51S4170DJ-8 HM51S4170DLJ-6 HM51S4170DLJ-7 HM51S4170DLJ-8 HM51S4270DJ-6 HM51S4270DJ-7 HM51S4270DJ-8 HM51S4270DLJ-6 HM51S4270DLJ-7 HM51S4270DLJ-8 HM514170DTT-6 HM514170DTT-7 HM514170DTT-8 HM514170DLTT-6 HM514170DLTT-7 HM514170DLTT-8 HM514270DTT-6 HM514270DTT-7 HM514270DTT-8 HM514270DLTT-6 HM514270DLTT-7 HM514270DLTT-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 400 mil 44-pin plastic TSOP II (TTP-44/40DB) Package 400-mil 40-pin plastic SOJ (CP-40D) 2 HM51(S)4170D Series, HM51(S)4270D Series Ordering Information (cont) Type No. HM51S4170DTT-6 HM51S4170DTT-7 HM51S4170DTT-8 HM51S4170DLTT-6 HM51S4170DLTT-7 HM51S4170DLTT-8 HM51S4270DTT-6 HM51S4270DTT-7 HM51S4270DTT-8 HM51S4270DLTT-6 HM51S4270DLTT-7 HM51S4270DLTT-8 Access time 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns 60 ns 70 ns 80 ns Package 400 mil 44-pin plastic TSOP II (TTP-44/40DB) 3 HM51(S)4170D Series, HM51(S)4270D Series Pin Arrangement HM514170DJ/DLJ Series HM51S4170DJ/DLJ Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC LWE UWE RAS A9 A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC CAS OE A8 A7 A6 A5 A4 VSS HM514170DTT/DLTT Series HM51S4170DTT/DLTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 (Top view) NC LWE UWE RAS A9 A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC NC CAS OE A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name A0 to A9 Function Address input — Refresh address A0 to A9 — Row address A0 to A9 — Column address A0 to A7 I/O0 to I/O15 Data input/output RAS CAS UWE / LWE OE VCC VSS NC Row address strobe Column address strobe Read/write enable Output enable Power supply Ground No connection 4 HM51(S)4170D Series, HM51(S)4270D Series Pin Arrangement HM514270DJ/DLJ Series HM51S4270DJ/DLJ Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC LWE UWE RAS NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC NC CAS OE A8 A7 A6 A5 A4 VSS HM514270DTT/DLTT Series HM51S4270DTT/DLTT Series VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 (Top view) NC LWE UWE RAS NC A0 A1 A2 A3 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 NC NC CAS OE A8 A7 A6 A5 A4 VSS (Top view) Pin Description Pin name A0 to A8 Function Address input — Refresh address A0 to A8 — Row address A0 to A8 — Column address A0 to A8 I/O0 to I/O15 Data input/output RAS CAS UWE / LWE OE VCC VSS NC Row address strobe Column address strobe Read/write enable Output enable Power supply Ground No connection 5 HM51(S)4170D Series, HM51(S)4270D Series Block Diagram I/O4 I/O4 buffer I/O5 buffer I/O6 buffer I/O7 buffer I/O3 I/O3 buffer I/O2 I/O2 buffer I/O1 I/O1 buffer I/O0 I/O0 buffer I/O15 I/O15 buffer I/O14 I/O14 buffer I/O13 I/O13 buffer I/O12 I/O12 buffer I/O11 buffer I/O11 I/O5 I/O10 I/O10 buffer I/O9 buffer I/O8 buffer I/O9 I/O6 I/O7 I/O8 Selector Selector Selector Selector I/O bus & column decoder I/O bus & column decoder I/O bus & column decoder I/O bus & column decoder 256 k memory array Mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat Row driver Row Row driver driver Row driver Row driver Row Row driver driver Row driver CAS RAS Row decoder & Peripheral circuit 256 k memory array mat UWE LWE OE Row driver Row driver Row Row driver driver Row driver Row driver Row Row driver driver I/O bus & column decoder I/O bus & column decoder I/O bus & column decoder I/O bus & column decoder 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat 256 k memory array mat Row address buffer RA0 to RA9: HM51(S)4170D RA0 to RA8: HM51(S)4270D Column address buffer CA0 to CA7: HM51(S)4170D CA0 to CA8: HM51(S)4270D Address A0 to A9: HM51(S)4170D Address A0 to A8: HM51(S)4270D 6 256 k memory array mat HM51(S)4170D Series, HM51(S)4270D Series Operation Mode The HM51(S)4170D, HM51(S)4270D series has the following 11 operation modes. 1. Read cycle 2. Early write cycle 3. Delayed write cycle 4. Read-modify-write cycle 5. RAS -only refresh cycle 6. CAS -before-RAS refresh cycle 7. Self refresh cycle (HM51S4170D, HM51S4270D) 8. Fast page mode read cycle 9. Fast page mode early write cycle 10. Fast page mode delayed write cycle 11. Fast page mode read-modify-write cycle Inputs RAS H H L L L L L H to L L L L L CAS H L L L L L H L H to L H to L H to L H to L UWE D H H L* L* 2 2 LWE D H H L* L* 2 2 Output Open Valid Valid Open Undefined Valid Open Open Valid Operation Standby Standby Read cycle Early write cycle Delayed write cycle Read-modify-write cycle RAS -only refresh cycle CAS -before-RAS refresh cycle Self refresh cycle Fast page mode read cycle Fast page mode early write cycle Fast page mode delayed write cycle Fast page mode read modify-write cycle H to L D D H L* L* 2 2 H to L D D H L* L* 2 2 Open Undefined Valid H to L H to L Notes: 1. H: High (inactive) L: Low (active) D: H or L 2. t WCS ≥ 0 ns Early write cycle t WCS < 0 ns Delay write cycle 3. Mode is determined by the OR function of the UWE and LWE . (Mode is set by the earliest of UWE and LWE active edge and reset by the latest of UWE and LWE inactive edge.) However write OPERATION and output High-Z control are done independently by each UWE, LWE . 7 HM51(S)4170D Series, HM51(S)4270D Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature range Storage temperature range Symbol VT VCC Iout PT Topr Tstg Value –1.0 to +7.0 –1.0 to +7.0 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Recommended DC Operating Conditions (Ta = 0 to +70 °C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage VIH VIL Min 0 4.5 2.4 –1.0 Typ 0 5.0 — — Max 0 5.5 6.5 0.8 Unit V V V V Notes 2 1, 2 1 1 Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 8 HM51(S)4170D Series, HM51(S)4270D Series DC Characteristics (Ta = 0 to +70 °C, VCC = 5 V ± 10%, VSS = 0 V)*5 (HM51(S)4170D Series) HM514170D, HM51S4170D -6 Parameter Operating current* * Standby current 1, 2 -7 Max Min 135 2 1 — — — -8 Max Min 120 2 1 — — — Max Unit Test conditions 105 2 1 mA RAS , CAS cycling, t RC = min mA TTL interface, RAS, CAS = VIH Dout = High-Z mA CMOS interface RAS , CAS , UWE, LWE , OE ≥ V CC – 0.2 V Dout = High-Z µA CMOS interface RAS , CAS , OE, UWE, LWE ≥ V CC – 0.2 V Dout = High-Z Symbol Min — — — I CC1 I CC2 Standby current (L-version) I CC2 — 200 — 200 — 200 RAS-only refresh current*2 I CC3 — — — — 135 135 150 300 — — — — 120 120 120 300 — — — — 100 100 100 300 mA t RC = min mA t RC = min mA t PC = min µA Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 125 µs t RAS ≤ 1 µs, CAS = VIL LWE , UWE, OE = VIH CAS -before-RAS refresh I CC6 current* 2 Fast page mode current*1, *3 I CC7 I CC10 Battery backup current* (Standby with CBR refresh) (L-version) 4 Self-refresh mode current I CC11 (HM51S4170D) Self-refresh mode current I CC11 (HM51S4170DL) Input leakage current Output leakage current Output high voltage Output low voltage I LI I LO VOH VOL — 1 — 1 — 1 mA CMOS interface RAS , CAS ≤ 0.2 V, Dout = High-Z µA CMOS interface RAS , CAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ 6.5 V 0 V ≤ Vout ≤ 6.5 V Dout = disable High Iout = –5.0 mA Low Iout = 4.2 mA — 200 — 200 — 200 –10 –10 2.4 0 10 10 VCC 0.4 –10 –10 2.4 0 10 10 VCC 0.4 –10 –10 2.4 0 10 10 VCC 0.4 µA µA V V Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH ≥ V CC – 0.2 V, 0 ≤ V IL ≤ 0.2 V, Address can be changed once or less while RAS = VIL. 5. All the V CC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage. 9 HM51(S)4170D Series, HM51(S)4270D Series DC Characteristics (Ta = 0 to +70 °C, VCC = 5 V ± 10%, VSS = 0 V)*5 (HM51(S)4270D Series) HM514270D, HM51S4270D -6 Parameter Operating current* * Standby current 1, 2 -7 Max Min 150 2 1 — — — -8 Max Min 140 2 1 — — — Max Unit Test conditions 125 2 1 mA RAS , CAS cycling, t RC = min mA TTL interface, RAS, CAS = VIH Dout = High-Z mA CMOS interface RAS , CAS , UWE, LWE , OE ≥ V CC – 0.2 V Dout = High-Z µA CMOS interface RAS , CAS , OE, UWE, LWE ≥ V CC – 0.2 V Dout = High-Z Symbol Min — — — I CC1 I CC2 Standby current (L-version) I CC2 — 200 — 200 — 200 RAS-only refresh current*2 I CC3 — — — — 140 140 150 300 — — — — 130 130 130 300 — — — — 110 110 120 300 mA t RC = min mA t RC = min mA t PC = min µA Standby: CMOS interface Dout = High-Z CBR refresh: tRC = 250 µs t RAS ≤ 1 µs, CAS = VIL LWE , UWE, OE = VIH CAS -before-RAS refresh I CC6 current* 2 Fast page mode current*1, *3 I CC7 I CC10 Battery backup current* (Standby with CBR refresh) (L-version) 4 Self-refresh mode current I CC11 (HM51S4270D) Self-refresh mode current I CC11 (HM51S4270DL) Input leakage current Output leakage current Output high voltage Output low voltage I LI I LO VOH VOL — 1 — 1 — 1 mA CMOS interface RAS , CAS ≤ 0.2 V, Dout = High-Z µA CMOS interface RAS , CAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ 6.5 V 0 V ≤ Vout ≤ 6.5 V Dout = disable High Iout = –5.0 mA Low Iout = 4.2 mA — 200 — 200 — 200 –10 –10 2.4 0 10 10 VCC 0.4 –10 –10 2.4 0 10 10 VCC 0.4 –10 –10 2.4 0 10 10 VCC 0.4 µA µA V V Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH ≥ V CC – 0.2 V, 0 ≤ V IL ≤ 0.2 V, Address can be changed once or less while RAS = VIL. 5. All the V CC pins shall be supplied with the same voltage. And all the VSS pins shall be supplied with the same voltage. 10 HM51(S)4170D Series, HM51(S)4270D Series Capacitance (Ta = 25°C, VCC = 5 V ± 10%) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ — — — Max 5 7 10 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *14, *15, *17, *18 Test Conditions • • • • Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.4 V Input levels: 0 V, 3 V Output load: 2 TTL gate + CL (100 pF) (Including scope and jig) 11 HM51(S)4170D Series, HM51(S)4270D Series Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters) HM514170D, HM51S4170D HM514270D, HM51S4270D -6 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Symbol t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t ODD t DZO t DZC tT Min 110 40 60 15 0 10 0 15 20 15 15 60 10 15 0 0 3 Max — — 10000 10000 — — — — 45 30 — — — — — — 50 -7 Min 130 50 70 20 0 10 0 15 20 15 20 70 15 20 0 0 3 Max — — 10000 10000 — — — — 50 35 — — — — — — 50 -8 Min 150 60 80 20 0 10 0 15 20 15 20 80 15 20 0 0 3 Max — — 10000 10000 — — — — 60 40 — — — — — — 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 8 9 22 Notes 12 HM51(S)4170D Series, HM51(S)4270D Series Read Cycle HM514170D, HM51S4170D HM514270D, HM51S4270D -6 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t OFF1 t OFF2 t CDD Min — — — — 0 0 0 30 0 0 15 Max 60 15 30 15 — — — — 15 15 — -7 Min — — — — 0 0 0 35 0 0 15 Max 70 20 35 20 — — — — 15 15 — -8 Min — — — — 0 0 0 40 0 0 15 Max 80 20 40 20 — — — — 15 15 — Unit ns ns ns ns ns ns ns ns ns ns ns 6 6 Notes 2, 3 3, 4, 13 3, 5, 13 3, 22 20 16, 19 16, 19 Write Cycle HM514170D, HM51S4170D HM514270D, HM51S4270D -6 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time CAS to OE delay time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH t COD Min 0 15 10 15 15 0 15 — Max — — — — — — — 0 -7 Min 0 15 10 20 20 0 15 — Max — — — — — — — 0 -8 Min 0 15 10 20 20 0 15 — Max — — — — — — — 0 Unit ns ns ns ns ns ns ns ns Notes 10, 19 20 21 21 21 11, 21 11, 21 22 13 HM51(S)4170D Series, HM51(S)4270D Series Read-Modify-Write Cycle HM514170D, HM51S4170D HM514270D, HM51S4270D -6 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 150 80 35 50 15 Max — — — — — -7 Min 180 95 45 60 20 Max — — — — — -8 Min 200 105 45 65 20 Max — — — — — Unit ns ns ns ns ns 10,19 10,19 10, 19 21 Notes Refresh Cycle HM514170D, HM51S4170D HM514270D, HM51S4270D -6 Parameter CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol Min 10 10 10 10 Max — — — — CAS setup time (CBR refresh cycle) t CSR t CHR t RPC -7 Min 10 10 10 10 Max — — — — -8 Min 10 10 10 10 Max — — — — Unit ns ns ns ns Notes 19 20 19 CAS precharge time in normal mode t CPN Fast Page Mode Cycle HM514170D, HM51S4170D HM514270D, HM51S4270D -6 Parameter Fast page mode cycle time Fast page mode CAS precharge time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol Min Max t PC t CP t RASC t ACP t RHCP 40 10 — — 35 — — -7 Min Max 45 10 — — -8 Min Max 50 10 — — Unit Notes ns ns 12 3, 13 100000 — 35 — — 40 100000 — 40 — — 45 100000 ns 45 — ns ns 14 HM51(S)4170D Series, HM51(S)4270D Series Fast Page Mode Read-Modify-Write Cycle HM514170D, HM51S4170D HM514270D, HM51S4270D -6 Parameter Symbol Min 55 80 Max — — CAS precharge to UWE, LWE delay t CPW time Fast page mode read-modify-write cycle time t PCM -7 Min 65 95 Max — — -8 Min 70 100 Max — — Unit ns ns Notes 21 Refresh (HM51(S)4170D Series) Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 16 128 Unit ms ms Notes 1024 cycles 1024 cycles Refresh (HM51(S)4270D Series) Parameter Refresh period Refresh period (L-version) Symbol t REF t REF Max 8 128 Unit ms ms Notes 512 cycles 512 cycles Self Refresh Mode HM51S4170D, HM51S4270D -6 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol t RASS t RPS t CHS Min 100 110 –50 Max — — — -7 Min 100 130 –50 Max — — — -8 Min 100 150 –50 Max — — — Unit µs ns ns Notes 23, 24, 25, 26 15 HM51(S)4170D Series, HM51(S)4270D Series Notes: 1. AC measurements assume t T = 5 ns. VIH = 3.0 V, VIL = 0.0 V. 2. Assumes that t RCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF. 4. Assumes that t RCD ≥ tRCD (max) and tRAD ≤ tRAD (max). 5. Assumes that t RCD ≤ tRCD (max) and tRAD ≥ tRAD (max). 6. t OFF (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD ≥ tRWD (min), tCWD ≥ t CWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among tAA, t CAC and t ACP. 14. After power up pause for 100 µs, then DRAM initialization requires a minimum of eight RAS-only refresh or eight CAS -before-RAS refresh cycles. If the user will implement CAS -before-RAS timing in their system, then the eight initialization cycles MUST be CAS -before-RAS cycles. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Either t RCH or tRRH must be satisfied for a read cycle. 17. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. 18. A word of data can be written only when UWE and LWE go low at the same time. This implies that early write cycles cannot be combined with delayed write cycles in the same cycles because all data is latched at the fall of the first WE. In other words, staggering the WE signals in one cycle is not permitted. 19. t RCH, t RRH, t WCS , t RWD, t CWD and t AWD are determined by the earlier falling edge of UWE and LWE . 20. t WCH and t RCS are determined by the later rising edge of UWE or LWE . 21. t WP, t RWL, t CWL, t OEH, t DS, t DH and tCPW should be satisfied by both UWE and LWE . 22. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH (min)/VIL (max) level. 23. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If t RASS > 100 µs, then RAS precharge time should use t RPS instead of tRP. 24. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed within 15.6 µs immediately after exiting from and before entering into self refresh mode. 16 HM51(S)4170D Series, HM51(S)4270D Series 25. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 or 512 cycles (1024 cycles: HM51S4170D Series, 512 cycles: HM51S4270D Series) of distributed CBR refresh with 15.6 µs interval should be executed within 16 or 8 ms (16 ms: HM51S4270D Series, 8 ms: HM51S4270D Series) immediately after exiting from and before entering into the self refresh mode. 26. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 27. XXX: H or L (H: V IH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL. 17 HM51(S)4170D Series, HM51(S)4270D Series Notes concerning 2WE control Please do not separate the U WE/LWE operation timing intentionally. However skew between U WE/LWE are allowed under the following conditions. (1) Each of the UWE/LWE should satisfy the timing specifications individually. (2) Different operation mode for upper/lower byte is not allowed; such as following. RAS CAS Delayed write LWE Early write UWE (3) Closely separated upper/lower byte control is not allowed, unless the condition (tCP ≤ tUL) is satisfied. RAS LWE UWE t UL 18 HM51(S)4170D Series, HM51(S)4270D Series Timing Waveforms *27 Read Cycle t RC t RAS RAS tT t RCD t CSH t RSH t CAS t RP t CRP CAS t ASR t RAD t RAH t ASC t RAL t CAH Address Row Column t RCS UWE LWE t CAC t AA High-Z Dout t RAC t DZC Din High-Z t OAC Dout t RCH t RRH t OFF1 t OFF2 t CDD t ODD t DZO OE 19 HM51(S)4170D Series, HM51(S)4270D Series Early Write Cycle t RC t RAS RAS tT t RCD t CSH t RSH t CAS t CRP t RP CAS t ASR t RAH t ASC t CAH Address Row Column t WCS UWE LWE t WCH t DS t DH Din Din Dout High-Z 20 HM51(S)4170D Series, HM51(S)4270D Series Delayed Write Cycle t RC t RAS t RP RAS t CSH tT t RCD t RSH t CAS t ASR t RAH t ASC t CAH Column t CWL t RWL t CRP CAS Address Row t RCS UWE LWE t WP t DH t DS   * Din Din t DZC t OEH t DZO t ODD Dout High-Z *Invalid Dout t OFF2 t COD OE * Do not enable Dout during delayed write cycle. 21 HM51(S)4170D Series, HM51(S)4270D Series Read-Modify-Write Cycle t RWC tT t RP RAS t CRP t RCD CAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWL t CWD t AWD t RWL t WP t AA t RWD t CAC t DH t DS Din UWE LWE t RAC t DZC Din High-Z  t OAC t DZO t ODD OE 22 Dout High-Z Dout t OEH t OFF2 HM51(S)4170D Series, HM51(S)4270D Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP t RPC t CRP CAS t RAH t ASR Address Row Dout High-Z 23 HM51(S)4170D Series, HM51(S)4270D Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS * t RP t RC t RAS * t RP RAS tT t RPC t CPN t RPC t CHR t CPN t CSR t CHR t CRP t CSR  "  Address t OFF1 Dout High-Z 24 ,   , CAS > * Do not extend tRAS _ tRAS (max). Untested self refresh mode may be activated and loss of data may be resulted (HM514270D, HM514270D) HM51(S)4170D Series, HM51(S)4270D Series Fast Page Mode Read Cycle t RASC t RHCP RAS tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t RP t CRP t CAS CAS t RAD t ASR t RAH t ASC t CAH t ASC t CAH t ASC t RAL t CAH Address Row Column t RCS t RCS t RCH Column t RCS t RCH Column t RRH t RCH UWE LWE t DZC High-Z t ODD t CAC t AA t RAC t OFF1 Dout High-Z t DZO OE t OAC t DZO t OFF2 Dout t AA t ACP t OFF1 t CDD t DZC t CDD High-Z t CAC High-Z t CAC t AA t ACP t DZO Dout t ODD t OFF2 t OAC t OFF2 t OFF1 t ODD t DZC t CDD Din Dout t OAC 25 HM51(S)4170D Series, HM51(S)4270D Series Fast Page Mode Early Write Cycle t RASC t RP RAS t CSH tT t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column t WCS t WCH Column t WCS t WCH t WCS Column t WCH UWE LWE t DS t DS t DH t DH t DS t DH Din Din Din Din Dout High-Z 26 HM51(S)4170D Series, HM51(S)4270D Series Fast Page Mode Delayed Write Cycle t RASC t RP RAS t CSH tT t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t CWL t ASC t CAH Address Row Column Column Column t CWL t RCS UWE LWE t DH t DS t RCS t DS t DH t RCS t DS t WP t WP t CWL t WP t RWL t DH Din Din Din Din t OEH Dout t ODD High-Z OE 27 HM51(S)4170D Series, HM51(S)4270D Series Fast Page Mode Read-Modify-Write Cycle t RASC RAS t RCD tT t CP t PCM t CP t RP t CRP CAS t RAD t RAH t CAH t ASC t ASC t ACP t CAH t CAH tASC t ASR Address Row Column t AWD t CWD t RWD t CWL t WP Column t AWD t RCS t CWD t CPW t CWL t WP Column t CPW t AWD t RCS t CWD t CWL t RWL t WP t RCS UWE LWE t DS t DZC t CAC t DH t DZC t CAC t DS t DH t ACP tDZC High-Z t CAC t OEH t OAC Dout t OFF2 t DS t DH Din High-Z t AA t RAC t OAC Din t DZO t OEH High-Z t AA t OAC Dout t OFF2 Din Din t OEH Dout High-Z Dout t DZO t OFF2 t DZO OE t ODD t ODD t ODD 28 HM51(S)4170D Series, HM51(S)4270D Series Self Refresh Cycle*23, 24, 25, 26 t RP t RASS t RPS RAS tT t RPC t CPN t CRP t CHS t CSR  "  Address t OFF1 Dout High-Z 29  ,  CAS HM51(S)4170D Series, HM51(S)4270D Series Package Dimensions HM514170DJ/DLJ, HM514270DJ/DLJ Series HM51S4170DJ/DLJ, HM51S4270DJ/DLJ Series (CP-40D) Unit: mm 25.80 26.16 Max 40 21 10.16 ± 0.13 1 0.74 1.30 Max 20 3.50 ± 0.26 0.31 2.30 + 0.14 – 11.18 ± 0.13 0.63 Min 0.43 ± 0.10 1.27 0.10 9.40 ± 0.25 30 HM51(S)4170D Series, HM51(S)4270D Series HM514170DTT/DLTT, HM514270DTT/DLTT Series HM51S4170DTT/DLTT, HM51S4270DTT/DLTT Series (TTP-44/40DB) Unit: mm 44 18.41 18.81 Max 35 32 23 1 0.27 ± 0.07 10 13 0.80 0.13 1.15 Max M 22 11.76 ± 0.2 0 – 5° 10.16 1.20 Max 0.10 0.145 0.08 Min 0.18 Max +0.075 –0.025 0.50 ± 0.10 0.68 31 HM51(S)4170D Series, HM51(S)4270D Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 32 HM51(S)4170D Series, HM51(S)4270D Series Revision Record Rev. 0.0 Date Oct. 18, 1996 Contents of Modification Initial issue Drawn by Approved by 33