HM51W16400LS-7

HM51W16400 Series HM51W17400 Series 4,194,304-word × 4-bit Dynamic RAM ADE-203-649C (Z) Rev. 3.0 Feb. 27, 1997 Description The Hitachi HM51W16400 Series, HM51W17400 Series are CMOS dynamic RAMs organized 4,194,304word × 4-bit. They employ the most advanced 0.5 µm CMOS technology for high performance and low power. The HM51W16400 Series, HM51W17400 Series offer Fast Page Mode as a high speed access mode. They have package variations of standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin plastic TSOP. Features • • • Single 3.3 V (±0.3 V) Access time: 50 ns/60 ns/70 ns (max) Power dissipation  Active mode : 324 mW/288mW/252 mW (max) (HM51W16400 Series) : 360 mW/324 mW/288 mW (max) (HM51W17400 Series)  Standby mode : 7.2 mW (max) : 0.36 mW (max) (L-version) Fast page mode capability Long refresh period  4096 refresh cycles : 64 ms (HM51W16400 Series) : 128 ms (L-version)  2048 refresh cycles : 32 ms (HM51W17400 Series) : 128 ms (L-version) • • HM51W16400 Series, HM51W17400 Series • 4 variations of refresh  RAS -only refresh  CAS -before-RAS refresh  Hidden refresh  Self refresh (L-version) Battery backup operation (L-version) Test function  16-bit parallel test mode • • Ordering Information Type No. HM51W16400S-5 HM51W16400S-6 HM51W16400S-7 HM51W16400LS-5 HM51W16400LS-6 HM51W16400LS-7 HM51W17400S-5 HM51W17400S-6 HM51W17400S-7 HM51W17400LS-5 HM51W17400LS-6 HM51W17400LS-7 HM51W16400TS-5 HM51W16400TS-6 HM51W16400TS-7 HM51W16400LTS-5 HM51W16400LTS-6 HM51W16400LTS-7 HM51W17400TS-5 HM51W17400TS-6 HM51W17400TS-7 HM51W17400LTS-5 HM51W17400LTS-6 HM51W17400LTS-7 Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns 300-mil 26-pin plastic TSOP II (TTP-26/24DA) Package 300-mil 26-pin plastic SOJ (CP-26/24DB) 2 HM51W16400 Series, HM51W17400 Series Pin Arrangement HM51W16400S/LS Series HM51W16400TS/LTS Series VCC I/O1 I/O2 WE RAS A11 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 VCC I/O1 I/O2 WE RAS A11 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 (Top view) A8 A7 A6 A5 A4 VSS A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 (Top view) A8 A7 A6 A5 A4 VSS Pin Description Pin name A0 to A11 Function Address input — Row/Refresh address — Column address Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground A0 to A11 A0 to A9 I/O1 to I/O4 RAS CAS WE OE VCC VSS 3 HM51W16400 Series, HM51W17400 Series Pin Arrangement HM51W17400S/LS Series HM51W17400TS/LTS Series VCC I/O1 I/O2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 VCC I/O1 I/O2 WE RAS NC 1 2 3 4 5 6 26 25 24 23 22 21 VSS I/O4 I/O3 CAS OE A9 A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS A10 A0 A1 A2 A3 VCC 8 9 10 11 12 13 19 18 17 16 15 14 A8 A7 A6 A5 A4 VSS (Top view) (Top view) Pin Description Pin name A0 to A10 Function Address input — Row/Refresh address — Column address Data input/Data output Row address strobe Column address strobe Read/Write enable Output enable Power supply Ground No connection A0 to A10 A0 to A10 I/O1 to I/O4 RAS CAS WE OE VCC VSS NC 4 HM51W16400 Series, HM51W17400 Series Block Diagram (HM51W16400 Series) RAS CAS WE OE Timing and control A0 A1 to A9 • • • Column address buffers Column decoder 4M array 4M array Row decoder • • • I/O buffers 4M array I/O1 to I/O4 Row address buffers A10 A11 4M array 5 HM51W16400 Series, HM51W17400 Series Block Diagram (HM51W17400 Series) RAS CAS WE OE Timing and control A0 A1 to A10 • • • Column address buffers Column decoder 4M array 4M array Row decoder • • • I/O buffers 4M array I/O1 to I/O4 Row address buffers 4M array 6 HM51W16400 Series, HM51W17400 Series Absolute Maximum Ratings Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value –0.5 to VCC + 0.5 (≤ +4.6 V (max)) –0.5 to +4.6 50 1.0 0 to +70 –55 to +125 Unit V V mA W °C °C Recommended DC Operating Conditions (Ta = 0 to +70˚C) Parameter Supply voltage Input high voltage Input low voltage Note: Symbol VCC VIH VIL Min 3.0 2.0 –0.3 Typ 3.3 — — Max 3.6 VCC + 0.3 0.8 Unit V V V Notes 1, 2 1 1 1. All voltage referred to VSS . 7 HM51W16400 Series, HM51W17400 Series DC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W16400 Series) HM51W16400 -5 Parameter Operating current* , * 1 2 -6 -7 Test conditions tRC = min TTL interface RAS , CAS = VIH Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z tRC = min RAS = VIH CAS = VIL Dout = enable tRC = min tPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 31.3 µs tRAS ≤ 0.3 µs CMOS interface RAS , CAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ 4.6 V 0 V ≤ Vin ≤ 4.6 V Dout = disable High Iout = –2 mA Low Iout = 2 mA Symbol ICC1 ICC2 Min Max Min Max Min Max Unit — — 90 2 — — 80 2 — — 70 2 mA mA Standby current — 1 — 1 — 1 mA Standby current (L-version) RAS -only refresh current*2 Standby current* 1 ICC2 — 100 — 100 — 100 µA ICC3 ICC5 — — 90 5 — — 80 5 — — 70 5 mA mA CAS -before-RAS refresh current Fast page mode current*1, *3 Battery backup current (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage ICC6 ICC7 ICC10 — — — 90 80 — — 80 70 — — 70 60 mA mA 300 — 300 — 300 µA ICC11 — 200 — 200 — 200 µA ILI ILO VOH VOL –10 10 –10 10 2.4 0 –10 10 –10 10 –10 10 –10 10 VCC 0.4 µA µA V V VCC 2.4 0.4 0 VCC 2.4 0.4 0 Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 8 HM51W16400 Series, HM51W17400 Series DC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (HM51W17400 Series) HM51W17400 -5 Parameter Operating current* , *2 1 -6 -7 Test conditions tRC = min TTL interface RAS , CAS = VIH Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z CMOS interface RAS , CAS ≥ VCC – 0.2 V Dout = High-Z tRC = min RAS = VIH CAS = VIL Dout = enable tRC = min tPC = min CMOS interface Dout = High-Z, CBR refresh: tRC = 62.5 µs tRAS ≤ 0.3 µs CMOS interface RAS , CAS ≤ 0.2 V Dout = High-Z 0 V ≤ Vin ≤ 4.6 V 0 V ≤ Vin ≤ 4.6 V Dout = disable High Iout = –2 mA Low Iout = 2 mA Symbol ICC1 ICC2 Min Max Min Max Min Max Unit — — 100 — 2 — 90 2 — — 80 2 mA mA Standby current — 1 — 1 — 1 mA Standby current (L-version) RAS -only refresh current*2 Standby current* 1 ICC2 — 100 — 100 — 100 µA ICC3 ICC5 — — 100 — 5 — 90 5 — — 80 5 mA mA CAS -before-RAS refresh current Fast page mode current*1, *3 Battery backup current (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage ICC6 ICC7 ICC10 — — — 100 — 90 — 90 80 — — 80 70 mA mA 300 — 300 — 300 µA ICC11 — 200 — 200 — 200 µA ILI ILO VOH VOL –10 10 –10 10 2.4 0 –10 10 –10 10 –10 10 –10 10 VCC 0.4 µA µA V V VCC 2.4 0.4 0 VCC 2.4 0.4 0 Notes : 1. ICC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 9 HM51W16400 Series, HM51W17400 Series Capacitance (Ta = 25˚C, VCC = 3.3 V ± 0.3 V) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ — — — Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 10 HM51W16400 Series, HM51W17400 Series AC Characteristics (Ta = 0 to +70˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) *1, *2, *18, *19 Test Conditions • • • • Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM51W16400/HM51W17400 -5 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol tRC tRP tCP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tOED tDZO tDZC tT Min 90 30 8 50 13 0 8 0 8 18 13 13 50 5 13 0 0 3 Max — — — -6 Min 110 40 10 Max — — — -7 Min 130 50 10 Max — — — Unit ns ns ns Notes 10000 60 10000 15 — — — — 37 25 — — — — — — 50 0 10 0 10 20 15 15 60 5 15 0 0 3 10000 70 10000 18 — — — — 45 30 — — — — — — 50 0 10 0 15 20 15 18 70 5 18 0 0 3 10000 ns 10000 ns — — — — 52 35 — — — — — — 50 ns ns ns ns ns ns ns ns ns ns ns ns ns 5 6 6 7 3 4 11 HM51W16400 Series, HM51W17400 Series Read Cycle HM51W16400/HM51W17400 -5 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol tRAC tCAC tAA tOEA tRCS tRCH tRRH tRAL tCAL tCLZ tOH tOHO tOFF tOEZ tCDD Min — — — — 0 0 0 25 25 0 3 3 — — 13 Max 50 13 25 13 — — — — — — — — 13 13 — -6 Min — — — — 0 0 0 30 30 0 3 3 — — 15 Max 60 15 30 15 — — — — — — — — 15 15 — -7 Min — — — — 0 0 0 35 35 0 3 3 — — 18 Max 70 18 35 18 — — — — — — — — 15 15 — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9, 20 9, 10, 17, 20 9, 11, 17, 20 9, 20 Write Cycle HM51W16400/HM51W17400 -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol tWCS tWCH tWP tRWL tCWL tDS tDH Min 0 8 8 13 13 0 8 Max — — — — — — — -6 Min 0 10 10 15 15 0 10 Max — — — — — — — -7 Min 0 15 10 18 18 0 15 Max — — — — — — — Unit ns ns ns ns ns ns ns 15 15 Notes 14 12 HM51W16400 Series, HM51W17400 Series Read-Modify-Write Cycle HM51W16400/HM51W17400 -5 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol tRWC tRWD tCWD tAWD tOEH Min 131 73 36 48 13 Max — — — — — -6 Min 155 85 40 55 15 Max — — — — — -7 Min 181 98 46 63 18 Max — — — — — Unit ns ns ns ns ns 14 14 14 Notes Refresh Cycle HM51W16400/HM51W17400 -5 Parameter Symbol Min 5 8 0 8 5 Max — — — — — -6 Min 5 10 0 10 5 Max — — — — — -7 Min 5 10 0 10 5 Max — — — — — Unit ns ns ns ns ns Notes CAS setup time (CBR refresh cycle) tCSR CAS hold time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time tCHR WE setup time (CBR refresh cycle) tWRP tWRH tRPC Fast Page Mode Cycle HM51W16400/HM51W17400 -5 Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge Symbol tPC tRASP tCPA Min Max 35 — — 30 — -6 Min Max 40 — -7 Min Max 45 — Unit ns 16 9, 17, 20 Notes 100000 — 30 — — 35 100000 — 35 — — 40 100000 ns 40 — ns ns RAS hold time from CAS precharge tCPRH 13 HM51W16400 Series, HM51W17400 Series Fast Page Mode Read-Modify-Write Cycle HM51W16400/HM51W17400 -5 Parameter Fast page mode read-modify-write cycle time Symbol tPRWC Min 76 53 Max — — -6 Min 85 60 Max — — -7 Min 96 68 Max — — Unit ns ns 14 Notes WE delay time from CAS precharge tCPW Test Mode Cycle *19 HM51W16400/HM51W17400 -5 Parameter Test mode WE setup time Test mode WE hold time Symbol tWTS tWTH Min 0 8 Max — — -6 Min 0 10 Max — — -7 Min 0 10 Max — — Unit ns ns Notes Refresh (HM51W16400 Series) Parameter Refresh Refresh (L-version) Symbol tREF tREF Max 64 128 Unit ms ms Notes 4096 cycles 4096 cycles Refresh (HM51W17400 Series) Parameter Refresh period Refresh period (L-version) Symbol tREF tREF Max 32 128 Unit ms ms Notes 2048 cycles 2048 cycles 14 HM51W16400 Series, HM51W17400 Series Self Refresh Mode (L-version) HM51W16400L/HM51W17400L -5 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol tRASS tRPS tCHS Min 100 90 –50 Max — — — -6 Min 100 110 –50 Max — — — -7 Min 100 130 –50 Max — — — Unit µs ns ns Notes 21, 22, 23, 24 Notes: 1. AC measurements assume tT = 5 ns. 2. An initial pause of 200 µs is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS -only refresh or CAS -before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS -before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either tOED or tCDD must be satisfied. 6. Either tDZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between VIH (min) and VIL (max). 8. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. (V OH = 2.0 V, VOL = 0.8 V) 10. Assumes that tRCD ≥ tRCD (max) and tRCD + tCAC (max) ≥ tRAD + tAA (max). 11. Assumes that tRAD ≥ tRAD (max) and tRCD + tCAC (max) ≤ tRAD + tAA (max). 12. Either tRCH or tRRH must be satisfied for a read cycles. 13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. tWCS , tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥ tCWD (min), and tAWD ≥ tAWD (min), or tCWD ≥ tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles. 16. tRASP defines RAS pulse width in Fast page mode cycles. 17. Access time is determined by the longest among tAA , tCAC and tCPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 15 HM51W16400 Series, HM51W17400 Series 19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M × 4 are don’t care during test mode. Test mode is set by performing a WE-and-CAS -before-RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read cycle, then the device has passed. If they are not equal, data output pin is a low state, then the device has failed. Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test mode and enter a normal operation mode, perform either a regular CAS-beforeRAS refresh cycle or RAS -only refresh cycle. 20. In a test mode read cycle, the value of tRAC , tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 21. Please do not use tRASS timing, 10 µs ≤ tRASS ≤ 100 µs. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS > 100 µs, then RAS precharge time should use tRPS instead of tRP. 22. If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle, CBR refresh should be executed with in 15.6 µs immediately after exiting from and before entering into self refresh mode. 23. If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 4096 or 2048 cycles (4096 cycles: HM51W16400 Series, 2048 cycles: HM51W 17400 Series) of distributed CBR refresh with 15.6 µs interval should be executed with in 64 or 32 ms (64 ms: HM51W16400 Series, 32 ms: HM51W17400 Series) immediately after exiting from and before entering into the self refresh mode. 24. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self fresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 25. XXX: H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 16 HM51W16400 Series, HM51W17400 Series Timing Waveforms*25 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t ASC t RAL t CAL t CAH t RAH Address Row Column t RRH t RCS t RCH WE t DZC t CDD Din High-Z t DZO t OEA t OED OE t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO 17 HM51W16400 Series, HM51W17400 Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) 18 HM51W16400 Series, HM51W17400 Series Delayed Write Cycle *18 t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t CWL t RCS t RWL t WP WE t DZC t DS t DH Din High-Z Din t OEH t OED t DZO   t OEZ t CLZ Dout High-Z Invalid Dout OE 19 HM51W16400 Series, HM51W17400 Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD t CWL t RWL t WP WE t DZC t DS Din High-Z Din t DH t DZO t OED t OEA t OEH OE t CAC t AA t RAC t OEZ t OHO High-Z Dout t CLZ Dout 20 HM51W16400 Series, HM51W17400 Series RAS-Only Refresh Cycle t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP    t ASR t RAH Address Row t OFF Dout High-Z 21 HM51W16400 Series, HM51W17400 Series CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP ,  t CP t WRP t WRH t CP WE Address t OFF Dout High-Z 22 HM51W16400 Series, HM51W17400 Series Hidden Refresh Cycle t RC t RAS t RP t RC t RAS t RC t RP t RAS t RP RAS tT t RSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t RAL t CAH t CHR t CRP Column t WRP t RCS t RRH t WRH   WE t DZC High-Z Din t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t WRP t WRH t CDD t OED t OEZ t OHO t OFF t OH 23 HM51W16400 Series, HM51W17400 Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RCS t RCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED t RCH t RCH t RCS t RRH t RCH t DZC t CDD High-Z t DZO t OED 
,  OE t RAC t AA t OH t CPA t AA t OH t CPA t AA t OH t OEA t OHO t OEA t OHO t OFF t OEZ t OHO t OEA t CAC t CLZ t OFF t CAC t OEZ t CLZ t CAC t CLZ t OFF t OEZ Dout Dout 1 Dout 2 Dout N 24 HM51W16400 Series, HM51W17400 Series Fast Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) 25 HM51W16400 Series, HM51W17400 Series Fast Page Mode Delayed Write Cycle *18 t RASP t RP RAS tT t CSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP      * t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z Invalid Dout Invalid Dout Invalid Dout 26 HM51W16400 Series, HM51W17400 Series Fast Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t CP t RCD CAS t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t PRWC t CP t CAS t CAS t RSH t CAS t CRP t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL Address t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED t WP t DZC t DS t DH Din N Din 1 t DZO t OEH t OEH    * OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z Dout Dout 1 Dout 2 Dout N 27 HM51W16400 Series, HM51W17400 Series Test Mode Cycle *19 Set Cycle** Test Mode Cycle *,** Reset Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din, OE: H or L Test Mode Set Cycle t RC t RP t RAS t RP RAS t RPC t CSR tT CAS t CP t WTS t CHR t RPC t CRP  ,  t WTH t CP WE Address t OFF Dout High-Z 28 Q@ A
, SR CP B HM51W16400 Series, HM51W17400 Series Self Refresh Cycle (L-version)*21,*22,*23,*24 t RP t RASS t RPS RAS t RPC tT t CRP t CHS  ,  , t CP t CSR CAS t WRP WE t OFF Dout t WRH , + &  $  High-Z 29 HM51W16400 Series, HM51W17400 Series Package Dimensions HM51W16400S/LS Series HM51W17400S/LS Series (CP-26/24DB) Unit: mm 26 16.90 17.27 Max 21 19 14 1 3.50 ± 0.26 68 0.74 13 8.51 ± 0.13 7.62 ± 0.13 1.30 Max 0.80 +0.25 –0.17 0.43 ± 0.10 0.41 ± 0.08 1.27 6.71 ± 0.25 Hitachi Code JEDEC Code EIAJ Code Weight CP-26/24DB MO-077-AA SC-632-A 0.8 g 2.54 0.10 30 2.65 ± 0.12 HM51W16400 Series, HM51W17400 Series HM51W16400TS/LTS Series HM51W17400TS/LTS Series (TTP-26/24DA) Unit: mm 26 17.14 17.54 Max 21 19 14 7.62 1 0.42 ± 0.08 0.40 ± 0.06 68 1.27 0.21 M 1.15 Max 13 0.80 9.22 ± 0.20 0.50 ± 0.10 0.68 0 – 5° 0.145 ± 0.05 0.125 ± 0.04 0.13 ± 0.05 Hitachi Code JEDEC Code EIAJ Code Weight 1.20 Max 2.54 0.10 TTP-26/24DA MO-132AB — 0.30 g 31 HM51W16400 Series, HM51W17400 Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi’s permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user’s unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Straße 3 D-85622 Feldkirchen München Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 32 HM51W16400 Series, HM51W17400 Series Revision Record Rev. 1.0 2.0 Date Oct. 14, 1996 Nov. 14, 1996 Contents of Modification Initial issue Addition of HM51W16400-5 Series Addition of HM51W17400-5 Series Power dissipation (active) 396/360 mW(max) to 360/324/288 mW (max) (HM51W17400 Series) DC Characteristics (HM51W17400 Series) ICC1 max: 110/100 mA to 100/90/80 mA ICC3 max: 110/100 mA to 100/90/80 mA ICC6 max: 110/100 mA to 100/90/80 mA 3.0 Feb. 27, 1997 AC Characteristics tRRH min: 5/5/5 ns to 0/0/0 ns Drawn by Y. Kasama Y. Kasama Approved by M. Mishima Y. Matsuno 33