HM6208HLP-45

HM6208H Series 65,536-word × 4-bit High Speed CMOS Static RAM Features • Single 5 V supply and high density 24-pin package • High speed: Access time 25/35/45 ns (max) • Low power  Operation: 300 mW (typ)  Standby: 100 µW (typ) 30 µW (typ) (L-version) • Completely static memory required  No clock or timing strobe required • Equal access and cycle time • Directly TTL compatible: All inputs and outputs • Battery backup operation capability (L-version) Ordering Information Type No. HM6208HP-25 HM6208HP-35 HM6208HP-45 HM6208HLP-25 HM6208HLP-35 HM6208HLP-45 HM6208HJP-25 HM6208HJP-35 HM6208HJP-45 HM6208HLJP-25 HM6208HLJP-35 HM6208HLJP-45 Access Time 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 25 ns 35 ns 45 ns 300-mil, 24-pin SOJ (CP-24D) Package 300-mil, 24-pin plastic DIP (DP-24NC) HM6208H Series Pin Arrangement A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 CS VSS 1 2 3 4 5 6 7 8 9 10 11 12 (Top view) 24 23 22 21 20 19 18 17 16 15 14 13 VCC A15 A14 A13 A12 A11 A10 I/O1 I/O2 I/O3 I/O4 WE Pin Description Pin Name A0–A15 I/O1–I/O4 CS WE VCC VSS Function Address lnput/output Chip select Write enable Power supply Ground 2 HM6208H Series Block Diagram A14 A15 A0 A1 A2 A3 A4 A5 I/O1 I/O2 I/O3 I/O4 A13 A12 A11 A10 A9 A8 A7 A6 Input data control VCC Row decoder Memory array 256 × 1024 VSS Column I/O Column decoder CS WE Truth Table CS H L L WE × H L Mode Not selected Read Write VCC Current I SB , I SB1 I CC I CC I/O Pin High-Z Dout Din Ref. Cycle — Read cycle Write cycle Note: ×: Don’t care. Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Power dissipation Operating temperature range Storage temperature range Storage temperature range under bias Note: Symbol Vin PT Topr Tstg Tbias Value –0.5 to +7.0 1.0 0 to +70 –55 to +125 –10 to +85 *1 Unit V W °C °C °C 1. Vin min = –2.5 V for pulse widths ≤ 10 ns. 3 HM6208H Series Recommended DC Operating Conditions (Ta = 0 to +70 °C) Parameter Supply voltage Symbol VCC VSS Input high (logic 1) voltage Input low (logic 0) voltage Note: VIH VIL Min 4.5 0 2.2 –0.5 *1 Typ 5.0 0 — — Max 5.5 0 6.0 0.8 Unit V V V V 1. VIL min = –2.0 V for pulse width ≤ 10 ns. DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) HM6208H-25 Parameter Input leakage current Output leakage current Operating power supply current Symbol Min I LI I LO I CC — — — Typ — — 60 *2 HM6208H-35/45 Max Min 2.0 — Typ*2 Max Unit Test Conditions — — 50 2.0 µA VCC = Max Vin = VSS to V CC CS = VIH, VIO = VSS to V CC CS = VIL, I I/O = 0 mA, min cycle, duty = 100% CS = VIL, II/O = 0 mA, t cycle = 50 ns, duty = 100% CS = VIH, min cycle CS ≥ V CC – 0.2 V, 0 V ≤ Vin < 0.2 V, or Vin ≥ V CC – 0.2 V 10.0 — 120 — 10.0 µA 100 mA I CC1 — 40 80 — 40 80 mA Standby power supply current I SB Standby power supply current I SB1 (1) I SB1*1 Output low voltage Output high voltage VOL VOH — — 20 0.02 40 2.0 — — 15 0.02 30 2.0 mA — — 2.4 0.006 0.1 *1 — — — 0.4 — — 2.4 0.006 0.1 *1 — — 0.4 — V V I OL = 8 mA I OH = –4.0 mA Notes: 1. L-version 2. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. Capacitance (Ta = 25°C, f = 1 MHz)*1 Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min — — Max 6 11 Unit pF pF Test Conditions Vin = 0 V VI/O = 0 V 1. These parameters are sampled and not 100% tested. 4 HM6208H Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted) Test Conditions • • • • Input pulse levels: V SS to 3.0 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: See figure Output Load +5V 480 Ω +5V 480 Ω Dout 255 Ω Dout 255 Ω 30 pF *1 5 pF *1 Output load (A) Output load (B) (tHZ, tLZ, tWZ, and tOW) Note: 1. Including scope and jig Read Cycle HM6208H-25 Parameter Read cycle time Address access time Chip select access time Output hold from address change Chip selection to output in low-Z Chip deselection to output in high-Z Chip selection to power up time Chip deselection to power down time Note: Symbol Min t RC t AA t ACS t OH t LZ *1 *1 HM6208H-35 Min 35 — — 5 5 0 0 — Max — 35 35 — — 20 — 25 HM6208H-45 Min 45 — — 5 5 0 0 — Max — 45 45 — — 20 — 30 Unit ns ns ns ns ns ns ns ns Max — 25 25 — — 15 — 15 25 — — 5 5 0 0 — t HZ t PU t PD 1. Transition is measured ±200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested. 5 HM6208H Series Read Timing Waveform (1) tRC Address tAA tOH Dout Valid Data tOH Notes: 1. WE is high for read cycle. 2. Device is continuously selected. Read Timing Waveform (2) tRC CS tACS tLZ Dout VCC supply current High impedance tPU ICC ISB Notes: 1. WE is high for read cycle. 2. Address valid prior to or coincident with the CS transition to low. 50% Valid Data tPD 50% High impedance tHZ 6 HM6208H Series Write Cycle HM6208H-25 Parameter Write cycle time Chip selection to end of write Address valid to end of write Address setup time Write pulse width Write recovery time Data valid to end of write Data hold time Write enabled to output in high-Z Output active from end of write Note: Symbol Min t WC t CW t AW t AS t WP t WR t DW t DH t WZ *1 *1 HM6208H-35 Min 35 30 30 0 25 3 20 0 0 0 Max — — — — — — — — 10 — HM6208H-45 Min 45 40 40 0 30 3 20 0 0 0 Max — — — — — — — — 15 — Unit ns ns ns ns ns ns ns ns ns ns Max — — — — — — — — 8 — 25 20 20 0 20 3 15 0 0 0 t OW 1. Transition is measured ± 200 mV from high impedance voltage with load (B). These parameters are sampled and not 100% tested. 7 HM6208H Series Write Timing Waveform (1) (WE Controlled) tWC Address tCW CS tAW tAS WE tDW Din tWZ *3 Dout Valid Data tOW *4 High impedance tDH *4 tWP *1 tWR *2 tOH *5 Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. During this period, I/O pins are in the output state. The input signals of the opposite phase to the outputs must not be applied. 4. If CS is low during this period, I/O pins are in the output state. The data input signals of opposite phase to the outputs must not be applied to them. 5. Dout is the same phase of write data of this write cycle. 8 HM6208H Series Write Timing Waveform (2) (CS Controlled) tWC Address tAW tAS tCW CS tWP *1 WE tDW Din Valid Data High impedance *3 Dout Notes: 1. A write occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high-impedance state. tDH tWR *2 9 HM6208H Series Low VCC Data Retention Characteristics (Ta = 0 to +70 °C) These characteristics are guaranteed for the L-version only. Parameter VCC for data retention Symbol Min VDR 2.0 Typ — Max — Unit V Test Conditions CS ≥ V CC – 0.2 V, Vin ≥ V CC – 0.2 V, or 0 V ≤ Vin < 0.2 V,or Data retention current I CCDR — 0 5 2 — — 50*1 — — µA ns ms Chip deselect to data retention time t CDR Operation recovery time Note: 1. VCC = 3.0 V tR Low V CC Data Retention Timing Waveform Data retention mode 4.5 V tCDR 2.2 V VDR CS 0V CS ≥ VCC – 0.2 V tR VCC 10 HM6208H Series Package Dimensions HM6208HP/HLP Series (DP-24NC) 29.88 30.48 Max Unit: mm 24 13 7.40 Max 7.10 1 1.14 1.27 Max 1.30 12 5.08 Max 7.62 0.51 Min 2.54 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.11 HM6208HJP/HLJP Series (CP-24D) 15.63 16.00 Max 24 13 7.62 ± 0.13 8.64 ± 0.13 Unit: mm 1 0.74 12 3.50 ± 0.26 0.21 2.40 + 0.24 – 1.30 Max 0.43 ± 0.10 1.27 0.10 0.80 +0.25 –0.17 6.76 – 0.16 + 0.35 11