HM628128DLTS-5SL

HM628128D Series 1 M SRAM (128-kword × 8-bit) ADE-203-996 (Z) Preliminary, Rev. 0.0 Jan. 20, 1999 Description The Hitachi HM628128D Series is 1-Mbit static RAM organized 131,072-kword × 8-bit. HM628128D Series has realized higher density, higher performance and low power consumption by employing HiCMOS process technology. The HM628128D Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has package variations of standard 32-pin plastic DIP, standard 32-pin plastic SOP and standard 32-pin plastic TSOPI. Features • Single 5 V supply: 5 V ± 10% • Access time: 55 ns/70 ns (max) • Power dissipation  Active: 30 mW/MHz (typ)  Standby: 10 µW (typ) • Completely static memory.  No clock or timing strobe required • Equal access and cycle times • Common data input and output  Three state output • Directly TTL compatible all inputs • Battery backup operation  2 chip selection for battery backup HM628128D Series Ordering Information Type No. HM628128DLP-5 HM628128DLP-7 HM628128DLP-5SL HM628128DLP-7SL HM628128DLP-5UL HM628128DLP-7UL HM628128DLFP-5 HM628128DLFP-7 HM628128DLFP-5SL HM628128DLFP-7SL HM628128DLFP-5UL HM628128DLFP-7UL HM628128DLTS-5 HM628128DLTS-7 HM628128DLTS-5SL HM628128DLTS-7SL HM628128DLTS-5UL HM628128DLTS-7UL HM628128DLT-5 HM628128DLT-7 HM628128DLT-5SL HM628128DLT-7SL HM628128DLT-5UL HM628128DLT-7UL HM628128DLR-5 HM628128DLR-7 HM628128DLR-5SL HM628128DLR-7SL HM628128DLR-5UL HM628128DLR-7UL Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns Reverse-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32DR) Normal-bend type 8 × 20 mm 32-pin plastic TSOP I (TFP-32D) 8 × 13.4 mm 32-pin plastic TSOP I (TFP-32DC) 525-mil 32-pin plastic SOP (FP-32D) Package 600-mil 32-pin plastic DIP (DP-32) 2 HM628128D Series Pin Arrangement 32-pin DIP/SOP 32-pin TSOP (Normal Type TSOP) NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 A1 A2 A3 32-pin TSOP (Reverse Type TSOP) OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A11 A9 A8 A13 WE CS2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 Pin Description Pin name A0 to A16 I/O0 to I/O7 CS1 CS2 WE OE VCC VSS NC Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Power supply Ground No connection 3 HM628128D Series Block Diagram LSB A12 A7 A6 A5 A4 A3 A2 A1 A0 A10 MSB Row decoder • • • • • VCC VSS Memory matrix 512 x 2,048 I/O0 Input data control I/O7 • • Column I/O Column decoder • • LSB A14 A16 A15 A13 A8 A9 A11 • • MSB CS1 CS2 WE OE Timing pulse generator Read/Write control 4 HM628128D Series Operation Table CS1 H L L L L L L CS2 H L L H H H H WE × × × H L L H OE × × × L H L H I/O High-Z High-Z High-Z Dout Din Din High-Z Operation Standby Standby Standby Read Write Write Output disable Note: H: V IH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to V SS Terminal voltage on any pin relative to V SS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value –0.5 to +7.0 –0.5* to V CC + 0.3* 1.0 –55 to +125 –20 to +85 1 2 Unit V V W °C °C Notes: 1. VT min: –1.5 V for pulse half-width ≤ 30 ns 2. Maximum voltage is +7.0 V DC Operating Conditions Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 4.5 0 2.2 –0.3 –20 Typ 5.0 0 — — — Max 5.5 0 VCC + 0.3 0.8 +70 Unit V V V V °C 1 Note 1. VIL min: –1.5 V for pulse half-width ≤ 30 ns 5 HM628128D Series DC Characteristics Parameter Input leakage current Output leakage current Symbol |ILI| |ILO | Min — — Typ*1 — — Max 1 1 Unit µA µA Test conditions Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, V I/O = VSS to V CC CS1 = VIL, CS2 = VIH, others = VIH/VIL, I I/O = 0 mA Min cycle, duty = 100% I I/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL Cycle time = 1 µs, duty = 100%, I I/O = 0 mA, CS1 ≤ 0.2 V, CS2 ≥ V CC – 0.2 V, VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V (1) CS1 = VIH, CS2 = VIH, or (2) CS2 = VIL 0 V ≤ Vin (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS1 ≥ V CC – 0.2 V, CS2 ≥ V CC – 0.2 V Operating current Average operating current I CC I CC1 — — — — 15 60 mA mA I CC2 — 6 20 mA Standby current I SB I SB1*2 — — — 2 2 100 mA µA I SB1*3 I SB1* Output high voltage Output low voltage Notes: 1. 2. 3. 4. VOH VOL 4 — — 2.4 — 2 1 — — 50 20 — 0.4 µA µA V V I OH = –1 mA I OL = 2.1 mA Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed. This characteristics is guaranteed only for L version. This characteristics is guaranteed only for L-SL version. This characteristics is guaranteed only for L-UL version. Capacitance (Ta = +25°C, f = 1 MHz) Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Typ — — Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1 1. This parameter is sampled and not 100% tested. 6 HM628128D Series AC Characteristics (Ta = –20 to +70°C, VCC = 5.0 V ± 10%, unless otherwise noted.) Test Conditions • • • • • Input pulse levels: VIL = 0.8 V, VIH = 2.4 V Input rise and fall time: 5 ns Input timing reference levels: 1.5 V Output timing reference level: 1.5 V Output load: 1 TTL Gate+ CL (100 pF) (HM628128D-7) 1 TTL Gate+ CL (50 pF) (HM628128D-5) (Including scope and jig) Read Cycle HM628128D -5 Parameter Read cycle time Address access time Chip select access time Symbol t RC t AA t ACS1 t ACS2 Output enable to output valid Output hold from address change Chip selection to output in low-Z t OE t OH t CLZ1 t CLZ2 Output enable to output in low-Z Chip deselection to output in high-Z t OLZ t CHZ1 t CHZ2 Output disable to output in high-Z t OHZ Min 55 — — — — 10 10 10 5 0 0 0 Max — 55 55 55 30 — — — — 20 20 20 -7 Min 70 — — — — 10 10 10 5 0 0 0 Max — 70 70 70 35 — — — — 25 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes 7 HM628128D Series Write Cycle HM628128D -5 Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from output in high-Z Output disable to output in high-Z WE to output in high-Z Symbol t WC t AW t CW t WP t AS t WR t DW t DH t OW t OHZ t WHZ Min 55 50 50 40 0 0 20 0 5 0 0 Max — — — — — — — — — 20 20 -7 Min 70 60 60 50 0 0 25 0 5 0 0 Max — — — — — — — — — 25 25 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 8 1, 2, 8 5 4, 13 6 7 Notes Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occurs during the overlap (tWP) of a low CS1 , a high CS2, and a low WE. A write begins at the later transition of CS1 going low, CS2 going high, or WE going low. A write ends at the earlier transition of CS1 going high, CS2 going low, or WE going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from CS1 going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earlier of WE or CS1 going high or CS2 going low to the end of write cycle. 8. During this period, I/O pins are in the output state; therefore, the input signals of the opposite phase to the outputs must not be applied. 9. If the CS1 goes low or CS2 going high simultaneously with WE going low or after WE going low, the output remain in a high impedance state. 10. Dout is the same phase of the write data of this write cycle. 11. Dout is the read data of next address. 12. If CS1 is low and CS2 high during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 13. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP ≥ tDW min + tWHZ max 8 HM628128D Series Timing Waveforms Read Cycle (WE = VIH) tRC Address Valid address tAA CS1 tACS1 tCLZ1 CS2 tACS2 tCLZ2 tCHZ2 tCHZ1 OE tOE tOLZ Dout High impedance tOHZ tOH Valid data 9 HM628128D Series Write Cycle (1) (OE Clock) tWC Address Valid address tAW OE tCW CS1 *9 tWR CS2 tAS WE tOHZ High impedance Dout tDW Din tDH tWP Valid data 10 HM628128D Series Write Cycle (2) (OE = VIL ) tWC Address Valid address tCW CS1 *9 tWR CS2 tAW tWP WE tAS tWHZ tOW *10 *11 tOH Dout High impedance tDW tDH *12 Din Valid data 11 HM628128D Series Low VCC Data Retention Characteristics (Ta = –20 to +70 °C) Parameter VCC for data retention Symbol VDR Min 2.0 Typ* 5 — Max — Unit V Test conditions*4 Vin ≥ 0V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ V CC – 0.2 V CS1 ≥ V CC – 0.2 V VCC = 3.0 V, Vin ≥ 0 V (1) 0 V ≤ CS2 ≤ 0.2 V or (2) CS2 ≥ V CC – 0.2 V, CS1 ≥ V CC – 0.2 V Data retention current I CCDR*1 — 1.0 50 µA I CCDR*2 I CCDR* Chip deselect to data retention time Operation recovery time Notes: 1. 2. 3. 4. t CDR tR 3 — — 0 t RC* 6 1.0 0.5 — — 15 10 — — µA µA ns ns See retention waveform This characteristic is guaranteed only for L-version, 20 µA max. at Ta = –20 to +40°C. This characteristic is guaranteed only for L-SL-version, 3 µA max. at Ta = –20 to +40° C. This characteristic is guaranteed only for L-UL-version, 1 µA max. at Ta = –20 to +40°C. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1 , I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 ≥ VCC – 0.2 V or 0 V ≤ CS2 ≤ 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 5. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 6. t RC = read cycle time. Low V CC Data Retention Timing Waveform (1) (CS1 Controlled) tCDR VCC 4.5 V Data retention mode tR 2.2 V VDR CS1 0V CS1 ≥ VCC – 0.2 V 12 HM628128D Series Low V CC Data Retention Timing Waveform (2) (CS2 Controlled) tCDR VCC 4.5 V CS2 VDR 0.8 V 0V 0 V ≤ CS2 ≤ 0.2 V Data retention mode tR 13 HM628128D Series Package Dimensions HM628128DLP Series (DP-32) Unit: mm 32 41.90 42.50 Max 17 13.4 13.7 Max 1 2.30 Max 5.08 Max 1.20 16 15.24 0.51 Min 2.54 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.11 Hitachi Code JEDEC EIAJ Weight (reference value) DP-32 — Conforms 5.1 g 14 HM628128D Series HM628128DLFP Series (FP-32D) Unit: mm 20.45 20.95 Max 32 17 1 1.00 Max 16 3.00 Max *0.22 ± 0.05 0.20 ± 0.04 11.30 14.14 ± 0.30 1.42 0.12 0.15 + 0.10 – 0° – 8° 0.80 ± 0.20 1.27 *0.40 ± 0.08 0.38 ± 0.06 0.10 0.15 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-32D Conforms — 1.3 g 15 HM628128D Series HM628128DLTS Series (TFP-32DC) Unit: mm 8.00 8.20 Max 32 17 1 0.22 ± 0.08 0.20 ± 0.06 16 0.50 0.08 M 0.43 Max 13.40 ± 0.30 0.80 0° – 5° 0.50 ± 0.10 1.20 Max 11.80 0.17 ± 0.05 0.15 ± 0.04 0.10 0.13 –0.08 +0.07 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TFP-32DC — — 0.23 g 16 HM628128D Series HM628128DLT Series (TFP-32D) Unit: mm 17 8.00 8.20 Max 32 1 0.22 ± 0.08 0.20 ± 0.06 16 0.50 0.08 M 0.45 Max 0.17 ± 0.05 0.125 ± 0.04 0.13 ± 0.05 20.00 ± 0.20 0° – 5° 0.50 ± 0.10 0.80 1.20 Max 0.10 18.40 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC Code EIAJ Code Weight (reference value) TFP-32D MO-142BD SC-664 0.39 g 17 HM628128D Series HM628128DLR Series (TFP-32DR) Unit: mm 32 8.00 8.20 Max 17 16 1 0.17 ± 0.05 0.125 ± 0.04 0.50 0.22 ± 0.08 0.08 M 0.20 ± 0.06 0.45 Max 1.20 Max 18.40 20.00 ± 0.20 0.80 0.10 0.13 ± 0.05 0° – 5° 0.50 ± 0.10 Dimension including the plating thickness Base material dimension Hitachi Code JEDEC Code EIAJ Code Weight (reference value) TFP-32DR MO-142BD SC-664 0.39 g 18 HM628128D Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to: Hitachi Semiconductor (America) Inc. 2000 Sierra Point Parkway Brisbane, CA 94005-1897 Tel: (800) 285-1601 Fax: (303) 297-0447 Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: (89) 9 9180-0 Fax: (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: (1628) 585000 Fax: (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: (2) 2718-3666 Fax: (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: (2) 735 9218 Fax: (2) 730 0281 Telex: 40815 HITEC HX Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 19 HM628128D Series Revision Record Rev. 0.0 Date Jan. 20, 1999 Contents of Modification Initial issue Drawn by Approved by 20