HM62V8512BLRR-8SL

HM62V8512B Series 4 M SRAM (512-kword × 8-bit) ADE-203-905G (Z) Rev. 6.0 Mar. 31, 2000 Description The Hitachi HM62V8512B is a 4-Mbit static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.35 µm Hi-CMOS process technology. The device, packaged in a 525-mil SOP (foot print pitch width) or 400-mil TSOP TYPE II is available for high density mounting. The HM62V8512B is suitable for battery backup system. Features • Single 3.0 V supply: 2.7 V to 3.6 V • Access time: 70/85 ns (max) • Power dissipation  Active: 15 mW/MHz (typ)  Standby: 3 µW (typ) • Completely static memory. No clock or timing strobe required • Equal access and cycle times • Common data input and output: Three state output • Directly LV-TTL compatible: All inputs • Battery backup operation HM62V8512B Series Ordering Information Type No. HM62V8512BLFP-7 HM62V8512BLFP-8 HM62V8512BLFP-7SL HM62V8512BLFP-8SL HM62V8512BLFP-7UL HM62V8512BLFP-8UL HM62V8512BLTT-7 HM62V8512BLTT-8 HM62V8512BLTT-7SL HM62V8512BLTT-8SL HM62V8512BLTT-7UL HM62V8512BLTT-8UL HM62V8512BLRR-7 HM62V8512BLRR-8 HM62V8512BLRR-7SL HM62V8512BLRR-8SL HM62V8512BLRR-7UL HM62V8512BLRR-8UL Access time 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 70 ns 85 ns 400-mil 32-pin plastic TSOP II reverse (TTP-32DR) 400-mil 32-pin plastic TSOP II (TTP-32D) Package 525-mil 32-pin plastic SOP (FP-32D) 2 HM62V8512B Series Pin Arrangement HM62V8512BLFP Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) HM62V8512BLRR Series VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS HM62V8512BLTT Series 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 Pin Description Pin name A0 to A18 I/O0 to I/O7 CS OE WE VCC VSS Function Address input Data input/output Chip select Output enable Write enable Power supply Ground 3 HM62V8512B Series Block Diagram A18 A16 A1 A0 A2 A12 A14 A3 A7 A6 Row Decoder • • • • • Memory Matrix 1,024 × 4,096 V CC V SS I/O0 Input Data Control I/O7 • • Column I/O Column Decoder • • A13 A17A15 A8 A9 A11A10 A4 A5 • • CS WE OE Timing Pulse Generator Read/Write Control 4 HM62V8512B Series Function Table WE × H H L L CS H L L L L OE × H L H L Mode Not selected Output disable Read Write Write VCC current I SB , I SB1 I CC I CC I CC I CC Dout pin High-Z High-Z Dout Din Din Ref. cycle — — Read cycle Write cycle (1) Write cycle (2) Note: ×: H or L Absolute Maximum Ratings Parameter Power supply voltage Voltage on any pin relative to V SS Power dissipation Operating temperature Storage temperature Storage temperature under bias Symbol VCC VT PT Topr Tstg Tbias Value –0.5 to +4.6 –0.5* to V CC + 0.5* 1.0 –20 to +70 –55 to +125 –20 to +85 1 2 Unit V V W °C °C °C Notes: 1. –3.0 V for pulse half-width ≤ 30 ns 2. Maximum voltage is 4.6 V Recommended DC Operating Conditions (Ta = –20 to +70 °C) Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Note: VIH VIL Min 2.7 0 2.0 –0.3* 1 Typ 3.0 0 — — Max 3.6 0 VCC + 0.3 0.8 Unit V V V V 1. –3.0 V for pulse half-width ≤ 30 ns 5 HM62V8512B Series DC Characteristics (Ta = –20 to +70°C, VCC = 2.7 V to 3.6 V, VSS = 0 V) Parameter Input leakage current Output leakage current Operating power supply current: DC Operating power supply current Operating power supply current Symbol Min |ILI| |ILO | I CC I CC1 — — — — Typ*1 — — — — Max 1 1 10 40 Unit Test conditions µA µA mA mA Vin = VSS to V CC CS = VIH or OE = VIH or WE = VIL, VI/O = VSS to V CC CS = VIL, others = VIH/VIL, I I/O = 0 mA Min cycle, duty = 100% CS = VIL, others = VIH/VIL I I/O = 0 mA Cycle time = 1 µs, duty = 100% I I/O = 0 mA, CS ≤ 0.2 V VIH ≥ V CC – 0.2 V, VIL ≤ 0.2 V CS = VIH Vin ≥ 0 V, CS ≥ V CC – 0.2 V I CC2 — 5 10 mA Standby power supply current: DC Standby power supply current (1): DC I SB I SB1 — — — — 0.1 1* 2 1* 3 1* — — 4 0.3 40* 2 20* 3 5* 4 mA µA µA µA V V V V Output low voltage VOL — — 0.4 0.2 — — I OL = 2.1 mA I OL = 100 µA I OH = –100 µA I OH = –1.0 mA Output high voltage VOH VCC – 0.2 — 2.4 — Notes: 1. 2. 3. 4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. This characteristics is guaranteed only for L version. This characteristics is guaranteed only for L-SL version. This characteristics is guaranteed only for L-UL version. Capacitance (Ta = +25°C, f = 1 MHz) Parameter Input capacitance* 1 1 Symbol Cin CI/O Typ — — Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Input/output capacitance* Note: 1. This parameter is sampled and not 100% tested. 6 HM62V8512B Series AC Characteristics (Ta = –20 to +70°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.) Test Conditions • • • • Input pulse levels: 0.4 V to 2.4 V Input rise and fall time: 5 ns Input timing reference levels: 1.4 V Output timing reference level: 1.5 V/1.5 V(HM62V8512B-7) 0.8 V/2.0 V(HM62V8512B-8) Output load: 1 TTL Gate + C L (50 pF) (Including scope & jig) Read Cycle HM62V8512B -7 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Chip selection to output in low-Z Output enable to output in low-Z Chip deselection to output in high-Z Output disable to output in high-Z Output hold from address change Symbol t RC t AA t CO t OE t LZ t OLZ t HZ t OHZ t OH Min 70 — — — 10 5 0 0 10 Max — 70 70 35 — — 30 30 — -8 Min 85 — — — 10 5 0 0 10 Max — 85 85 45 — — 35 35 — Unit ns ns ns ns ns ns ns ns ns 2 2 1, 2 1, 2 Notes 7 HM62V8512B Series Write Cycle HM62V8512B -7 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time WE to output in high-Z Data to write time overlap Data hold from write time Output active from output in high-Z Output disable to output in high-Z Symbol t WC t CW t AS t AW t WP t WR t WHZ t DW t DH t OW t OHZ Min 70 60 0 60 50 0 0 30 0 5 0 Max — — — — — — 30 — — — 30 -8 Min 85 75 0 75 55 0 0 35 0 5 0 Max — — — — — — 35 — — — 35 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 7 3, 12 6 1, 2, 7 4 5 Notes Notes: 1. t HZ , t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 4. t CW is measured from CS going low to the end of write. 5. t AS is measured from the address valid to the beginning of write. 6. t WR is measured from the earlier of WE or CS going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. t WP ≥ tDW min + tWHZ max 8 HM62V8512B Series Timing Waveforms Read Timing Waveform (WE = VIH) tRC Address tAA tCO CS tLZ tOE tOLZ OE tOHZ tHZ Dout Valid Data tOH 9 HM62V8512B Series Write Timing Waveform (1) (OE Clock) tWC Address tAW OE tCW CS *8 tWR tAS WE tOHZ Dout tWP tDW Din Valid Data tDH 10 HM62V8512B Series Write Timing Waveform (2) (OE Low Fixed) tWC Address tCW CS *8 tWR tAW tWP WE tAS tWHZ tOW tOH *9 *10 Dout tDW Din tDH *11 Valid Data 11 HM62V8512B Series Low VCC Data Retention Characteristics (Ta = –20 to +70 °C) Parameter VCC for data retention Data retention current Symbol VDR I CCDR Min 2 — — — Chip deselect to data retention time Operation recovery time Notes: 1. 2. 3. 4. t CDR tR 0 t RC* 6 Typ — 0.8* 5 Max — 20* 1 Unit V µA µA µA ns ns Test conditions*4 CS ≥ V CC – 0.2 V, Vin ≥ 0 V VCC = 3.0 V, Vin ≥ 0 V CS ≥ V CC – 0.2 V 0.8*5 0.8* — — 5 10* 2 2* — — 3 See retention waveform For L-version and 10 µA (max.) at Ta = –20 to +40° C. For L-SL-version and 3 µA (max.) at Ta = –20 to +40° C. For L-UL-version and 2 µA (max.) at Ta = –20 to +40°C. CS controls address buffer, WE buffer, OE buffer, and Din buffer. In data retention mode, Vin levels (address, WE, OE, I/O) can be in the high impedance state. 5. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 6. t RC = read cycle time. Low V CC Data Retention Timing Waveform (CS Controlled) t CDR V CC 2.7 V Data retention mode tR V DR 2.0 V CS 0V CS ≥ VCC – 0.2 V 12 HM62V8512B Series Package Dimensions HM62V8512BLFP Series (FP-32D) Unit: mm 20.45 20.95 Max 32 17 1 1.00 Max 16 3.00 Max *0.22 ± 0.05 0.20 ± 0.04 11.30 14.14 ± 0.30 1.42 0.12 0.15 + 0.10 – 0° – 8° 0.80 ± 0.20 1.27 *0.40 ± 0.08 0.38 ± 0.06 0.10 0.15 M *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-32D Conforms — 1.3 g 13 HM62V8512B Series Package Dimensions (cont.) HM62V8512BLTT Series (TTP-32D ) Unit: mm 20.95 21.35 Max 32 17 1 *0.42 ± 0.08 0.40 ± 0.06 1.15 Max 1.27 0.21 M 16 10.16 0.80 11.76 ± 0.20 0° – 5° 0.50 ± 0.10 0.10 *0.17 ± 0.05 0.125 ± 0.04 0.13 ± 0.05 1.20 Max *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-32D Conforms — 0.51 g 14 HM62V8512B Series Package Dimensions (cont.) HM62V8512BLRR Series (TTP-32DR) Unit: mm 20.95 21.35 Max 1 16 32 *0.42 ± 0.08 0.40 ± 0.06 1.15 Max 1.27 0.21 M 17 10.16 0.80 11.76 ± 0.20 0° – 5° 0.50 ± 0.10 0.10 *0.17 ± 0.05 0.125 ± 0.04 0.13 ± 0.05 1.20 Max *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) TTP-32DR Conforms — 0.51 g 15 HM62V8512B Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/index.htm For further information write to: Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: (89) 9 9180-0 Fax: (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: (1628) 585000 Fax: (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: (2) 2718-3666 Fax: (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: (2) 735 9218 Fax: (2) 730 0281 Telex: 40815 HITEC HX Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: (408) 433-1990 Fax: (408) 433-0223 Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 16 HM62V8512B Series Revision Record Rev. Date 0.0 0.1 Apr. 24, 1998 Nov. 19, 1998 Contents of Modification Initial issue DC Characteristics I CC1 max: 30 mA to 40 mA I SB1 max: 20/2 µA to 40/20 µA Low V CC Data Retention Characteristics I CCDR max: 10/1 µA to 20/10 µA Change of note1 and 2 Deletion of Preliminary Features Change of Power dissipation Active: TBD (typ) to 15 mW/MHz (typ) Standby: TBD (typ) to 3 µW (typ) DC Characteristics I CC2 typ: TBD to 5 mA I SB1 typ: TBD/TBD to 1/1 µA Low V CC Data Retention Characteristics I CCDR typ: TBD/TBD to 0.8/0.8 µA Low VCC Data Retention Characteristics Change of Low VCC Data Retention Timmng Waveform Addition of L-UL-version DC Characteristics I SB1 typ: 1/1 µA to 1/1/1 µA I SB1 max: 40/20 µA to 40/20/5 µA Addition of note4 Low V CC Data Retention Characteristics I CCDR typ: 0.8/0.8 µA to 0.8/0.8/0.8 µA I CCDR max: 20/10 µA to 20/10/2 µA Addition of note3 Low VCC Data Retention Characteristics Correct error: tR unit ms to ns Low VCC Data Retention Characteristics Change of Low VCC Data Retention Timmng Waveform AC Characteristics Test Conditions: Output timing reference level 0.8 V/2.0 V to 1.5 V/1.5 V (HM62V8512B-7) 0.8 V/2.0 V (HM62V8512B-8) Drawn by M. Higuchi S. Kunito Approved by K. Imato K. Imato 1.0 Dec. 17, 1998 S. Kunito K. Imato 2.0 3.0 Jan. 29, 1999 Apr. 8, 1999 S. Kunito S. Kunito K. Imato K. Imato 4.0 5.0 6.0 Aug. 24, 1999 Oct. 20, 1999 Mar. 31, 2000 S. Kunito I. Ogiwara K. Imato K. Imato 17