HN27C4000G-15

ADE-203-311A (Z) HN27C4000G Series 524288-Word × 8-Bit/262144-Word × 16-Bit CMOS UV Erasable and Programmable ROM Rev. 1 Nov. 10, 1994 The Hitachi HN27C4000 is a 4-Mbit UV erasable and electrically programmable ROM that is organized either as 524288-word × 8 bit or as 262144-word × 16 bit, featuring extra-high speed burst mode that gives two times faster 4-word or 8byte serial access than normal. And also high speed and fast programming are served as well as the existing Hitachi 4M device HN27C4096 and HN27C4001. Fabricated on advanced fine process and high speed circuitry technique, HN27C4000 makes high speed access time and low power dissipation in either active or stand-by mode. Therefore, it is suitable for all systems featuring high speed microprocessor such as the 80386, 80486, 68030, 68040 and so on. Features • Organization: 524288-word × 8-bit/262144word × 16-bit (BYTE/VPP enables selection byte-wide or word-wide) • High speed: Access time 100 ns/120 ns/150 ns (max) Burst access time 50 ns/60 ns/60 ns (max) • Low power dissipation: Standby mode; 5 µW (typ), Active mode; 150 mW/MHz (typ) • Fast high reliability page programming, fast high-reliability programming and option programming: Program voltage; +12.5 V DC Program time; 3.5 sec (min) (Theoretical in Page programming) • Inputs and outputs TTL compatible during both read and program modes • Pin arrangement: 40-pin EIAJ standard pin compatible with HN62414/ HN62434 • Device identifier mode: Manufacturer code and device code HN27C4000G Series Pin Arrangement HN27C4000G Series A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE I/O0 I/O8 I/O1 I/O9 I/O2 I/O10 I/O3 I/O11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE/VPP VSS I/O15/A-1 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 VCC (Top view) Ordering Information Type No. HN27C4000G-10 HN27C4000G-12 HN27C4000G-15 Access time 100 ns 120 ns 150 ns Package 600-mil 40-pin cerdip (DG-40A) Pin Description Pin name A0 – A17 I/O0 – I/O14 I/O15/A-1 CE OE VCC BYTE/VPP VSS Function Address Input/output Input/output/address Chip enable Output enable Power supply Byte/word selection/ Programming power supply Ground 2 HN27C4000G Series Block Diagram A7 : : : : : : : : : : : : A17 XDecoder 2,048 x 2,048 Memory Matrix I/O0 : : : I/O15 Input Data Control Y-Gating Y-Decoder CE OE VCC V PP VSS H A0 . . . . . . . . . . . . . A6 H : High threshold inverter Mode Selection Pin Mode Read (X16 bit) Read (X8 bit) Output disable (X16 bit) Output disable (X8 bit) DG-40A CE (10) VIL VIL VIL VIL OE (12) VIL VIL VIH VIH A9 (39) X X X X BYTE/VPP VCC (31) VIH VIL VIH VIL (21) VCC VCC VCC VCC I/O0 – I/O7, I/O8 – I/O14, I/O15/A-1 (13 – 20, Dout Dout High-Z High-Z 22 – 28, Dout High-Z High-Z High-Z 29) Dout VIH/VIL High-Z VIH/VIL 3 HN27C4000G Series Mode Selection (cont) Pin Mode Standby Page Page program set prog. Page data latch Page program DG-40A CE (10) VIH VIH VIL VIL OE (12) X VH*2 VH*2 VIH VIL VIH VIH VIL VIL VIH VIL A9 (39) X X X X X X X X X X VH *2 BYTE/VPP VCC (31) VSS – VCC VPP VPP VPP VPP VCC VPP VPP VPP VPP VSS – VCC (21) VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC I/O0 – I/O7, I/O8 – I/O14, I/O15/A-1 (13 – 20, High-Z High-Z Din High-Z Dout High-Z Din Dout Dout High-Z Code 22 – 28, High-Z High-Z Din High-Z Dout High-Z Din Dout Dout High-Z Code 29) High-Z High-Z Din High-Z Dout High-Z Din Dout Dout High-Z Code Page program verify VIH Page program reset VIH Word Program prog. Program verify Optional verify Program inhibit Identifier VIL VIH VIL VIH VIL Notes: 1. X: Don’t care. 2. VH: 12.0 V ± 0.5 V Absolute Maximum Ratings Item All input and output *1 *1 Symbol voltages*1 Vin, Vout VID VPP VCC Topr Tstg Tbias *3 Value –0.6*2 –0.6*2 to +7.0 to +13.0 Unit V V V V °C °C °C Voltage on pin A9 and OE VPP voltage VCC voltage –0.6 to +13.5 –0.6 to +7.0 0 to +70 –65 to +125 –20 to +80 Operating temperature range Storage temperature range Storage temperature under bias Notes: 1. Relative to VSS. 2. Vin, Vout, VID min = –2.0 V for pulse width ≤ 20 ns 3. Storage temperature range of device before programming. 4 HN27C4000G Series Capacitance (Ta = 25°C, f = 1 MHz) Item Input capacitance Output capacitance Symbol Cin Cout Min — — Typ — — Max 12 20 Unit pF pF Test conditions Vin = 0 V Vout = 0 V Notes Except BYTE/VPP Read Operation DC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C) Item Input leakage current Output leakage current VPP current Standby VCC current Operating VCC current Input voltage Symbol ILI ILO IPP1 ISB1 ISB2 ICC1 ICC2 VIL VIH Output voltage VOL VOH Min — — — — — — — –0.3*1 2.2 — 2.4 Typ — — 1 — 1 — — — — — — Max 2 2 20 1 20 35 120 0.8 VCC + 1*2 0.45 — Unit µA µA µA mA µA mA mA V V V V IOL = 2.1 mA IOH = –400 µA Test conditions Vin = 5.5 V Vout = 5.5 V/0.45 V VPP = 5.5 V CE = VIH CE = VCC ± 0.3 V Iout = 0 mA, f = 1 MHz Iout = 0 mA, f = 10 MHz Notes: 1. VIL min = –1.0 V for pulse width ≤ 50 ns VIL min = –2.0 V for pulse width ≤ 20 ns 2. VIH max = VCC +1.5 V for pulse width ≤ 20 ns If VIH is over the specified maximum value, read operation cannot be guaranteed. 5 HN27C4000G Series AC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C) Test Conditions • • • • Input pulse levels: 0.45 to 2.4 V Input rise and fall times: ≤ 10 ns Output load: 1 TTL gate +100 pF Reference levels for measuring timing: 0.8 V, 2.0 V HN27C4000 HN27C4000 HN27C4000 -10 -12 -15 Item Address to output delay CE to output delay OE to output delay Burst address to output delay OE high to output float *1 Address to output hold Note: Symbol tACC tCE tOE tBAC tDF tOH Min — — — — 0 5 Max 100 100 60 50 35 — Min — — — — 0 5 Max 120 120 60 60 40 — Min — — — — 0 5 Max 150 150 70 60 50 — Unit ns ns ns ns ns ns Test conditions CE = OE = VIL OE = VIL CE = VIL CE = VIL CE = VIL CE = OE = VIL 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. Read Timing Waveform Address CE Standby mode tCE Active mode Standby mode OE tOE t ACC Data Out Data Out Valid tOH tDF 6 HN27C4000G Series Read Timing Waveform (Burst access mode) In Burst Access mode, fast read-out of 4 word data is selected by address A0, A1. (Valid only for Read × 16 mode) A2 to A17 t ACC t CE CE t OE OE t BAC t BAC tBAC tBAC A0, A1 t OH t OH Valid Output t OH Valid Output t OH Valid Output Data Out Valid Output 7 HN27C4000G Series In Burst Access mode, fast read-out of 8 byte data is selected by address A-1, A0, A1. (Valid only for Read × 8 mode) A2 to A17 t ACC t CE CE t OE OE tBAC t BAC tBAC tBAC tBAC tBAC tBAC tBAC A-1, A0, A1 t OH t OH Valid Output t OH Valid Output t OH Valid Output t OH Valid Output t OH Valid Output t OH Valid Output t OH Valid Output Data Out Valid Output 8 HN27C4000G Series Fast High-Reliability Page Programming This device can be applied the high performance page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. Page Program Set Apply 12 V to OE pin after applying 12.5 V to VPP to set a page program mode. The device operates in a page program mode until reset. Page Program Reset Set V PP to V CC level or less to reset a page program mode. START SET PAGE PROG LATCH MODE VPP= 12.5 ± 0.3 V V = 6.25 ± 0.25 V CC OE = 12.0 ± 0.5 V Address = 0 n=0 Latch Address + 1 → Address Latch Address + 1 → Address Latch Address + 1 → Address Latch n + 1 →n SET PAGE PROG./VERIFY MODE VPP = 12.5 ± 0.3 V V = 6.25 ± 0.25 V CC Address + 1 → Address Program tPW = 50 µs ± 5% VERIFY NO GO LAST address? NOGO n = 10? YES NO YES SET READ MODE VCC = 5.0 ± 0.5 V VPP = V CC READ all address GO END Fast High-Reliability Page Programming Flowchart NOGO FAIL 9 HN27C4000G Series DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Item Input leakage current Output voltage during verify Symbol ILI VOL VOH Operating VCC current Input voltage ICC VIL VIH VH VPP supply current IPP Min — — 2.4 — –0.1*5 2.2 11.5 — Typ — — — — — — 12.0 — Max 2 0.45 — 50 0.8 VCC + 0.5*6 12.5 70 Unit µA V V mA V V V mA CE = VIL Test conditions Vin = 6.5 V/0.45 V IOL = 2.1 mA IOH = –400 µA Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = –0.6 V for pulse width ≤ 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 10 HN27C4000G Series AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Test Conditions • Input pulse levels: 0.45 to 2.4 V • Input rise and fall times: ≤ 20 ns • Reference levels for measuring timing: Inputs; 0.8 V, 2.0 V, Outputs; 0.8 V, 2.0 V Item Address setup time OE setup time Data setup time Address hold time Data hold time OE high to output float delay VPP setup time VCC setup time CE initial programming pulse width CE setup time Data valid from OE CE pulse width during data latch OE = VH setup time OE = VH hold time VPP hold time*2 Symbol tAS tOES tDS tAH tDH tDF*1 tVPS tVCS tPW tCES tOE tLW tOHS tOHH tVRS Min 2 2 2 0 2 0 2 2 47.5 2 0 1 2 2 1 Typ — — — — — — — — 50.0 — — — — — — Max — — — — — 130 — — 52.5 — 150 — — — — Unit µs µs µs µs µs ns µs µs µs µs ns µs µs µs µs Test conditions Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Page program mode will be reset when VPP is set to VCC or less. 11 HN27C4000G Series Fast High-Reliability Page Programming Timing Waveform Page program mode Program data latch A2 – A17 t AS A0, A1 t DH t DS Data Data in stable Data out valid t VPS VPP VPP VCC Page program Program verify t AH t AS t AH t OE t DF t VCS VCC + 1.25 VCC VCC t OHH t OHS t CES t PW t OES CE t LW OE VH VIH VIL t VRS 12 HN27C4000G Series Fast High-Reliability Programming This device can be applied the fast high-reliability programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. START SET PROG./VERIFY MODE VPP = 12.5 ± 0.3 V V = 6.25 ± 0.25 V CC Address = 0 n=0 n+1 n Program tPW = 50 µs ± 5% Address + 1 Address NO VERIFY GO LAST address? NOGO n = 10? YES NO YES SET READ MODE VCC = 5.0 ± 0.5 V VPP = V CC READ all address GO END NOGO FAIL Fast High-Reliability Programming Flowchart 13 HN27C4000G Series DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP =12.5 V ± 0.3 V, Ta=25°C ± 5°C) Item Input leakage current VPP supply current Operating VCC current Input voltage Symbol ILI IPP ICC VIL VIH Output voltage VOL VOH Min — — — –0.1*5 2.2 — 2.4 Typ — — — — — — — Max 2 40 50 0.8 VCC + 0.5*6 0.45 — Unit µA mA mA V V V V IOL = 2.1 mA IOH = –400 µA Test conditions Vin = 6.5 V/0.45 V CE = VIL Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = –0.6 V for pulse width ≤ 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Test Conditions • Input pulse levels: 0.45 to 2.4 V • Input rise and fall times: ≤ 20 ns • Reference levels for measuring timings: 0.8 V, 2.0 V Item Address setup time OE setup time Data setup time Address hold time Data hold time OE to output float delay VPP setup time VCC setup time CE initial programming pulse width Data valid from OE Note: Symbol tAS tOES tDS tAH tDH tDF *1 Min 2 2 2 0 2 0 2 2 47.5 0 Typ — — — — — — — — 50.0 — Max — — — — — 130 — — 52.5 150 Unit µs µs µs µs µs ns µs µs µs ns Test conditions tVPS tVCS tPW tOE 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 14 HN27C4000G Series Fast High-Reliability Programming Timing Waveform Program Address t AS Data t DS V PP V PP V CC t VPS V CC V CC+1.25 V CC t VCS CE Data In Stable t DH Program Verify t AH Data Out Valid t DF t PW OE t OES t OE Optional Page Programming This device can be applied the optional page programming algorithm shown in the following flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration in reliability of programmed data. This programming algorithm is the combination of page programming and word verify. It can avoid the increase of programming verify time when a programmer with slow machine cycle is used, and shorten the total programming time. Regarding the timing specifications for page programming and word verify, please refer to the specifications for fast high-reliability page programming and fast high-reliability programming. 15 HN27C4000G Series START SET PAGE PROG LATCH MODE VPP= 12.5 ± 0.3 V V = 6.25 ± 0.25 V CC OE = 12.0 ± 0.5 V Address = 0 Latch Address + 1 Latch Address + 1 Latch Address + 1 Latch SET PAGE PROG. MODE VPP = 12.5 ± 0.3 V V CC = 6.25 ± 0.25 V Address + 1 Address Program tPW = 50 µs ± 5% NO LAST address? Address Address Address YES PAGE PROG. RESET VPP = VCC = 6.25 ± 0.25 V SET WORD PROG./VERIFY MODE VPP = 12.5 ± 0.3 V V CC = 6.25 ± 0.25 V Address = 0 n=0 VERIFY NOGO n+1 Address + 1 Address n Program tPW = 50 µs ± 5% VERIFY GO LAST all address? YES SET READ MODE VCC = 5.0 ± 0.5 V VPP = VCC READ all address GO END Optional Page Programming Flowchart FAIL NOGO n = 10? YES NO NOGO GO 16 HN27C4000G Series DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP =12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Item Input leakage current Output voltage during verify Symbol ILI VOL VOH Operating VCC current Input voltage ICC VIL VIH VH VPP supply current IPP Min — — 2.4 — –0.1*5 2.2 11.5 — Typ — — — — — — 12.0 — Max 2 0.45 — 50 0.8 VCC + 0.5*6 12.5 70 Unit µA V V mA V V V mA CE = VIL Test conditions Vin = 6.5 V/0.45 V IOL = 2.1 mA IOH = –400 µA Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. VPP must not exceed 13 V including overshoot. 3. An influence may be had upon device reliability if the device is installed or removed while VPP = 12.5 V. 4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low. 5. VIL min = –0.6 V for pulse width ≤ 20 ns. 6. If VIH is over the specified maximum value, programming operation cannot be guaranteed. 17 HN27C4000G Series AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C) Test Conditions • Input pulse levels: 0.45 to 2.4 V • Input rise and fall times: ≤ 20 ns • Reference levels for measuring timings: Inputs; 0.8 V, 2.0 V Outputs; 0.8 V, 2.0 V Item Address setup time OE setup time Data setup time Address hold time Data hold time OE high to output float delay VPP setup time VCC setup time CE initial programming pulse width CE setup time Data valid from OE CE pulse width during data latch OE = VH setup time OE = VH hold time Page programming reset time VPP hold time *2 *2 Symbol tAS tOES tDS tAH tDH tDF *1 Min 2 2 2 0 2 0 2 2 47.5 2 0 1 2 2 1 1 Typ — — — — — — — — 50.0 — — — — — — — Max — — — — — 130 — — 52.5 — 150 — — — — — Unit µs µs µs µs µs ns µs µs µs µs ns µs µs µs µs µs Test conditions tVPS tVCS tPW tCES tOE tLW tOHS tOHH tVLW tVRS Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no longer driven. 2. Page program mode will be reset when VPP is set to VCC or less. 18 HN27C4000G Series Option Page Programming Timing Waveform Page program mode Program data latch Page program Word program mode Program verify Program A2 – A17 t AH t AS t AH t AS t AH A0, A1 t DS Data in stable t DH t DS Data out valid t DF Data in stable Data t VPS VPP VCC t VCS t VPS t OE t DF VPP t VRS t VLW VCC+ 1.25 VCC VCC t OHS t OHH t CES t CES CE t LW t PW OE VH VIH VIL t OES t PW 19 HN27C4000G Series Erase Erasure of this device is performed by exposure to ultraviolet light of 2537 Å and all the output data are changed to “1” after this erasure procedure. The minimum integrated dose (i.e. UV intensity X exposure time) for erasure is 15 W•sec/cm2. Mode Description Device Identifier Mode The device identifier mode allows the reading out of binary codes that identify manufacturer and type of device, from outputs of EPROM. By this mode, the device will be automatically matched its own corresponding programming algorithm, using programming equipment. HN27C4000G Identifier Code A0 Identifier DG-40 (9) VIL VIH I/O8 – I/O15 I/O7 — X X (28) 0 1 I/O6 (26) 0 0 I/O5 (24) 0 1 I/O4 (22) 0 0 I/O3 (19) 0 0 I/O2 (17) 1 0 I/O1 (15) 1 0 I/O0 (13) 1 1 Hex Data 07 A1 Manufacturer code Device code Notes: 1. 2. 3. 4. 5. VCC = 5.0 V ± 10% A9 = 12.0 V ± 0.5 V CE, OE = VIL A1 – A8, A10 – A17: Don’t care. X: Don’t care. 20