HN29W25611T

HN29W25611T-50H 256M AND type Flash Memory More than 16,057-sector (271,299,072-bit) ADE-203-1178A (Z) Rev. 1.0 May. 10, 2000 Description The Hitachi HN29W25611T is a CMOS Flash Memory with AND type multi-level memory cells. It has fully automatic programming and erase capabilities with a single 3.3 V power supply. The functions are controlled by simple external commands. To fit the I/O card applications, the unit of programming and erase is as small as (2048 + 64) bytes. Initial available sectors of HN29W25611T are more than 16,057 (98% of all sector address) and less than 16,384 sectors. Features • On-board single power supply (VCC): VCC = 3.3 V ± 0.3 V • Organization  AND Flash Memory: (2048 + 64) bytes × (More than 16,057 sectors)  Data register: (2048 + 64) bytes • Multi-level memory cell  2 bit/per memory cell • Automatic programming  Sector program time: 3.0 ms (typ)  System bus free  Address, data latch function  Internal automatic program verify function  Status data polling function • Automatic erase  Single sector erase time: 1.5 ms (typ)  System bus free  Internal automatic erase verify function  Status data polling function HN29W25611T-50H • Erase mode  Single sector erase ((2048 + 64) byte unit) • Fast serial read access time:  First access time: 50 µs (max)  Serial access time: 50 ns (max) • Low power dissipation:  ICC2 = 50 mA (max) (Read)  ISB2 = 50 µA (max) (Standby)  ICC3/ICC4 = 40 mA (max) (Erase/Program)  ISB3 = 5 µA (max) (Deep standby) • The following architecture is required for data reliability.  Error correction: more than 3-bit error correction per each sector read  Spare sectors: 1.8% (290 sectors) within usable sectors Ordering Information Type No. HN29W25611T-50H Available sector More than 16,057 sectors Package 12.0 × 18.40 mm 2 0.5 mm pitch 48-pin plastic TSOP I (TFP-48D) 2 HN29W25611T-50H Pin Arrangement 48-pin TSOP VSS VCC OE I/O0 I/O1 I/O2 I/O3 VSS NC NC NC NC NC NC NC NC VCC I/O4 I/O5 I/O6 I/O7 SC VSS VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Top view) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS VSS NC CDE NC RES NC VCC NC NC NC NC NC NC NC NC VSS RDY/Busy WE NC CE NC VCC VSS Pin Description Pin name I/O0 to I/O7 CE OE WE CDE VCC* VSS * 1 1 Function Input/output Chip enable Output enable Write enable Command data enable Power supply Ground Ready/ Busy Reset Serial clock No connection RDY/Busy RES SC NC Note: 1. All V CC and VSS pins should be connected to a common power supply and a ground, respectively. 3 HN29W25611T-50H Block Diagram 2048 + 64 X-decoder 16384 × (2048 + 64) × 8 memory matrix •• I/O0 to I/O7 Data input buffer Input data control Data register (2048 + 64) • • Multiplexer • • • • • • Y-gating Y-decoder Data output buffer ••• RDY/Busy •• • • Y-address counter VCC VSS CE OE WE SC RES CDE Control signal buffer Read/Program/Erase control 4 16057 - 16384 Sector address buffer HN29W25611T-50H Memory Map and Address Sector address 2048 bytes 3FFFH 3FFEH 3FFDH 2048 bytes 2048 bytes 64 bytes 64 bytes 64 bytes 2048 bytes 0002H 0001H 0000H 000H 2048 + 64 bytes 2048 bytes 2048 bytes 64 bytes 64 bytes 64 bytes 800H 83FH Column address Control bytes Address Sector address Cycles SA (1): SA (2): Column address CA (1): CA (2): I/O0 I/O1 I/O2 I/O3 A0 A1 A2 A3 A8 A9 A10 A11 A0 A1 A2 A3 A8 A9 A10 A11 I/O4 A4 A12 A4 × I/O5 I/O6 I/O7 A5 A6 A7 A13 ×*2 × A5 A6 A7 × × × First cycle Second cycle First cycle Second cycle Notes: 1. Some failed sectors may exist in the device. The failed sectors can be recognized by reading the sector valid data written in a part of the column address 800 to 83F (The specific address is TBD.). The sector valid data must be read and kept outside of the sector before the sector erase. When the sector is programmed, the sector valid data should be written back to the sector. 2. An × means "Don't care". The pin level can be set to either VIL or VIH, referred to DC characteristics. 16057 - 16384 sectors *1 5 HN29W25611T-50H Pin Function CE: CE is used to select the device. The status returns to the standby at the rising edge of CE in the reading operation. However, the status does not return to the standby at the rising edge of CE in the busy state in programming and erase operation. OE: Memory data and status register data can be read, when OE is VIL . WE : Commands and address are latched at the rising edge of WE. SC: Programming and reading data is latched at the rising edge of SC. RES: RES pin must be kept at the VILR (VSS ± 0.2 V) level when VCC is turned on and off. In this way, data in the memory is protected against unintentional erase and programming. RES must be kept at the VIHR (VCC ± 0.2 V) level during any operations such as programming, erase and read. CDE: Commands and data are latched when CDE is VIL and address is latched when CDE is VIH. RDY/Busy: The RDY/Busy indicates the program/erase status of the flash memory. The RDY/Busy signal is initially at a high impedance state. It turns to a VO L level after the (40H) command in programming operation or the (B0H) command in erase operation. After the erase or programming operation finishes, the RDY/Busy signal turns back to the high impedance state. I/O0 to I/O7: The I/O pins are used to input data, address and command, and are used to output memory data and status register data. Mode Selection Mode Deep standby Standby Output disable Status register read* Command write* 2 1 CE ×* 4 VIH VIL VIL VIL OE × × VIH VIL VIH WE × × VIH VIH VIL SC × × × × VIL RES VILR VIHR VIHR VIHR VIHR CDE × × × × VIL RDY/Busy* 3 I/O0 to I/O7 VOH VOH VOH VOH VOH High-Z High-Z High-Z Status register outputs Din Notes: 1. Default mode after the power on is the status register read mode (refer to status transition). From I/O0 to I/O7 pins output the status, when CE = VIL and OE = VIL (conventional read operation condition). 2. Refer to the command definition. Data can be read, programmed and erased after commands are written in this mode. 3. The RDY/ Busy bus should be pulled up to VCC to maintain the VOH level while the RDY/Busy pin outputs a high impedance. 4. An × means “Don’t care”. The pin level can be set to either VIL or VIH referred to DC characteristics. 6 HN29W25611T-50H Command Definition*1, 2 First bus cycle Command Read Bus cycles Serial read (1) (Without CA) 3 (With CA) Serial read (2) Read identifier codes Data recovery read Auto erase Single sector (Without CA*7) (With CA*7) Program (2)*10 Operation Data in mode*3 Write 00H 00H F0H 90H 01H 20H 10H 10H 1FH 0FH 11H 11H FFH 50H 12H Write SA (1)*4 Second bus cycle Operation Data in mode Write Write Write Read Read Write Write Write Write Write Write Write SA (1)*4 SA (1)*4 SA (1)*4 SA (1)*4 SA (1)*4 SA (1)*4 SA (1)*4 SA (1)*4 SA (1)*4 SA (1)*4 ID*8, 9 Recovery data Data out 3 + 2h*6 Write 3 1 1 4 4 Write Write Write Write Write Auto program Program (1) 4 + 2h*6 Write 4 Write Write Write Program (3) (Control bytes)*7 4 Program (4) (WithoutCA*7) 4 (With CA*7) Reset Clear status register Data recovery write 4 + 2h*6 Write 1 1 4 Write Write Write 7 HN29W25611T-50H Third bus cycle Command Read Bus cycles Serial read (1) (Without CA) 3 (With CA) Serial read (2) Read identifier codes Data recovery read Auto erase Single sector (Without CA*7) (With CA*7) Program (2)* 10 Fourth bus cycle Operation mode Data in Operation mode Write Data in SA (2)*4 SA (2)*4 SA (2)*4 3 + 2h*6 Write 3 1 1 4 4 Write Write Write Write CA (1)*5 SA (2)*4 SA (2)*4 SA (2)*4 SA (2)* 4 Write Write Write Write Write Write Write B0H*11 40H *11, 12 CA (1) 40H *11, 12 40H *11, 12 40H *11, 12 CA (1) Auto program Program (1) 4 + 2h*6 Write 4 Write Write Write Program (3) (Control bytes)*7 4 Program (4) (WithoutCA*7) 4 (With CA*7) Reset Clear status register Data recovery write SA (2)*4 SA (2)*4 SA (2)*4 4 + 2h*6 Write 1 1 4 Write SA (2)*4 Write 40H *11, 12 8 HN29W25611T-50H Fifth bus cycle Command Read Bus cycles Serial read (1) (Without CA) 3 (With CA) Serial read (2) Read identifier codes Data recovery read Auto erase Single sector (Without CA*7) (With CA*7) Program (2)*10 7 Sixth bus cycle Operation mode Data in Operation mode Data in 3 + 2h*6 Write 3 1 1 4 4 4 + 2h*6 Write 4 CA (2)*5 Auto program Program (1) CA (2)*5 Write 40H *11, 12 Program (3) (Control bytes)* 4 Program (4) (WithoutCA*7) 4 (With CA*7) Reset Clear status register Data recovery write 4 + 2h*6 Write 1 1 4 CA (2) Write 40H *11, 12 Notes: 1. Commands and sector address are latched at rising edge of WE pulses. Program data is latched at rising edge of SC pulses. 2. The chip is in the read status register mode when RES is set to VIHR first time after the power up. 3. Refer to the command read and write mode in mode selection. 4. SA (1) = Sector address (A0 to A7), SA (2) = Sector address (A8 to A13). 5. CA (1) = Column address (A0 to A7), CA (2) = Column address (A8 to A11). (0 ≤ A11 to A0 ≤ 83FH) 6. The variable h is the input number of times of set of CA (1) and CA (2) (1 ≤ h ≤ 2048 + 64). Set of CA (1) and CA (2) can be input not only one time but free times. 7. By using program (1) and (3), data can additionally be programmed for each sector before erase. 8. ID = Identifier code; Manufacturer code (07H), Device code (99H). 9. The manufacturer identifier code is output when CDE is low and the device identifier code is output when CDE is high. 10. Before program (2) operations, data in the programmed sector must be erased. 11. No commands can be written during auto program and erase (when the RDY/ Busy pin outputs a VOL ). 12. The fourth or sixth cycle of the auto program comes after the program data input is complete. 9 HN29W25611T-50H Mode Description Read Serial Read (1): Memory data D0 to D2111 in the sector of address SA is sequentially read. Output data is not valid after the number of the SC pulse exceeds 2112. When CA is input, memory data D (m) to D (m + j) in the sector of address SA is sequentially read. Then output data is not valid after the number of the SC pulse exceeds (2112 to m). The mode turns back to the standby mode at any time when CE is VIH. Serial Read (2): Memory data D2048 to D2111 in the sector of address SA is sequentially read. Output data is not valid after the number of the SC pulse exceeds 64. The mode turns back to the standby mode at any time when CE is VIH. Automatic Erase Single Sector Erase: Memory data D0 to D2111 in the sector of address SA is erased automatically by internal control circuits. After the sector erase starts, the erasure completion can be checked through the RDY/Busy signal and status data polling. All the bits in the sector are "1" after the erase. The sector valid data stored in a part of memory data D2048 to D2111 must be read and kept outside of the sector before the sector erase. Automatic Program Program (1): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into the sector of address SA automatically by internal control circuits. By using program (1), data can additionally be programed for each sector before the following erase. When the column is programmed, the data of the column must be [FF]. After the programming starts, the program completion can be checked through the RDY/ Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0" when they are programmed. The sector valid data should be included in the program data PD2048 to PD2111. Program (2): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by internal control circuits. After the programming starts, the program completion can be checked through the RDY/Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0" when they are programmed. The sector must be erased before programming. The sector valid data should be included in the program data PD2048 to PD2111. Program (3): Program data PD2048 to PD2111 is programmed into the sector of address SA automatically by internal control circuits. By using program (3), data can additionally be programed for each sector befor the following erase. When the column is programmed, the data of the column must be [FF]. After the programming starts, the program completion can be checked through the RDY/Busy signal and status data polling. Programmed bits in the sector turn from "1" to "0" when they are programmed. 10 HN29W25611T-50H Program (4): Program data PD0 to PD2111 is programmed into the sector of address SA automatically by internal control circuits. When CA is input, program data PD (m) to PD (m + j) is programmed from CA into the sector of address SA automatically by internal control circuits. By using program (4), data can be rewritten for each sector before the following erase. So the column data before programming operation are either "1" or "0". In this mode, E/W number of times must be counted whenever program (4) execute. After the programming starts, the program completion can be checked through the RDY/ Busy signal and status data polling. The sector valid data should be included in the program data PD2048 to PD2111. 16383 Sector address Memory array 0 0 16383 Sector address Memory array 0 16383 Sector address Memory array 0 Register 2111 0 Column address Register 2111 0 2048 Register Serial read (2) Program (3) 2111 Serial read (1) (Without CA) Program (1) (Without CA) Program (2) Serial read (1) (With CA) Program (1) (With CA) Status Register Read The status returns to the status register read mode from standby mode, when CE and OE is VIL. In the status register read mode, I/O pins output the same operation status as in the status data polling defined in the function description. Identifier Read The manufacturer and device identifier code can be read in the identifier read mode. The manufacturer and device identifier code is selected with CDE VIL and V IH, respectively. 11 HN29W25611T-50H Data Recovery Read When the programming was an error, the program data can be read by using data recovery read. When an additional programming was an error, the data compounded of the program data and the origin data in the sector address SA can be read. Output data are not valid after the number of SA pulse exeeds 2112. The mode turns back to the standby mode at any time when CE is VIH. The read data are invalid when addresses are latched at a rising edge of WE pulse after the data recovery read command is written. Data Recovery Write When the programming into a sector of address SA was an error, the program data can be rewritten automatically by internal control circuit into the other selected sector of address SA’. In this case, top address [SA13] of sector of address SA’ must be the same as SA. Since the data recovery write mode is internally Program (4) mode, rewritten sector of address SA’ needs no sector erase before rewrite. After the data recovery write mode starts, the program completion can be checked through the RDY/ Busy signal and the status data polling. 12 HN29W25611T-50H Command/Address/Data Input Sequence Serial Read (1) (With CA before SC) Command /Address CDE WE SC Low Data output Data output 00H SA (1) SA (2) CA (1) CA (2) CA (1)' CA (2)' Serial Read (1) (With CA after SC) Command /Address CDE WE SC Low Data output Data output Data output 00H SA (1) SA (2) CA (1) CA (2) CA (1)' CA (2)' Serial Read (1) (Without CA), (2) Command/Address CDE WE SC Low Data output 00H/F0H SA (1) SA (2) Single Sector Erase Command/Address CDE WE SC Low Erase start 20H SA (1) SA (2) B0H 13 HN29W25611T-50H Program (1), (4) (With CA before SC) Command /Address CDE WE SC Low Data input Data input Program start 10H/11H SA (1) SA (2) CA (1) CA (2) CA (1)' CA (2)' 40H Program (1), (4) (With CA after SC) Command /Address CDE WE SC Low Data input Data input Data input Program start 10H/11H SA (1) SA (2) CA (1) CA (2) CA (1)' CA (2)' 40H Program (1), (4) (Without CA) Command/Address CDE WE SC Low Data input Program start 10H/11H SA (1) SA (2) 40H Program (2) Command/Address CDE WE SC Low Data input Program start 1FH SA (1) SA (2) 40H 14 HN29W25611T-50H Program (3) Command/Address CDE WE SC Low Data input Program start 0FH SA (1) SA (2) 40H ID Read Mode Command/Address CDE WE SC Low Manufacture Device code Manufacture code output output code output 90H Data Recovery Read Mode Command/Address CDE WE SC Low Data output 01H Data Recovery Write Mode Command/Address CDE WE SC Low Program start 12H SA (1) SA (2) 40H 15 HN29W25611T-50H Status Transition Deep standby RES 00H/F0H FFH CE 90H FFH CE 20H FFH Sector Erase setup SA (1), SA (2) Sector address input B0H Erase start OE Read (1) / (2) SA (1), SA (2) setup VCC Column address input CA(1) CA(2) Sector address OE, SC input Power off CA(1)' OE CA(2)' SC Read (1) / (2) ID read setup CDE, OE ID read BUSY Status register read Erase finish Column address SC, CDE PD(m) input CA(1) CA(2) CA(1)' to CA(2)' PD(m+j) CE Standby PD0 to 10H SA (1), PD2111 OE 40H Output /11H SA (2) Sector address Program Program Program disable (1)/(4) setup input data input start FFH SC, CDE Program finish Status register read PD0 to 1FH SA (1), PD2111*3 OE 40H /0FH Program (2)/(3) SA (2) Sector address Status register Program Program read input data input setup start SC, CDE FFH Program finish Program error or Status register clear 50H Erase error CE*2 FFH*2 ERROR Data recovery OE, SC Data recovery read setup read SA(1) 1 Error CE Output 12H* Program retry SA(2) Sector address 40H standby disable setup input *4 FFH OE Status register read OE Status register read 01H*1 Notes: 1. 2. 3. 4. (01H)/(12H) Data recovery read/write can be used only for Program (1), (2), (3), (4) errors. When reset is done by CE or FFH, error status flag is cleared. When Program (3) mode, input data is PD2048 to PD2111. When Error standby, ICC3 level is current. 16 HN29W25611T-50H Absolute Maximum Ratings Parameter VCC voltage VSS voltage All input and output voltages Operating temperature range Storage temperature range Storage temperature under bias Symbol VCC VSS Vin, Vout Topr Tstg Tbias Value –0.6 to +7 0 –0.6 to +7 0 to +70 –65 to +125 –10 to +80 Unit V V V ˚C ˚C ˚C 3 1, 2 Notes 1 Notes: 1. Relative to VSS . 2. Vin, Vout = –2.0 V for pulse width ≤ 20 ns. 3. Device storage temperature range before programming. Capacitance (Ta = 25˚C, f = 1 MHz) Parameter Input capacitance Output capacitance Symbol Cin Cout Min — — Typ — — Max 6 12 Unit pF pF Test conditions Vin = 0 V Vout = 0 V 17 HN29W25611T-50H DC Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to +70˚C) Parameter Input leakage current Output leakage current Standby V CC current Symbol Min I LI I LO I SB1 I SB2 Deep standby VCC current Operating VCC current I SB3 I CC1 I CC2 Operating VCC current (Program) I CC3 Operating VCC current (Erase) Input voltage I CC4 VIL VIH Input voltage (RES pin) VILR VIHR Output voltage VOL VOH — — — — — — — — — –0.3* 2.0 –0.2 1, 2 Typ — — 0.3 30 1 20 30 20 20 — — — Max 2 2 1 50 5 25 50 40 40 0.8 VCC + 0.3* 0.2 VCC + 0.2 0.4 — 3 Unit µA µA mA µA µA mA mA mA mA V V V V V V Test conditions Vin = VSS to V CC Vout = VSS to V CC CE = VIH CE = VCC ± 0.2 V, RES = VCC ± 0.2 V RES = VSS ± 0.2 V Iout = 0 mA, f = 0.2 MHz Iout = 0 mA, f = 20 MHz In programming In erase VCC – 0.2 — — 2.4 — — I OL = 2 mA I OH = –2 mA Notes: 1. VIL min = –1.0 V for pulse width ≤ 50 ns in the read operation. VIL min = –2.0 V for pulse width ≤ 20 ns in the read operation. 2. VIL min = –0.6 V for pulse width ≤ 20 ns in the erase/data programming operation. 3. VIH max = VCC + 1.5 V for pulse width ≤ 20 ns. If VIH is over the specified maximum value, the operations are not guaranteed. AC Characteristics (VCC = 3.3 V ± 0.3 V, Ta = 0 to +70˚C) Test Conditions • • • • • Input pulse levels: 0.4 V/2.4 V Input pulse levels for RES: 0.2 V/VCC – 0.2 V Input rise and fall time: ≤ 5 ns Output load: 1 TTL gate + 100 pF (Including scope and jig.) Reference levels for measuring timing: 0.8 V, 1.8 V 18 HN29W25611T-50H Power on and off, Serial Read Mode Parameter Write cycle time Serial clock cycle time CE setup time CE hold time Write pulse time Write pulse high time Address setup time Address hold time Data setup time Data hold time SC to output delay OE setup time for SC OE low to output low-Z OE setup time before read OE setup time before command write SC to output hold OE high to output float WE to SC delay time RES to CE setup time SC to OE hold time SC pulse width SC pulse low time SC setup time for CE CDE setup time for WE CDE hold time for WE VCC setup time for RES RES to V CC hold time CE setup time for RES RDY/Busy undefined for V CC off RES high to device ready CE pulse high time CE , WE setup time for RES RES to CE , WE hold time Symbol t CWC t SCC t CES t CEH t WP t WPH t AS t AH t DS t DH t SAC t OES t OEL t OER t OEWS t SH t DF t WSD t RP t SOH t SP t SPL t SCS t CDS t CDH t VRS t VRH t CESR t DFP t BSY t CPH t CWRS t CWRH Min 120 50 0 0 60 40 50 10 50 10 — 0 0 250 0 15 — 50 1 50 20 20 0 0 20 1 1 1 0 — 200 0 0 Typ — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Max — — — — — — — — — — 50 — 40 — — — 40 — — — — — — — — — — — — 1 — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms ns ns ns ns ns ns µs µs µs ns ms ns ns ns CE = VIH CE = VIH CE = OE = VIL, WE = VIH CE = VIL, WE = VIH 1 2 CE = OE = VIL, WE = VIH CE = VIL, OE = VIH Test conditions Notes 19 HN29W25611T-50H Parameter SC setup for WE CE hold time for OE SA (2) to CA (2) delay time RDY/Busy setup for SC Symbol t SW t COH t SCD t RS Min 50 0 — 200 — — Typ — — — — — 45 Max — — 30 — 1 — Unit ns ns µs ns µs µs Test conditions Notes Time to device busy on read t DBR mode Busy time on reset mode t RBSY Notes: 1. t DF is a time after which the I/O pins become open. 2. t WSD (min) is specified as a reference point only for SC, if t WSD is greater than the specified tWSD (min) limit, then access time is controlled exclusively by tSAC. 20 HN29W25611T-50H Program, Erase and Erase Verify Parameter Write cycle time Serial clock cycle time CE setup time CE hold time Write pulse time Write pulse high time Address setup time Address hold time Data setup time Data hold time Symbol t CWC t SCC t CES t CEH t WP t WPH t AS t AH t DS t DH Min 120 50 0 0 60 40 50 10 50 10 0 40 250 — — — — — — 50 2 200 20 20 0 30 50 0 20 Typ — — — — — — — — — — — — — — — 1.5 3.0 2.5 3.5 — — — — — — — — — — Max — — — — — — — — — — — — — 150 1 10.0 20.0 20.0 30.0 — — — — — — — — — — Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ms ms ms ms µs µs ns ns ns ns ns ns ns ns CDE = VIL Test conditions Note OE setup time before command t OEWS write OE setup time before status polling OE setup time before read Time to device busy Time to device busy on read mode Auto erase time Auto program time Program(1), (3) Program(2) Program(4), Data recovery write WE to SC delay time WE to SC delay time on recovery read mode CE pulse high time SC pulse width SC pulse low time Data setup time for SC Data hold time for SC SC setup for WE SC setup for CE SC hold time for WE t OEPS t OER t DB t DBR t ASE t ASP t ASP t ASP t WSD t WSDR t CPH t SP t SPL t SDS t SDH t SW t SCS t SCHW 21 HN29W25611T-50H Parameter CE to output delay OE to output delay OE high to output float RES to WE setup time CDE setup time for WE CDE hold time for WE CDE setup time for SC CDE hold time for SC Next cycle ready time CDE to OE hold time CDE to output delay CDE to output invalid CE setup time for OE CE hold time for OE CDE to OE setup time OE setup time for SC OE low to output low-Z SC to output delay SC to output hold RDY/Busy setup for SC CE hold time for WE CE hold time for WE on recovery read mode WE hold time for WE Busy time on read mode Note: Symbol t CE t OE t DF t RP t CDS t CDH t CDSS t CDSH t RDY t CDOH t CDAC t CDF t COS t COH t CDOS t OES t OEL t SAC t SH t RS t CWH t CWHR t WWH t RBSY Min — — — 1 0 20 1.5 30 0 50 — — 0 0 20 0 0 — 15 200 1.0 2 1 — Typ — — — — — — — — — — — — — — — — — — — — — — — 45 Max 120 60 40 — — — — — — — 50 100 — — — — 40 50 — — — — — — Unit ns ns ns ms ns ns µs ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs µs µs 1 Test conditions Note 1. t DF is a time after which the I/O pins become open. 22 HN29W25611T-50H Timing Waveforms Power on and off Sequence VCC tVRS CE tRP WE tCES tCEH tCESR tRP tCES tCEH tCESR tCWRH tVRH     !    tCWRS tDFP RES *1 *2 *1 tBSY High-Z Ready tBSY RDY /Busy Notes: 1. RES must be kept at the VILR level referred to DC characteristics at the rising and falling edges of VCC to guarantee data stored in the chip. 2. RES must be kept at the VIHR level referred to DC characteristics while I/O7 outputs the VOL level in the status data polling and RDY/Busy outputs the VOL level. 3. : Undefined 23 HN29W25611T-50H Serial Read (1) (2) Timing Waveform *1 tCPH tCWC tWPH tOER *3 CE tCES OE tOEWS WE tCDS CDE tWP tCDS tCDH SC tSCS I/O0 to I/O7 00H /F0H RES tRP RDY /Busy tDBR SA(1) SA(2) tDS tDH tAS tAH tAS tAH tOEL tWP tWP tOES tWSD tSCC tSP tSCC *2 tCWC tWPH tCOH tCEH tWP tCDH tSOH tCDS tDS tDH tSPL tSAC tSH tSAC tSH D1out/D2049out tSAC tSAC tDF D0out/D2048out D2111out/D2111out *2 FFH tRBSY tRS High-Z Notes: 1. The status returns to the standby at the rising edge of CE. 2. Output data is not valid after the number of the SC pulse exceeds 2112 and 64 in the serial read mode (1)and (2), respectively. 3. After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the VIH level. Serial Read (1) with CA before SC Timing Waveform h-1 cycle * 5 CE tCES OE tOEWS WE tCDS CDE tCDH SC tSCS I/O0 to I/O7 tRP RES tDBR RDY /Busy tRBSY tRS High-Z 00H SA(1) SA(2) CA(1) CA(2) D(n)out D(n+1)out D(n+i)out *2 * tCOH 1 tCPH tCWC tWPH tCWC tWPH tCWC tWPH tOEWS tOER tSW tWP tWP tSCD tWSD tWP tOES tSCC tSP tDS tDH tAS tAH tAS tAH tAS tAH tAS tAH tSAC tSPL tSAC t tOEL SAC t tSH SH tSAC tDF tAS tAH tAS tAH CA(2)' tSAC tOEL tSP tSPL tSAC tSAC tSH tSH D(m)out D(m+1)out tSAC tDF tDS tDH tSCC *2 tSOH tCWC tWPH tOER * tCEH4 tCWC tWPH tWP tCDS t WP tWP tWP tOES tSCC tSCC *3 tSOH tWP tCDH tCDS CA(1)' D(m+j)out *3 FFH Notes: 1. 2. 3. 4. The status returns to the Standby at the rising edge of CE. Output data is not valid after the number of the SC pulse exceeds (2112-n). (i ≤ 2111-n, 0 ≤ n ≤ 2111) Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111) After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the VIH level. 5. This interval can be repeated (h-1) cycle. (1≤ h ≤ 2048 + 64) 24 HN29W25611T-50H Serial Read (1) with CA after SC Timing Waveform h cycle* CE tCES OE tOEWS WE tWP CDE tCDH tCDS SC tSCS I/O0 to I/O7 tRP RES tDBR RDY /Busy tRBSY tRS High-Z 00H SA(1) SA(2) D0out D1out D(k)out *2 5 tCOH *1 tCPH tCWC tWPH tOER tSW tWP tWP tOES tCDS tWSD tSCC tSCC 2 * tSOH tOEWS tCWC tWPH tOER 4 tCEH* tCWC tWPH tWP tWP tOES tSCC tSCC *3 tSOH tWP tCDH tCDS tDS tDH tAS tAH tAS tAH tSAC t t tOEL t SP SPL tSH SAC tSAC tSH tSAC tDF tSP tAS tAH tAS tAH tOEL CA(1) CA(2) tSAC tSAC tSPL tSAC tSH tSH D(m)out D(m+1)out tSAC tDF tDS tDH D(m+j)out *3 FFH Notes: 1. 2. 3. 4. 5. The status returns to the Standby at the rising edge of CE. Output data is not valid after the number of the SC pulse exceeds 2112. (0 ≤ k ≤ 2111) Output data is not valid after the number of the SC pulse exceeds (2112-m). (j ≤ 2111-m, 0 ≤ m ≤ 2111) After any commands are written, the status can return to the standby after the command FFH is input and CE turns to the VIH level. This interval can be repeated h cycle. (1≤ h ≤ 2048 + 64) Erase and Status Data Polling Timing Waveform (Sector Erase) CE tCES OE tOEWS WE tCDS CDE tWP tCDS tCDH SC tSCS I/O0 to I/O7 20H RES tRP RDY /Busy High-Z tDB *1 *2 High-Z SA(1) SA(2) B0H IO7 = VOL IO7 = VOH tDS tDH tAS tAH tAS tAH tDS tDH tDF tDF tWP tWP tWP tCDS tCDH tCDH tSCHW tCWC tWPH tCWC tWPH tCWC tWPH tCEH tOEPS tCE tOE tASE tCOS tRDY tCDS Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy outputs a VOL. 2. The status returns to the standby status after RDY/Busy returns to High-Z. 25 HN29W25611T-50H Program (1) and Status Data Polling Timing Waveform CE tCES OE tOEWS tCWC tWPH WE tCDS CDE tCDH SC tSCS I/O0 to I/O7 10H RES tRP RDY /Busy High-Z *2 SA (1) SA (2) PD0 PD1 PD2111 40H tDB I/O7 = VOL I/O7 = VOH *3 High-Z tDS tDH tAS tAH tAS tAH tSDH tSP tSDS tSP tDS tDH tDF tDF tCDH tSCC tSPL *1 tCDH tSCHW tWPtCDS tWP tWP tCDSS tSW tWP tASP tCWC tWPH tOEPS tOE tRDY tCEH tCE tCOS tCDS Notes: 1. 2. 3. 4. The programming operation is not guranteed when the number of the SC pulse exceeds 2112. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL. The status returns to the standby status after RDY/Busy returns to High-Z. By using program (1), data can be programmed additionally for each sector before erase. 26 HN29W25611T-50H Program (1) with CA before SC and Status Data Polling Timing Waveform h–1 cycle*6 CE tCES OE tOEWS tCWC tCWC tWPH tWPH tCWC tWPH tCWC tWPH tSW tCDS tWP tCDS tWP CDE tSCS SC tDS I/O0 to I/O7 10H RES tRP RDY /Busy Notes: 1. 2. 3. 4. 5. 6. High-Z tDB *3 The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111) The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111) Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL. The status returns to the standby status after RDY/Busy returns to High-Z. By using program (1), data can be programmed additionally for each sector before erase. This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64) High-Z*4 SA(1) SA(2) CA(1) CA(2) PD(n) PD(n+1) PD(n+i)*1 CA(1)' CA(2)' PD(m) PD(m+1)PD(m+j)*2 40H I/O7=VOL I/O7=VOH t tDHAS tAH tAS tAH tAS tAH tAS tCDH tCDH tSCC tSPL tSP *1 tSP tCDSH tAH tCDH tAH tSDS tSCC tSPL tSDH *2 tSP tSP tDS tWP tWP tWP tCDSS tCDS tWP tWP tCDSS tWP tSW tCDH tSCHW tDH tDF tDF tASP tCDS tCWC tWPH tCEH tCE tCOS tOEPS tOE tRDY WE tAH t tSDS SDH tAS tAS Program (1) with CA after SC and Status Data Polling Timing Waveform h cycle*6 CE tCES OE tOEWS tCWC tCWC tWPH tWPH tSW tCDS tWP tCDS tWP CDE tSCS SC tDS I/O0 to I/O7 10H RES tRP RDY /Busy Notes: 1. 2. 3. 4. 5. 6. High-Z tDB *3 The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111) The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111) Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL. The status returns to the standby status after RDY/Busy returns to High-Z. By using program (1), data can be programmed additionally for each sector before erase. This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64) High-Z*4 SA(1) SA(2) PD0 PD1 PD(k)*1 CA(1) CA(2) PD(m) PD(m+1)PD(m+j)*2 40H I/O7=VOL I/O7=VOH t tDHAS tAH tAS tAH tSDS tCDH tCDH tSCC tSPL tSDH tSP *1 tSP tCDSH tAH tCDH tAH tSCC tSPL tSDH *2 tSP tSP tWP tCDSS tCDS tWP tWP tCDSS tWP tSW tCDH tSCHW tDH tDF tDF tASP tCDS tCWC tWPH tCEH tCE tCOS tOEPS tOE tRDY WE tAS tAS tSDS tDS 27 HN29W25611T-50H Program (2) and Status Data Polling Timing Waveform CE tCES OE tOEWS tCWC tWPH WE tCDS CDE tCDH SC tSCS I/O0 to I/O7 1FH RES tRP RDY /Busy High-Z *2 SA (1) SA (2) PD0 PD1 PD2111 40H tDB I/O7 = VOL I/O7 = VOH *3 High-Z tDS tDH tAS tAH tAS tAH tSDH tSP tSDS tSP tDS tDH tDF tCDH tSCC tSPL *1 tCDH tSCHW tWPtCDS tWP tWP tCDSS tSW tWP tASP tCDS tCWC tWPH tOEPS tOE tRDY tCEH tCE tCOS Notes: 1. 2. 3. 4. The programming operation is not guranteed when the number of the SC pulse exceeds 2112. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL. The status returns to the standby status after RDY/Busy returns to High-Z. By using program (2), the programmed data of each sector must be erased before programming next data. 28 HN29W25611T-50H Program (3) and Status Data Polling Timing Waveform CE tCES OE tOEWS tCWC tWPH WE tCDS CDE tCDH SC tSCS I/O0 to I/O7 0FH RES tRP RDY /Busy High-Z *2 SA (1) SA (2) PD2048 PD2049 PD2111 40H tDB I/O7 = VOL I/O7 = VOH *3 High-Z tDS tDH tAS tAH tAS tAH tSDH tSP tSDS tSP tDS tDH tDF tCDH tSCC tSPL *1 tCDH tSCHW tWPtCDS tWP tWP tCDSS tSW tWP tASP tCDS tCWC tOEPS tOE tRDY tCEH tCE tCOS Notes: 1. 2. 3. 4. The programming operation is not guranteed when the number of the SC pulse exceeds 64. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL. The status returns to the standby status after RDY/Busy returns to High-Z. By using program (3), the data can be programmed additionally for each sector before erase. 29 HN29W25611T-50H Program (4) and Status Data Polling Timing Waveform CE tCES OE tOEWS tCWC tWPH WE tCDS CDE tCDH SC tSCS I/O0 to I/O7 11H RES tDBR tRP RDY /Busy tRBSY Notes: 1. 2. 3. 4. The programming operation is not guranteed when the number of the SC pulse exceeds 2112. Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL. The status returns to the standby status after RDY/Busy returns to High-Z. By using program (4), data can be rewritten for each sector. tRS High-Z *2 SA (1) SA (2) PD0 PD1 PD2111 40H tDB I/O7 = VOL I/O7 = VOH *3 High-Z tDS tDH tAS tAS tAH tCDH tWSD tAH tSDH tSP tSDS tSP tDS tDH tDF tSCC tSPL *1 tCDH tSCHW tWPtCDS tWP tWP tCDSS tSW tWP tASP tCDS tCWC tWPH tOEPS tOE tRDY tCEH tCE tCOS 30 HN29W25611T-50H Program (4) with CA before SC and Status Data Polling Timing Waveform h–1 cycle*6 CE tCES OE tOEWS tCWC tCWC tWPH tWPH tCWC tWPH tCWC tWPH tSW tCDS tWP tCDS tWP CDE tSCS SC tDS I/O0 to I/O7 11H RES tRP RDY /Busy Notes: 1. 2. 3. 4. 5. 6. tDBR tRBSY tRS High-Z tDB *3 The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – n).(i ≤ 2111 – n, 0 ≤ n ≤ 2111) The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111) Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL. The status returns to the standby status after RDY/Busy returns to High-Z. By using program (4), data can be rewritten for each sector. This interval can be repeated (h – 1) cycle.(1 ≤ h ≤ 2048 + 64) High-Z*4 SA(1) SA(2) CA(1) CA(2) PD(n) PD(n+1) PD(n+i)*1 CA(1)' CA(2)' PD(m) PD(m+1)PD(m+j)*2 40H I/O7=VOL I/O7=VOH t tDHAS tAH tAS tAH tAS tAH tAS tCDH tWSD tCDH tSCC tSPL tSP *1 tSP tCDSH tAH tCDH tAH tSDS tSCC tSPL tSDH *2 tSP tSP tDS tWP tWP tWP tCDSS tCDS tWP tWP tCDSS tWP tSW tCDH tSCHW tDH tDF tDF tASP tCDS tCWC tWPH tCEH tCE tCOS tOEPS tOE tRDY WE tAH t tSDS SDH tAS tAS Program (4) with CA after SC and Status Data Polling Timing Waveform h cycle*6 CE tCES OE tOEWS tCWC tCWC tWPH tWPH tSW tCDS tWP tCDS tWP CDE tSCS SC tDS I/O0 to I/O7 11H RES tRP RDY /Busy Notes: 1. 2. 3. 4. 5. 6. tDBR SA(1) SA(2) PD0 PD1 PD(k)*1 CA(1) CA(2) PD(m) PD(m+1)PD(m+j)*2 40H I/O7=VOL I/O7=VOH t tDHAS tAH tAS tAH tSDS tCDH tCDH tWSD tSCC tSPL tSDH tSP *1 tSP tCDSH tAH tCDH tAH tSCC tSPL tSDH *2 tSP tSP tWP tCDSS tCDS tWP tWP tCDSS tWP tSW tCDH tSCHW tDH tDF tDF tASP tCDS tCWC tWPH tCEH tCE tCOS tOEPS tOE tRDY WE tAS tAS tSDS tDS tRBSY tRS High-Z tDB *3 The programming operation is not guaranteed when the number of the SC pulse exceeds 2112.(0 ≤ k ≤ 2111) The programming operation is not guaranteed when the number of the SC pulse exceeds (2112 – m).(j ≤ 2111 – m, 0 ≤ m ≤ 2111) Any commands, including reset command FFH, cannot be input while RDY/Busy is VOL. The status returns to the standby status after RDY/Busy returns to High-Z. By using program (4), data can be rewritten for each sector. This interval can be repeated h cycle.(1 ≤ h ≤ 2048 + 64) High-Z*4 31 HN29W25611T-50H ID and Status Register Read Timing Waveform *1 CE tCES OE tOEWS WE tCDS CDE tSCHW SC tSCS I/O0 to I/O7 90H RES tRP RDY /Busy Note: 1. The status returns to the standby at the rising edge of CE. High-Z Manufacturer Device Manufacturer code code code Status register tDS tDH t OE tCDF tCDAC tCDF tCDAC tDF tSCS tOE tDF tWP tCDH tCDCH tOEPS tCOH tCOS tCOH *1 32 HN29W25611T-50H Data Recovery Read Timing Waveform *1 tCPH tCES OE tOEWS WE tCDS CDE tWSDR SC tSCS I/O0 to I/O7 01H RES High-Z RDY /Busy Notes: 1. The status returns to the standby at the rising edge of CE. 2. Output data is not valid after the number of the SC pulse exceed 2112 in the recovery data read mode. 3. After any commands are written, the status can turns to the standby after the command FFH is input and CE turns to the VIH level. D0out D1out D2111out High *2 FFH tDS tDH tWP tCDH tOES tSCC tSP tOEL tSAC tSCC *2 tSOH tCDS tOER tCDOS tWP tCDH tCWHR tCOH *3 CE tCEH tSPL t t tSH SAC tSH SAC tSAC tDF tDS tDH 33 HN29W25611T-50H Data Recovery Write Timing Waveform CE tCES OE tOEWS WE tCDS CDE tWP tCDS tCDH SC tSCS I/O0 to I/O7 12H RES tRP RDY /Busy High-Z tDB *1 *2 High-Z SA(1) SA(2) 40H IO7 = VOL IO7 = VOH tDS tDH tAS tAH tAS tAH tDS tDH tDF tDF tWP tWP tWP tCDS tCDH tCDH tSCHW tASP tCWC tWPH tCWC tWPH tCWC tWPH tCEH tOEPS tCE tOE tCOS tRDY tCDS Notes: 1. Any commands,including reset command FFH, cannot be input while RDY/Busy is VOL. 2. The status returns to the standby status after RDY/Busy returns to High-Z. 34 HN29W25611T-50H Clear Status Register Timing Waveform *1 CE tCES OE tOEWS WE tWP tCDH CDE tCDS SC tSCS tDS tDH tDS tDH tSCS tDS tDH tWWH tCDS tWP tCDH tCPH tCES tCWH tOEWS tCDS tWP tCDH I/O0 to I/O7 50H RES High High-Z Next Command Next Command RDY /Busy Note 1. The status returns to the standby at the rising edge of CE. 35 HN29W25611T-50H Function Description Status Register: The HN29W25611T outputs the operation status data as follows: I/O7 pin outputs a V OL to indicate that the memory is in either erase or program operation. The level of I/O7 pin turns to a VOH when the operation finishes. I/O5 and I/O4 pins output V OLs to indicate that the erase and program operations complete in a finite time, respectively. If these pins output VOHs, it indicates that these operations have timed out. When these pins monitor, I/O7 pin must turn to a VOH . To execute other erase and program operation, the status data must be cleared after a time out occurs. From I/O0 to I/O3 pins are reserved for future use. The pins output VOLs and should be masked out during the status data read mode. The function of the status register is summarized in the following table. I/O I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Flag definition Ready/ Busy Reserved Erase check Program check Reserved Reserved Reserved Reserved Definition VOH = Ready, VOL = Busy Outputs a V OL and should be masked out during the status data poling mode. VOH = Fail, VOL = Pass VOH = Fail, VOL = Pass Outputs a V OL and should be masked out during the status data poling mode. Requirement for System Specifications Item Usable sectors (initially) Spare sectors ECC (Error Correction Code) Program/Erase endurance Min 16,057 290 3 — Typ — — — — Max 16,384 — — 3 × 10 5 Unit sector sector bit/sector cycle 36 HN29W25611T-50H Unusable Sector Initially, the HN29W25611T includes unusable sectors. The unusable sectors must be distinguished from the usable sectors by the system as follows. 1. Check the partial invalid sectors in the devices on the system. The usable sectors were programmed the following data. Refer to the flowchart “Indication of unusable sectors”. Initial Data of Usable Sectors Column address Data 0H to 81FH FFH 820H 1CH 821H 71H 822H C7H 823H 1CH 824H 71H 825H C7H 826H to 83FH FFH 2. Do not erase and program to the partial invalid sectors by the system. START Sector number = 0 Read data Column address = 820H to 825H Sector number = Sector number + 1 Bad sector*2 No Check data*1 Yes No Sector number = 16,383 Yes END Notes: 1. Refer to table "Initial data of usable sectors". 2. Bad sectors are installed in system. Indication of Unusable Sectors 37 HN29W25611T-50H Requirements for High System Reliability The device may fail during a program, erase or read operation due to write or erase cycles. The following architecture will enable high system reliability if a failure occurs. 1. For an error in read operation: An error correction more than 3-bit error correction per each sector read is required for data reliability. 2. For errors in program or erase operations: The device may fail during a program or erase operation due to write or erase cycles. The status register indicates if the erase and program operation complete in a finite time. When an error happens in the sector, try to reprogram the data into another sector. Avoid further system access to the sector that error happens. Typically, recommended number of a spare sectors are 1.8% of initial usable 16,057 sectors by each device. If the number of failed sectors exceeds the number of the spare sectors, usable data area in the device decreases. For the reprogramming, do not use the data from the failed sectors, because the data from the failed sectors are not fixed. So the reprogram data must be the data reloaded from outer buffer, or use the Data recovery read mode or the Data recovery write mode (see the “Mode Description” and under figure “Spare Sectors in Program Error”). To avoid consecutive sector failures, choose addresses of spare sectors as far as possible from the failed sectors. 38 HN29W25611T-50H START Program start Set an usable sector Program end Check RDY/Busy Check status Yes No Clear status register Load data from external buffer Data recovery read Data recovery write Program start Set another usable sector Program end Check RDY/Busy Check status Yes Check status: Status register read END No Spare Sectors in Program Error 39 HN29W25611T-50H Memory Structure bit 16,384 sectors sector byte (8 bits) 2,112 bytes (16,896 bits) Bit: Minimum unit of data. Byte: Input/output data unit in programming and reading. (1 byte = 8 bits) Sector: Page unit in erase, programming and reading. (1 sector = 2,112 bytes = 16,896 bits) Device: 1 device = 16,384 sectors. 40 HN29W25611T-50H Package Dimensions HN29W25611T Series (TFP-48D) Unit: mm 25 12.00 12.40 Max 48 1 0.50 *0.22 ± 0.08 0.08 M 0.20 ± 0.06 0.45 Max 1.20 Max 24 *0.17 ± 0.05 0.125 ± 0.04 18.40 0.80 20.00 ± 0.20 0° – 5° 0.13 ± 0.05 0.50 ± 0.10 Hitachi Code JEDEC EIAJ Mass (reference value) TFP-48D Conforms Conforms 0.49 g 0.10 *Dimension including the plating thickness Base material dimension 41 HN29W25611T-50H Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/index.htm For further information write to: Hitachi Europe GmbH Electronic components Group Dornacher Straße 3 D-85622 Feldkirchen, Munich Germany Tel: (89) 9 9180-0 Fax: (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: (1628) 585000 Fax: (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: (2) 2718-3666 Fax: (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: (2) 735 9218 Fax: (2) 730 0281 Telex: 40815 HITEC HX Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: (408) 433-1990 Fax: (408) 433-0223 Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan. 42