R1LP0408CSB-7LI

R1LP0408C-I Series Wide Temperature Range Version 4 M SRAM (512-kword × 8-bit) REJ03C0067-0100Z Rev. 1.00 Aug.01.2003 Description The R1LP0408C-I is a 4-Mbit static RAM organized 512-kword × 8-bit. R1LP0408C-I Series has realized higher density, higher performance and low power consumption by employing CMOS process technology (6-transistor memory cell). The R1LP0408C-I Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin TSOP II. Features • Single 5 V supply: 5 V ± 10% • Access time: 55/70 ns (max) • Power dissipation:  Active: 10 mW/MHz (typ)  Standby: 4 µW (typ) • Completely static memory.  No clock or timing strobe required • Equal access and cycle times • Common data input and output.  Three state output • Directly TTL compatible.  All inputs and outputs • Battery backup operation. • Operating temperature: −40 to +85°C Rev.1.00, Aug.01.2003, page 1 of 13 R1LP0408C-I Series Ordering Information Type No. R1LP0408CSP-5SI R1LP0408CSP-7LI R1LP0408CSB-5SI R1LP0408CSB-7LI R1LP0408CSC-5SI R1LP0408CSC-7LI Access time 55 ns 70 ns 55 ns 70 ns 55 ns 70 ns 400-mil 32-pin plastic TSOP II reverse (32P3Y-J) 400-mil 32-pin plastic TSOP II (32P3Y-H) Package 525-mil 32-pin plastic SOP (32P2M-A) Rev.1.00, Aug.01.2003, page 2 of 13 R1LP0408C-I Series Pin Arrangement 32-pin SOP 32-pin TSOP A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 VCC A15 A17 WE# A13 A8 A9 A11 OE# A10 CS# I/O7 I/O6 I/O5 I/O4 I/O3 32-pin TSOP (reverse) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (Top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS Pin Description Pin name A0 to A18 I/O0 to I/O7 CS# (CS) OE# (OE) WE# (WE) VCC VSS Function Address input Data input/output Chip select Output enable Write enable Power supply Ground Rev.1.00, Aug.01.2003, page 3 of 13 R1LP0408C-I Series Block Diagram LSB V CC V SS • • • • • MSB A11 A9 A8 A15 A18 A10 A13 A17 A16 A14 A12 Row Decoder Memory Matrix 2,048 × 2,048 I/O0 Input Data Control I/O7 • • Column I/O Column Decoder • • LSB A3 A2A1A0 A4 A5 A6 A7 MSB • • CS# WE# OE# Timing Pulse Generator Read/Write Control Rev.1.00, Aug.01.2003, page 4 of 13 R1LP0408C-I Series Operation Table WE# × H H L L CS# H L L L L OE# × H L H L Mode Not selected Output disable Read Write Write VCC current ISB, ISB1 ICC ICC ICC ICC I/O0 to I/O7 High-Z High-Z Dout Din Din Ref. cycle   Read cycle Write cycle (1) Write cycle (2) Note: H: VIH, L: VIL, ×: VIH or VIL Absolute Maximum Ratings Parameter Power supply voltage relative to VSS Terminal voltage on any pin relative to VSS Power dissipation Operating temperature Storage temperature range Storage temperature range under bias Symbol VCC VT PT Topr Tstg Tbias Value −0.5 to +7.0 −0.5* to VCC + 0.3* 1 2 Unit V V W °C °C °C 0.7 −40 to +85 −65 to +150 −40 to +85 Notes: 1. VT min: −3.0 V for pulse half-width ≤ 30 ns. 2. Maximum voltage is +7.0 V. DC Operating Conditions (Ta = −40 to +85°C) Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Note: VIH VIL Min 4.5 0 2.2 −0.3* 1 Typ 5.0 0   Max 5.5 0 VCC + 0.3 0.8 Unit V V V V 1. VIL min: −3.0 V for pulse half-width ≤ 30 ns. Rev.1.00, Aug.01.2003, page 5 of 13 R1LP0408C-I Series DC Characteristics Parameter Input leakage current Output leakage current Operating current Average operating current Symbol Min Typ* Max Unit Test conditions |ILI| |ILO| ICC ICC1       1.5 8 1 1 3 25 µA µA mA mA Vin = VSS to VCC CS# = VIH or OE# = VIH or WE# = VIL or VI/O = VSS to VCC CS# = VIL, Others = VIH/ VIL, II/O = 0 mA Min. cycle, duty = 100%, CS# = VIL, Others = VIH/VIL II/O = 0 mA Cycle time = 1 µs, duty = 100%, II/O = 0 mA, CS# ≤ 0.2 V, VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V CS# = VIH Vin ≥ 0 V, CS# ≥ VCC − 0.2 V 1 ICC2  2 5 mA Standby current Standby current to +85°C to +40°C −20°C to +25°C Output low voltage Output high voltage ISB ISB1 ISB1 ISB1 VOL VOH VOH2         0.1   1.0* 1.0* 2 3 2 3 0.5 20* 10* 10* 3* 3 2 2 3 2 mA µA µA µA µA µA µA V V V 0.8* 0.8*  10* 3* 3 0.4   IOL = 2.1 mA IOH = −1.0 mA IOH = −0.1 mA 2.4  2.6  Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and specified loading, and not guaranteed. 2. L version. (−7LI) 3. SL version. (−5SI) Capacitance (Ta = +25°C, f = 1.0 MHz) Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min   Typ   Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1 1. This parameter is sampled and not 100% tested. Rev.1.00, Aug.01.2003, page 6 of 13 R1LP0408C-I Series AC Characteristics (Ta = −40 to +85°C, VCC = 5 V ± 10%, unless otherwise noted.) Test Conditions • Input pulse levels: VIL = 0.4 V, VIH = 2.4 V • Input rise and fall time: 5 ns • Input and output timing reference levels: 1.5 V • Output load: 1 TTL Gate + CL (50 pF) (R1LP0408C-5I) 1 TTL Gate + CL (100 pF) (R1LP0408C-7I) (Including scope and jig) Read Cycle R1LP0408C-I -5 Parameter Read cycle time Address access time Chip select access time Output enable to output valid Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Output hold from address change Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH Min 55    10 5 0 0 10 Max  55 55 25   20 20  -7 Min 70    10 5 0 0 10 Max  70 70 35   25 25  Unit ns ns ns ns ns ns ns ns ns 2 2 1, 2 1, 2 Notes Rev.1.00, Aug.01.2003, page 7 of 13 R1LP0408C-I Series Write Cycle R1LP0408C-I -5 Parameter Write cycle time Chip selection to end of write Address setup time Address valid to end of write Write pulse width Write recovery time Write to output in high-Z Data to write time overlap Data hold from write time Output active from end of write Output disable to output in high-Z Symbol tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW tOHZ Min 55 50 0 50 40 0 0 25 0 5 0 Max       20    20 -7 Min 70 60 0 60 50 0 0 30 0 5 0 Max       25    25 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2, 7 3, 12 6 1, 2, 7 4 5 Notes Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going high or WE# going high. tWP is measured from the beginning of write to the end of write. 4. tCW is measured from CS# going low to the end of write. 5. tAS is measured from the address valid to the beginning of write. 6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle. 7. During this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE# transition, the output remain in a high impedance state. 9. Dout is the same phase of the write data of this write cycle. 10. Dout is the read data of next address. 11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention. tWP ≥ tDW min + tWHZ max Rev.1.00, Aug.01.2003, page 8 of 13 R1LP0408C-I Series Timing Waveform Read Timing Waveform (WE# = VIH) tRC Address Valid address tAA tCO CS# tLZ tOE tOLZ OE# tOHZ tHZ Dout High impedance Valid data tOH Rev.1.00, Aug.01.2003, page 9 of 13 R1LP0408C-I Series Write Timing Waveform (1) (OE# Clock) tWC Address Valid address tAW OE# tCW CS# *8 tWR tAS tWP WE# tOHZ Dout High impedance tDW Din Valid data tDH Rev.1.00, Aug.01.2003, page 10 of 13 R1LP0408C-I Series Write Timing Waveform (2) (OE# Low Fixed) tWC Address Valid address tCW tWR CS# *8 tAW tWP WE# tAS tWHZ tOW tOH *9 *10 Dout High impedance tDW tDH *11 Din Valid data Rev.1.00, Aug.01.2003, page 11 of 13 R1LP0408C-I Series Low VCC Data Retention Characteristics (Ta = −40 to +85°C) Parameter VCC for data retention Data retention current to +85°C Symbol Min Typ* Max Unit Test conditions* VDR ICCDR* ICCDR* to +40°C −20°C to +25°C Chip deselect to data retention time Operation recovery time ICCDR* ICCDR* ICCDR* ICCDR* tCDR tR 1 4 3 2       0 tRC* 5    1.0 1.0 0.8 0.8    20 10 10 3 10 3   V µA CS# ≥ VCC − 0.2 V, Vin ≥ 0 V VCC = 3.0 V, Vin ≥ 0 V CS# ≥ VCC − 0.2 V 2 1 2 1 2 µA µA ns ns See retention waveform Notes: 1. This characteristic is guaranteed only for L version. 2. This characteristic is guaranteed only for SL version. 3. CS# controls address buffer, WE# buffer, OE# buffer, and Din buffer. In data retention mode, Vin levels (address, WE#, OE#, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25°C and specified loading, and not guaranteed. 5. tRC = read cycle time. Low VCC Data Retention Timing Waveform (CS# Controlled) tCDR VCC 4.5 V Data retention mode tR 2.4 V VDR CS# 0V CS# ≥ VCC – 0.2 V Rev.1.00, Aug.01.2003, page 12 of 13 R1LP0408C-I Series Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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