625LP5E

HMC625LP5 / 625LP5E v09.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 6 GHz Typical Applications The HMC625LP5(E) is ideal for: • Cellular/3G Infrastructure • WiBro / WiMAX / 4G • Microwave Radio & VSAT • Test Equipment and Sensors • IF & RF Applications Features -13.5 to +18 Gain Control in 0.5 dB Steps Power-up State Selection High Output IP3: +33 dBm TTL/CMOS Compatible Serial, Parallel, or latched Parallel Control ±0.25 dB Typical Gain Step Error Single +5V Supply 32 Lead 5x5mm SMT Package: 25mm2 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT Functional Diagram General Description The HMC625LP5(E) is a digitally controlled variable gain amplifier which operates from DC to 6 GHz, and can be programmed to provide anywhere from 13.5 dB attenuation, to 18 dB of gain, in 0.5 dB steps. The HMC625LP5(E) delivers noise figure of 6 dB in its maximum gain state, with output IP3 of up to +33 dBm in any state. The dual mode control interface is CMOS/ TTL compatible, and accepts either a three wire serial input or a 6 bit parallel word. The HMC625LP5(E) also features a user selectable power up state and a serial output port for cascading other Hittite serial controlled components. The HMC625LP5(E) is housed in a RoHS compliant 5x5 mm QFN leadless package, and requires no external matching components. Electrical Specifi cations, TA = +25° C, 50 Ohm System, Vdd= +5V, Vs= +5V Parameter Gain (Maximum Gain State) Gain Control Range Input Return Loss Output Return Loss Gain Accuracy: (Referenced to Maximum Gain State) All Gain States Output Power for 1dB Compression Output Third Order Intercept Point (Two-Tone Input Power= 0 dBm Each Tone) Noise Figure Supply Current (Idd) DC - 6.0 GHz DC - 6.0 GHz DC - 0.8 GHz 0.8 - 6.0 GHz DC - 3.0 GHz 3.0 - 6.0 GHz DC - 6.0 GHz DC - 6.0 GHz DC - 6.0 GHz 60 Frequency DC - 3.0 GHz 3.0 - 6.0 GHz Min. 13 5 Typ. 18 13 31.5 15 12 ± (0.10 + 5% of Gain Setting) Max. ± (0.30 + 3% of Gain Setting) Max. 16 13 19 16 33 6 88 100 Max. Units dB dB dB dB dB dB dB dBm dBm dB mA 12 - 1 For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC625LP5 / 625LP5E v09.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 6 GHz Normalized Attenuation [2] Maximum Gain vs. Frequency 25 20 15 10 GAIN (dB) 5 0 -5 -10 -15 -20 -25 0 1 2 3 4 5 6 FREQUENCY (GHz) +25 C +85 C -40 C (Only Major States are Shown) 0 NORMALIZED ATTENUATION (dB) [1] -5 -10 -15 -20 -25 -30 -35 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 FREQUENCY (GHz) [2] 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 12 - 2 Input Return Loss [1] (Only Major States are Shown) 0 -5 RETURN LOSS (dB) Output Return Loss [1] (Only Major States are Shown) 0 -5 RETURN LOSS (dB) -10 -15 -20 -25 -30 -35 -40 -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 FREQUENCY (GHz) 0 1 2 3 4 5 6 FREQUENCY (GHz) Input Return Loss [2] (Only Major States are Shown) 0 -5 RETURN LOSS (dB) Output Return Loss [2] (Only Major States are Shown) 0 -5 RETURN LOSS (dB) -10 -15 -20 -25 -30 -35 -40 -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 FREQUENCY (GHz) 0 1 2 3 4 5 6 FREQUENCY (GHz) [1] Tested with broadband bias tee on RF ports and C1 = 10,000pF [2] C1, C6 and C8 = 100pF, L1 = 24nH For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC625LP5 / 625LP5E v09.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 6 GHz Bit Error vs. Frequency [2] (Only Major States are Shown) 2 1.5 1 BIT ERROR (dB) 0.5 0 -0.5 -1 Bit Error vs. Attenuation State [2] 1 0.8 0.6 BIT ERROR (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 100MHz, 3GHz, 4GHz 500MHz, 1GHz, 2GHz -1.5 -2 0 1 2 3 4 5 6 -0.8 -1 0 4 8 12 16 20 24 28 32 FREQUENCY (GHz) 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 80 60 RELATIVE PHASE (deg) ATTENUATION STATE (dB) Normal Relative Phase vs. Frequency [2] (Only Major States are Shown) Step Error vs. Frequency [2] (Only Major States are Shown) 1 0.8 0.6 STEP ERROR (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 31.5 dB 16 dB 40 8 dB 20 0 -20 -40 0 1 2 3 4 5 6 FREQUENCY (GHz) 0.5 - 4 dB -1 0 1 2 3 4 5 6 FREQUENCY (GHz) [1] Tested with broadband bias tee on RF ports and C1 = 10,000pF [2] C1, C6 and C8 = 100pF, L1 = 24nF 12 - 3 For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC625LP5 / 625LP5E v09.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 6 GHz Serial Control Interface The HMC625LP5(E) contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded asynchronously with parallel digital inputs (D0-D5). When LE is high, 6-bit parallel data is transferred to the attenuator. For all modes of operations, the DVGA state will stay constant while LE is kept low. 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 12 - 4 Parameter Min. serial period, tSCK Control set-up time, tCS Control hold-time, tCH LE setup-time, tLN Min. LE pulse width, tLEW Min LE pulse spacing, tLES Serial clock hold-time from LE, tCKN Hold Time tPH Latch Enable Minimum width, tLEN Setup Time, tPS Typ. 100 ns 20 ns 20 ns 10 ns 10 ns 630 ns 10 ns 0 ns 10 ns 2 ns Timing Diagram (Latched Parallel Mode) Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC625LP5 / 625LP5E v09.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, DC - 6 GHz Power-Up States If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The DVGA latches in the desired power-up state approximately 200 ms after power-up. PUP Truth Table LE 0 0 0 0 1 PUP1 0 1 0 1 X PUP2 0 0 1 1 X Gain Relative to Maximum Gain -31.5 -24 -16 Insertion Loss 0 to -31.5 dB Power-On Sequence 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND Note: The logic state of D0 - D5 determines the power-up state per truth table shown below when LE is high at power-up. Absolute Maximum Ratings RF Input Power [1] Digital Inputs (Reset, Shift Clock, Latch Enable & Serial Input) Bias Voltage (Vdd) Collector Bias Voltage (Vcc) Channel Temperature Continuous Pdiss (T = 85 °C) (derate 15.1 mW/°C above 85 °C) [1] Thermal Resistance Storage Temperature Operating Temperature [1] At max gain settling 11.5 dBm (T = 85 °C) -0.5 to Vdd +0.5V 5.6V 5.5V 150 °C 0.98 W 66.3 °C/W -65 to +150 °C -40 to +85 °C Truth Table Control Voltage Input D5 High High High High High High Low Low D4 High High High High High Low High Low D3 High High High High Low High High Low D2 High High High Low High High High Low D1 High High Low High High High High Low D0 High Low High High High High High Low Gain Relative to Maximum Gain 0 dB -0.5 dB -1 dB -2 dB -4 dB -8 dB -16 dB -31.5 dB Any combination of the above states will provide a reduction in gain approximately equal to the sum of the bits selected. Bias Voltage Vdd (V) 5V Vs (V) 5V Idd (Typ.) (mA) 2 Is (Typ.) (mA) 86 Control Voltage Table State Low High Vdd = +3V 0 to 0.5V @