627LP5E

HMC627LP5 / 627LP5E v10.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz Features -11.5 to 20 dB Gain Control in 0.5 dB Steps Power-up State Selection High Output IP3: +36 dBm TTL/CMOS Compatible Serial, Parallel, or latched Parallel Control ±0.25 dB Typical Gain Step Error Single +5V Supply 32 Lead 5x5mm SMT Package: 25mm2 Typical Applications The HMC627LP5(E) is ideal for: • Cellular/3G Infrastructure • WiBro / WiMAX / 4G • Microwave Radio & VSAT • Test Equipment and Sensors • IF & RF Applications Functional Diagram General Description The HMC627LP5(E) is a digitally controlled variable gain amplifier which operates from 50 MHz to 1 GHz, and can be programmed to provide anywhere from 11.5 dB attenuation, to 20 dB of gain, in 0.5 dB steps. The HMC627LP5(E) delivers noise figure of 4.3 dB in its maximum gain state, with output IP3 of up to +36 dBm in any state. The dual mode gain control interface accepts either three wire serial input or 6 bit parallel word. The HMC627LP5(E) also features a user selectable power up state and a serial output for cascading other Hittite serially controlled components. The HMC627LP5(E) is housed in a RoHS compliant 5x5 mm QFN leadless package, and requires no external matching components. 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT Electrical Specifications, TA = +25° C, 50 Ohm System Vdd = +5V, Vs= +5V Parameter Gain (Maximum Gain State) Gain Control Range Input Return Loss Output Return Loss Gain Accuracy: (Referenced to Maximum Gain State) All Gain States Output Power for 1 dB Compression Output Third Order Intercept Point (Two-Tone Input Power= 0 dBm Each Tone) Noise Figure Switching Characteristics tRISE, tFall (10 / 90% RF) 20 Min. Typ. 50 - 350 18 20 31.5 18 12 15 Max. Min. Typ. 350 - 1000 17.5 31.5 17 12 dB Max. Units MHz dB dB 50 MHz -100MHz, 250 MHz - 350 MHz ± (0.2 + 3% of Gain Setting) Max 100 MHZ - 250 MHz ± (0.1 + 2% of Gain Setting) Max 18 33 20 36 4.3 170 70 90 110 ± (0.3 + 3% of Gain Setting) Max dB dBm dBm dB ns 16 33 20 36 4.3 170 70 90 110 tON, tOFF (Latch Enable to 10 / 90% RF) Supply Current (Idd) mA 12 - 1 For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC627LP5 / 627LP5E v10.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz Maximum Gain vs. Frequency [1] 25 Normalized Attenuation vs. Frequency (Only Major States are Shown) 0 NORMALIZED ATTENUATION (dB) [1] 20 +25 C -40 C +85 C -5 -10 -15 -20 -25 -30 -35 31.5 dB 16 dB 8 dB GAIN (dB) 15 10 [2] 5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 FREQUENCY (GHz) 0 0.5 1 1.5 2 2.5 3 3.5 4 FREQUENCY (GHz) Input Return Loss [1] 0 -5 RETURN LOSS (dB) I.L, .5, 2, 4dB 0 -5 RETURN LOSS (dB) -10 -15 -20 I.L. 31.5 dB -10 -15 -20 -25 -30 -35 -40 0 0.5 1dB 8dB 31.5dB 16dB -25 -30 -35 -40 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 FREQUENCY (GHz) FREQUENCY (GHz) Input Return Loss [2] 0 -5 I.L, 0.5 dB (Only Major States are Shown) Output Return Loss [2] 0 -5 RETURN LOSS (dB) -10 -15 -20 -25 31.5 dB (Only Major States are Shown) 1, 16 dB RETURN LOSS (dB) -10 -15 -20 -25 -30 -35 -40 0 0.5 1 1.5 2 1 dB 16 dB 8, 31.5 dB 2, 4 dB 0.5, 2, 4, 8 dB -30 -35 -40 I.L 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 FREQUENCY (GHz) FREQUENCY (GHz) [1] Tested with broadband bias tee on RF ports and C1 = 10,000pF [2] C1, C6 and C8 = 100pF, L1 = 270nF For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 12 - 2 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT (Only Major States are Shown) Output Return Loss [1] 12 (Only Major States are Shown) HMC627LP5 / 627LP5E v10.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz Bit Error vs. Frequency [2] (Only Major States are Shown) 2 1.5 1 BIT ERROR (dB) 0.5 0 -0.5 -1 -1.5 -2 0 0.5 1 1.5 2 2.5 3 3.5 4 31.5 dB 31.5 dB Bit Error vs. Attenuation State [2] 1 0.8 0.6 BIT ERROR (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 4 8 12 16 20 24 28 32 2.4 GHz 800 MHz FREQUENCY'S: 400, 800, 1200, 1600, 2000, 2400 MHz 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT FREQUENCY (GHz) ATTENUATION STATE (dB) Normal Relative Phase vs. Frequency [2] (Only Major States are Shown) 80 60 16 dB 31.5 dB Step Error vs. Frequency [2] (Only Major States are Shown) 1 0.8 2, 4, 8 dB 2 dB RELATIVE PHASE (deg) 0.6 STEP ERROR (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 40 8 dB 20 0 -20 -40 0 0.5 1 1.5 2 2.5 3 3.5 4 FREQUENCY (GHz) 0.5 - 4 dB 0.5, 1, 31.5 dB 16 dB -1 0 0.5 1 1.5 2 2.5 3 3.5 4 FREQUENCY (GHz) Maximum Gain vs. Frequency[3] 25 Normalized Attenuation vs. Frequency [3] 0 NORMALIZED ATTENUATION (dB) -5 -10 8 dB 20 GAIN (dB) 15 -15 -20 -25 -30 -35 0.05 16 dB 10 5 31.5 dB 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.1 0.15 0.2 0.25 0.3 0.35 FREQUENCY (GHz) FREQUENCY (GHz) [1] Tested with broadband bias tee on RF ports and C1 = 10,000pF [2] C1, C6 and C8 = 100pF, L1 = 270nF [3] C1, C6, C8 = 3300pF; C3, C4 & C5 = 330pF; L1 = 560nH 12 - 3 For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC627LP5 / 627LP5E v10.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz Input Return Loss [3] 0 -5 RETURN LOSS (dB) IL, 0.5, 2, 4 dB Output Return Loss [3] 0 -5 RETURN LOSS (dB) -10 -15 -20 I. L 31.5 dB -10 -15 -20 -25 -25 -30 -35 1 dB -30 -35 8, 16, 31.5 dB -40 0.05 0.1 0.15 0.2 0.25 0.3 0.35 -40 0.05 0.1 0.15 0.2 0.25 0.3 0.35 FREQUENCY (GHz) FREQUENCY (GHz) 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 12 - 4 Bit Error vs. Frequency [3] 2 1.5 8, 16 dB 31.5 dB Bit Error vs. Attenuation State [3] 2 1.5 1 BIT ERROR (dB) 0.5 0 -0.5 -1 -1.5 -2 100, 150, 200, 250, 300, 350 MHz 50 MHz 1 BIT ERROR (dB) 0.5 0 -0.5 0.5, 1, 2, 4 dB -1 -1.5 -2 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0 4 8 12 16 20 24 28 32 FREQUENCY (GHz) ATTENUATION STATE (dB) Normal Relative Phase vs. Frequency [3] 80 60 Step Error vs. Frequency [3] 1 0.8 RELATIVE PHASE (deg) 0.6 STEP ERROR (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 0.2 0.25 0.3 0.35 -1 0.05 0.1 0.15 0.2 8 dB 40 20 0 -20 8 dB 31.5 dB 16 dB 0.5, 31.5 dB -40 0.05 0.1 0.15 0.25 0.3 0.35 FREQUENCY (GHz) FREQUENCY (GHz) [3] C1, C6, C8 = 3300pF; C3, C4 & C5 = 330pF; L1 = 560nH For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC627LP5 / 627LP5E v10.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz Serial Control Interface The HMC627LP5(E) contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). It is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, 6 -bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded asynchronously with parallel digital inputs (D0-D5). When Le is high, 6-bit parallel data is transferred to the attenuator. For all modes of operations, the DVGA state will stay constant while LE is kept low. 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT Parameter Min. serial period, tSCK Control set-up time, tCS Control hold-time, tCH LE setup-time, tLN Min. LE pulse width, tLEW Min LE pulse spacing, tLES Serial clock hold-time from LE, tCKN Hold Time, tPH. Latch Enable Minimum Width, tLEN Setup Time, tPS Typ. 100 ns 20 ns 20 ns 10 ns 10 ns 630 ns 10 ns 0 ns 10 ns 2 ns Timing Diagram (Latched Parallel Mode) Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the Control Voltage Inputs directly. The LE (Latch Enable) must be at a logic high to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the Control Voltage Inputs and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 12 - 5 HMC627LP5 / 627LP5E v10.0410 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 50 MHz - 1 GHz Power-Up States If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The DVGA latches in the desired power-up state approximately 200 ms after power-up. PUP Truth Table LE 0 0 0 0 1 PUP1 0 1 0 1 X PUP2 0 0 1 1 X Gain Relative to Maximum Gain -31.5 -24 -16 Insertion Loss 0 to -31.5 dB Power-On Sequence The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND Note: The logic state of D0 - D5 determines the power-up state per truth table shown below when LE is high at power-up. 12 Control Voltage Input D5 High High High High High High Low Low D4 High High High High High Low High Low D3 High High High High Low High High Low D2 High High High Low High High High Low D1 High High Low High High High High Low D0 High Low High High High High High Low Gain Relative to Maximum Gain 0 dB -0.5 dB -1 dB -2 dB -4 dB -8 dB -16 dB -31.5 dB RF Input Power [1] Digital Inputs (Reset, Shift Clock, Latch Enable & Serial Input) Bias Voltage (Vdd) Collector Bias Voltage (Vcc) Channel Temperature Continuous Pdiss (T = 85 °C) (derate 9 mW/°C above 85 °C) [1] Thermal Resistance Storage Temperature Operating Temperature [1] At max gain settling 11.5 dBm (T = +85 °C) -0.5V to Vdd +0.5V 5.6V 5.5V 150 °C 0.593 W 110 °C/W -65 to +150 °C -40 to +85 °C Any combination of the above states will provide a reduction in gain approximately equal to the sum of the bits selected. Bias Voltage Vdd (V) +5 Vs (V) +5 Idd (Typ.) (mA) 2 Is (mA) 88 Control Voltage Table State Low High Vdd = +3V 0 to 0.5V @