HMC624LP4_10

HMC624LP4 / 624LP4E v09.0210 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL ATTENUATOR, DC - 6 GHz Features 0.5 dB LSB Steps to 31.5 dB Power-Up State Selection High Input IP3: +55 dBm Low Insertion Loss: 2.2 dB @ 3.5 GHz TTL/CMOS Compatible, Serial, Parallel or Latched Parallel Control ±0.25 dB Typical Step Error Single +3V or +5V Supply 24 Lead 4x4mm SMT Package: 16mm2 8 ATTENUATORS - DIGITAL - SMT Typical Applications The HMC624LP4(E) is ideal for: • Cellular/3G Infrastructure • WiBro / WiMAX / 4G • Microwave Radio & VSAT • Test Equipment and Sensors • IF & RF Applications Functional Diagram General Description The HMC624LP4(E) is a broadband 6-bit GaAs IC Digital Attenuator in a low cost leadless SMT package. This versatile digital attenuator incorporates off-chip AC ground capacitors for near DC operation, making it suitable for a wide variety of RF and IF applications. The dual mode control interface is CMOS/TTL compatible, and accepts either a three wire serial input or a 6 bit parallel word. The HMC624LP4(E) also features a user selectable power up state and a serial output port for cascading other Hittite serial controlled components. The HMC624LP4(E) is housed in a RoHS compliant 4x4 mm QFN leadless package, and requires no external matching components. Electrical Specifications, Parameter Insertion Loss Attenuation Range TA = +25° C, 50 Ohm System, with Vdd = +5V & Vctl = 0/+5V (Unless Otherwise Noted) Frequency (GHz) DC - 3 GHz 3.0 - 6.0 GHz Min. Typ. 1.8 2.8 31.5 DC - 6 GHz DC - 0.8 GHz 0.8 - 6.0 GHz DC - 6 GHz DC - 6 GHz 15 ± (0.10 + 5% of Atten. Setting) Max. ± (0.30 + 3% of Atten. Setting) Max. 30 55 Max. 2.4 3.8 Units dB dB dB dB dB dB dBm dBm Return Loss (ATTIN, ATTOUT, All Atten. States) Attenuation Accuracy: (Referenced to Insertion Loss) All Attenuation States Input Power for 0.1 dB Compression Input Third Order Intercept Point (Two-Tone Input Power= 10 dBm Each Tone) 8-1 F or price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC624LP4 / 624LP4E v09.0210 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL ATTENUATOR, DC - 6 GHz Insertion Loss vs. Temperature 0 NORMALIZED ATTENUATION (dB) Normalized Attenuation [1] [1] (Only Major States are Shown) 0 -5 -10 16 dB 8 dB 8 ATTENUATORS - DIGITAL - SMT 8-2 INSERTION LOSS (dB) -1 -2 -15 -20 -25 31.5 dB -3 +25 C +85 C -40 C -4 -30 -35 -5 0 1 2 3 4 5 6 FREQUENCY (GHz) 0 1 2 3 4 5 6 FREQUENCY (GHz) Input Return Loss [1] 0 -5 RETURN LOSS (dB) (Only Major States are Shown) Output Return Loss [1] 0 -5 RETURN LOSS (dB) -10 -15 -20 -25 -30 -35 -40 8 dB 31.5 dB 2 dB (Only Major States are Shown) -10 -15 -20 -25 -30 -35 -40 0 1 2 3 4 5 6 FREQUENCY (GHz) 31.5 dB 16 dB IL 1 dB 16 dB 0 1 2 3 4 5 6 FREQUENCY (GHz) Bit Error vs. Attenuation State 1 0.8 0.6 BIT ERROR (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 4 8 12 16 20 2GHz, 3GHz 4GHz 500MHz Bit Error vs. Frequency [2] [2] (Only Major States are Shown) 2 1.5 1 BIT ERROR (dB) 0.5 0 -0.5 -1 -1.5 -2 0 1 2 3 31.5 dB 100MHz, 1GHz 24 28 32 4 5 6 ATTENUATION STATE (dB) FREQUENCY (GHz) [1] Data taken with bias tees on input and output RF ports. [2] C1, C6 = 330pF F or price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC624LP4 / 624LP4E v09.0210 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL ATTENUATOR, DC - 6 GHz 8 ATTENUATORS - DIGITAL - SMT Worst Case Step Error Between Successive Attenuation States [2] 1 0.8 0.6 STEP ERROR (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1 2 3 4 5 6 FREQUENCY (GHz) 4 dB 16 dB 8 dB IP3 vs. Temperature [2] 80 70 IP3 (dBm) 60 50 40 30 0 1 2 3 4 5 6 FREQUENCY (GHz) Serial Control Interface The HMC624LP4E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). The serial control interface is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches are used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and the input register is loaded with parallel digital inputs (D0-D5). When LE is high, 6-bit parallel data changes the state of the part per truth table. For all modes of operations, the state will stay constant while LE is kept low. 8-3 F or price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC624LP4 / 624LP4E v09.0210 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL ATTENUATOR, DC - 6 GHz Timing Diagram (Latched Parallel Mode) Parameter Min. serial period, tSCK Control set-up time, tCS Control hold-time, tCH LE setup-time, tLN Min. LE pulse width, tLEW Min LE pulse spacing, tLES Serial clock hold-time from LE, tCKN Hold Time, tPH. Latch Enable Minimum Width, tLEN Setup Time, tPS Typ. 100 ns 20 ns 20 ns 10 ns 10 ns 630 ns 10 ns 0 ns 10 ns 2 ns 8 ATTENUATORS - DIGITAL - SMT 8-4 Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch Enable) must be at a logic high at all times to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. Power-Up States If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The attenuator latches in the desired power-up state approximately 200 ms after power-up. PUP Truth Table LE 0 0 0 0 1 PUP1 0 1 0 1 X PUP2 0 0 1 1 X Relative Attenuation -31.5 -24 -16 Insertion Loss 0 to -31.5 dB Power-On Sequence The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND Note: The logic state of D0 - D5 determines the power-up state per truth table shown below when LE is high at power-up. Truth Table Control Voltage Input D5 High D4 High High High High High Low High Low D3 High High High High Low High High Low D2 High High High Low High High High Low D1 High High Low High High High High Low D0 High Low High High High High High Low Reference Insertion Loss 0 dB -0.5 dB -1 dB -2 dB -4 dB -8 dB -16 dB -31.5 dB Bias Voltage Vdd (V) 3 5 Idd (Typ.) (mA) 1.8 2.0 High High High High Control Voltage Table State Low High Vdd = +3V 0 to 0.5V @