HMC625HFLP5E

HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz Typical Applications the HmC625Hflp5e is ideal for: Features -13.5 to +18 Gain Control in 0.5 db steps power-up state selection High Output ip3: +33 dbm ttl /CmOs Compatible serial, parallel, or latched parallel Control ±0.25 db typical Gain step error single +5V supply 32 lead 5 x 5 mm smt package: 25 mm2 Variable Gain amplifiers - DiGital - smt • Cellular/3G Infrastructure • WiBro / WiMAX / 4G • Microwave Radio & VSAT • Test Equipment and Sensors • IF & RF Applications Functional Diagram General Description the HmC625Hflp5e is a digitally controlled variable gain amplifier which operates from 0.5 - 6 GHz, and can be programmed to provide anywhere from 13.5 db attenuation, to 18 db of gain, in 0.5 db steps. the HmC625Hflp5e delivers noise figure of 6 db in its maximum gain state, with output ip3 of up to +33 dbm in any state. the dual mode control interface is CmOs/ ttl compatible, and accepts either a three wire serial input or a 6 bit parallel word. the HmC625Hflp5e also features a user selectable power up state and a serial output port for cascading other Hittite serial controlled components. the HmC625Hflp5e is housed in a roHs compliant 5 x 5 mm Qfn leadless package, and requires no external matching components. Electrical Specifications, TA = +25 °C, 50 Ohm System Vdd = +5V, Vs = +5V parameter Frequency Range Gain (ma ximum Gain state) Gain Control range input return loss Output return loss Gain accuracy: (referenced to ma ximum Gain state) all Gain states Output power for 1 db Compression Output third Order intercept point ( two-tone Output power= 12 dbm each tone) noise figure (ma x Gain state) switching Characteristics trise, tfall (10 / 90% rf) 60 tOn, tOff (latch enable to 10 / 90% rf) supply Current (amplifier) supply Current (Controller) idd 13 min. typ. 500 - 2700 18 31.5 15 12 ± (0.3 + 3% of relative gain setting) ma x 16 19 33 6 30 60 86 0.12 100 0.25 60 11 ma x. min. typ. 2700 - 4000 14 31.5 12 12 ± (0.3 + 3% of relative gain setting) ma x 14 17 29 7 30 60 86 0.12 100 0.25 60 5 ma x. min. typ. 4000 - 6000 10 31.5 10 14 ± (0.4 + 5% of relative gain setting) ma x 11 14 27 8 30 60 86 0.12 100 0.25 ma x. Units mHz db db db db db dbm dbm db ns ns ma ma 0-1 F or price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz Maximum Gain vs. Frequency 25 NORMAILIZED ATTENUATION (dB) Normalized Attenuation 0 (Only Major States are Shown) 20 -10 8dB 15 -20 31.5dB -30 10 +25 C +85 C -40 C 16dB 5 0 0.4 -40 1.4 2.4 3.4 4.4 5.4 6.4 FREQUENCY (GHz) 0.4 1.4 2.4 3.4 4.4 5.4 6.4 FREQUENCY (GHz) Input Return Loss 0 (Only Major States are Shown) Output Return Loss 0 (Only Major States are Shown) RETURN LOSS (dB) -20 RETURN LOSS (dB) -10 0dB -10 -20 -30 -30 -40 0.4 1.4 2.4 3.4 4.4 5.4 6.4 -40 0.4 1.4 2.4 3.4 4.4 5.4 6.4 FREQUENCY (GHz) FREQUENCY (GHz) Bit Error vs. Frequency 2 (Only Major States are Shown) Bit Error vs. Attenuation State 1.5 1 1 BIT ERROR (dB) 31.5dB 16dB BIT ERROR (dB) 0.5 0 -0.5 0.5 GHz 0.7 GHz 5.0 GHz 0 2.0 GHz 4.0 GHz -1 -1 -2 -1.5 0.4 1.4 2.4 3.4 4.4 5.4 6.4 0 4 8 12 16 20 24 28 32 FREQUENCY (GHz) ATTENUATION STATE (dB) F or price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 0-2 Variable Gain amplifiers - DiGital - smt GAIN (dB) HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz Normal Relative Phase vs. Frequency (Only Major States are Shown) 60 Step Attenuation vs. Attenuation State, 0.5 - 3.5 GHz 1.5 0.5 GHz 0.7 GHz 2.0 GHz 2.7 GHz 3.5 GHz Variable Gain amplifiers - DiGital - smt 50 40 30 20 10 0 -10 -20 0.4 1.4 2.4 3.4 4.4 5.4 6.4 FREQUENCY (GHz) 31.5dB 16dB STEP ATTENUATION (dB) RELATIVE PHASE (DEG) 1 8dB 0.5 0 -0.5 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) Step Attenuation vs. Attenuation State, 4.0 - 6.0 GHz 1.5 Output P1dB vs. Temperature 25 STEP ATTENUATION (dB) 1 P1dB (dBm) 20 0.5 15 +25 C +85 C -40 C 0 4.0 GHz 5.0 GHz 6.0 GHz 10 -0.5 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) 5 0.4 1.4 2.4 3.4 4.4 5.4 6.4 FREQUENCY (GHz) Output IP3 vs. Temperature 40 35 30 IP3 (dBm) 25 20 15 10 0.4 Noise Figure 12 10 NOISE FIGURE (dB) 8 6 4 2 0 0.4 +25 C +85 C -40 C +25 C +85 C -40 C 1.4 2.4 3.4 4.4 5.4 6.4 1.4 2.4 3.4 4.4 5.4 6.4 FREQUENCY (GHz) FREQUENCY (GHz) 0-3 F or price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz Serial Control Interface When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and serial input register is loaded asynchronously with parallel digital inputs (D0 - D5). When LE is high, 6-bit parallel data is transferred to the attenuator. for all modes of operations, the DVGa state will stay constant while le is kept low. parameter min. serial period, tsCK Control set-up time, tCs Control hold-time, tCH le setup-time, tln min. le pulse width, tLEW min le pulse spacing, tles serial clock hold-time from le, tCKn Hold time tpH latch enable minimum width, tlen setup time, tps typ. 100 ns 20 ns 20 ns 10 ns 10 ns 630 ns 10 ns 0 ns 10 ns 2 ns Timing Diagram (Latched Parallel Mode) Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: the parallel mode is enabled when p/s is set to low. Direct Parallel Mode - the attenuation state is changed by the Control Voltage inputs directly. the le (latch enable) must be at a logic high to control the attenuator in this manner. Latched Parallel Mode - the attenuation state is selected using the Control Voltage inputs and set while the le is in the low state. the attenuator will not change state while le is low. Once all Control Voltage inputs are at the desired states the le is pulsed. see timing diagram above for reference. F or price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 0-4 Variable Gain amplifiers - DiGital - smt the HmC625Hflp5e contains a 3-wire spi compatible digital interface (serin, ClK, le). it is activated when p/s is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches were used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. HMC625HFLP5E v00.0311 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 6 GHz Power-Up States PUP Truth Table le 0 0 0 0 1 pUp1 0 1 0 1 X pU p 2 0 0 1 1 X Gain relative to ma ximum Gain -31.5 -24 -16 insertion loss 0 to -31.5 db Variable Gain amplifiers - DiGital - smt If LE is set to logic LOW at power-up, the logic state of pUp1 and pUp2 determines the power-up state of the part per pUp truth table. if the le is set to logic HiGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. the DVGa latches in the desired power-up state approximately 200 ms after power-up. Power-On Sequence The ideal power-up sequence is: GND, Vdd, digital inputs, rf inputs. the relative order of the digital inputs are not important as long as they are powered after Vdd / GnD note: the logic state of D0 - D5 determines the powerup state per truth table shown below when le is high at power-up. Absolute Maximum Ratings rf input power [1] Digital inputs (le, serin, ClK, p/s, DO-D5, pUp1, pUp2) Controller bias Voltage (Vdd) amplifier bias Voltage (Vcc) Channel temperature Continuous pdiss (t = 85 °C) (derate 15.1 mW/°C above 85 °C) [1] thermal resistance storage temperature Operating temperature esD sensitivity (Hbm) [1] at max gain settling 11.5 dbm ( t = 85 °C) -0.5 to Vdd +0.5V 5.6V 5.5V 150 °C 0.98 W 66.3 °C/W -65 to +150 °C -40 to +85 °C Class 1a Truth Table Control Voltage input D5 High High High High High High low low D4 High High High High High low High low D3 High High High High low High High low D2 High High High low High High High low D1 High High low High High High High low D0 High low High High High High High low Gain relative to ma ximum Gain 0 db -0.5 db -1 db -2 db -4 dB -8 db -16 db -31.5 db any combination of the above states will provide a reduction in gain approximately equal to the sum of the bits selected. Bias Voltage Vdd (V) 5V Vs (V) 5V idd ( typ.) (ma) 0.12 is ( typ.) (ma) 86 Control Voltage Table state low High Vdd = +3V 0 to 0.5V @