HMC702LP6CE_11

HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt Features • Fractional or integer Modes • 14 GHz, 16-Bit rF n-counter • 24-Bit Step Size resolution, 6 Hz typ • Ultra Low Phase noise 12 GHz, 50 MHz ref. -98 / -103 dBc/Hz @ 20 kHz (Frac / integer) • reference Path input: 200 MHz • 14-Bit reference Path Divider • Low Fractional Spurious • reference spurs: -90 dBc typ • auto and triggered Sweeper Functions • cycle Slip Prevention (cSP) for fast settling • auxiliary clock Source • 40 Lead 6x6mm SMt Package: 36mm² Typical Applications • Base Stations for Mobile radio (GSM, PcS, DcS, cDMa, WcDMa) • Wireless Lans, WiMax • communications test Equipment • catV Equipment • FMcW Sensors • automotive radar • Phased-array Systems Functional Diagram 0-1 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL General Description the HMc702LP6cE is a SiGe BicMoS fractional-n PLL. the fractional-n PLL includes a fixed divide by 2 followed by a 8GHz 16-bit rF n-Divider, a 24-bit delta-sigma modulator, a very low noise digital phase frequency detector (PFD), and a precision controlled charge pump. the fractional-n PLL features an advanced delta-sigma modulator design that allows ultra-fine frequency step sizes. the fractional-n PLL features the ability to alter both the phase-frequency detector (PFD) gain and the cycle slipping characteristics of the PFD. this feature can reduce the time to arrive at the new frequency by 50% vs. conventional PFDs. Ultra low in-close phase noise also allows wider loop bandwidths for faster frequency hopping. the fractional-n PLL contains a built-in linear sweeper function, which allows it to perform frequency chirps with a wide variety of sweep times, polarities and dwells, all with an external or automatic sweep trigger. in addition the fractional-n PLL has a number of auxiliary clock generation modes that can be accessed via the GPo. 0 PLL - FractionaL-n - SMt 0-2 VccHF = VccPrS = rVDD = +3.3V VPPcP = Vccoa = VDDPDr = VPPDrV = VDDPD = VDDPDV = +5V DVDD = DVDDio = DVDDQ = +3.3V GnDDrV = GnDcP = GnDPD = GnDPDV = GnDPDr = 0V Electrical Specifications, TA = +25°C Table 1. Electrical Specifications Parameter Prescaler Characteristics Max rF input Frequency (3.3V) Max rF input Frequency (2.7 - 3.3V) Min rF input Frequency rF input Power 16-bit n-Divider range (integer) 16-bit n-Divider range (Fractional) REF Input Characteristics Max ref input Frequency (pin XrEFP) Max ref input Frequency (pin XSin) Min ref input Frequency ref input Voltage range (pin XrEFP) ref input Power range (pin XSin) ref input capacitance 14-Bit r-Divider range 1 XSin minimum 20MHz due to phase noise degradation ac coupled 50 Ω Source 250 250 100 1.5 -6 2.0 0 3.3 12 5 16,383 MHz MHz kHz Vpp dBm pF Fmin Vco path freq, vco path freq > ref path freq, and a PFD strobe which holds the PFD at maximum gain, are routed to GPo3, GPo2, and GPo1 respectively. these lines will be active during frequency pull-in and will indicate instantaneously which signal, reference or vco path is greater in frequency. the PFD strobe gives insight into when the PFD is near maximum gain at 2π. the PFD strobe will be active until the Vco pulls into lock. 0 PLL - FractionaL-n - SMt 0 - 12 Internal Synchronized Frac strobe with clocks (gpo_sel= 4) Setting register gpo_sel=4 in (Reg1Bh table 37) gives visibility into the internally synchronized strobe that is generated when commanding a frequency change by writing to the frac register. the internal strobe initiates the update to the fractional modulator. the internal frac strobe, the ref path divider output and the sine reference input are buffered out to GPo1, GPo2 and GPo3 respectively as shown in Figure 8. in this mode, GPo1 may be used to trigger an external instrument when doing frequency hopping tests for example. Figure 8. gpo_04 Outputs Δ∑ Modulator Phase Accumulator (gpo_sel=6) Setting register gpo_sel=6 (Reg1Bh table 37) assigns the three msb’s of the delta sigma modulator first accumulator to GPo , where GPo3 is the msb. this feature provides insight into the phase of the Vco. Auxiliary Oscillators (gpo_sel=7) Setting register gpo_sel=7 (Reg1Bh table 37) assigns an auxiliary clock, an internal ring oscillator, and the internal sigma delta clock to GPo3, 2, 1 respectively. the control of the auxiliary clock is determined by reg18h table 34 and Reg19h table 35. in general terms, this highly flexible clock source allows the selection of one of the various Vco or crystal related clocks inside the synthesizer or the selection of a flexible unstabilized auxiliary ring oscillator clock. any of the sources may be routed out via gpo_sel=7. additional Reg18h table 34 clock controls allow the aux clock to be delayed by a variable amount (auxclk_modesel Reg18h), or to be divided down by even values from 2 to 14 (auxclk_divsel Reg18h). F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt Δ∑ Modulator Outputs (gpo_sel=10) Setting register gpo_sel=10 (Reg1B table 37) assigns the three lsb’s of the delta sigma modulator output to GPo, where GPo1 is the lsb. this feature allows the possibility of using the HMc702LP6cE as a general purpose digital delta sigma modulator for many possible applications. External VCO the HMc702LP6cE is targeted for ultra low phase noise applications with an external Vco. the synthesizer has been designed to work with Vcos that can be tuned nominally over 0.5 to 4.5 Volts on the varactor tuning port with a +5V charge pump supply voltage. Slightly wider ranges are possible with a +5.5V charge pump supply or with slightly degraded performance. External VCO with Active Inverting OpAmp Loop Filter an external opamp active filter is required to support external Vcos with tuning voltages above 5V. if an inverting opamp is used with a positive slope Vco, phase_sel reg05h = 1 table 16 must be set to invert the PFD phase polarity and obtain correct closed loop operation. Figure 9. Conventional Synthesizer with VCO 0 - 13 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL Temperature Sensor the HMc702LP6cE features a built in temperature sensor which may be used as a general purpose temperature sensor. the temperature sensor is enabled via tsens_spi_enable (Reg1Eh=1 table 40) and when enabled draws 2 ma. the temperature sensor features a built in 3-bit quantizer that allows the temperature to be read in register tsens_ temperature (Reg21h table 43). the temperature sensor data converter is not clocked. Updates to the temperature sensor register are made by strobing register tsens_spi_strobe (reg00h table 11). the 3-bit quantizer operates over a -40°c to +100°c range as follows: tn = floor {(temperature +40) / 17.5 where Tn is the decimal value of register tsens_temperature} TEMPERATURE SENSOR QUANTIZER OUTPUT 7 6 5 4 3 2 1 0 -40 0 PLL - FractionaL-n - SMt 0 - 14 (EQ 7) -20 0 20 40 60 TEMPERATURE (°C) 80 100 Figure 10. Typical Temperature Sensor Quantizer output temperature sensor slope is 17.5 mV/lsb. absolute tolerances on the temperature sensor thresholds may vary by up to ±10°c worst case. nominal temperature is given by: (EQ 8) Charge Pump & Phase Frequency Detector (PFD) the Phase Frequency Detector or PFD has two inputs, one from the reference path divider and one from the Vco path divider. the PFD compares the phase of the Vco path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. the output current varies linearly over a full ±2π radians input phase difference. PFD Functions phase_sel (Reg05h table 16) inverts the phase detector polarity for use with an inverting opamp or negative slope Vco upout_en in Reg05h table 16 allows masking of the PFD up output, which effectively prevents the charge pump from pumping up. dnout_en in Reg05h table 16 allows masking of the PFD down output, which effectively prevents the charge pump from pumping down. Charge Pump Tri-State De-asserting both upout_en and dnout_en effectively tri-states the charge pump while leaving all other functions operating internally. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt PFD Jitter & Lock Detect Background in normal phase locked operation the divided Vco signal arrives at the phase detector in phase with the divided crystal signal, known as the reference signal. Despite the fact that the device is in lock, the phase of the Vco signal and the reference signal vary in time due to the phase noise of the crystal and Vco oscillators, the loop bandwidth used and the presence of fractional modulation or not. the total integrated noise on the Vco path normally dominates the variations in the two arrival times at the phase detector if fractional modulation is turned off. if we wish to detect if the Vco is in lock or not we need to distinguish between normal phase jitter when in lock and phase jitter when not in lock. First, we need to understand what is the jitter of the synthesizer, measured at the phase detector in integer or fractional modes. the standard deviation of the arrival time of the Vco signal, or the jitter, in integer mode may be estimated with a simple approximation if we assume that the locked Vco has a constant phase noise, Ф2 ( ƒ0), at offsets less than the loop 3 dB bandwidth and a 20 dB per decade roll off at greater offsets. the simple locked Vco phase noise approximation is shown on the left of Figure 11. Figure 11. Synthesizer Phase Noise & Jitter With this simplification the single sideband integrated Vco phase noise, Ф2 , in rads2 at the phase detector is given by (EQ 9) where Ф2 SSB(ƒ0) is the single sideband phase noise in rads2/Hz inside the loop bandwidth, B is the 3 dB corner frequency of the closed loop PLL and n is the division ratio of the prescaler the rms phase jitter of the Vco in rads, Ф , results from the power sum of the two sidebands: 2 Ф = √ 2Ф SSB (EQ 10) Since the simple integral of (EQ 9) is just a product of constants, we can easily do the integral in the log domain. For example if the Vco phase noise inside the loop is -100 dBc/Hz at 10 kHz offset and the loop bandwidth is 100 kHz, and the division ratio n=100, then the integrated single sideband phase noise at the phase detector in dB is given by Ф2dB = 10log (Ф2(ƒ0)Bπ ⁄ n2) = -100 + 50 + 5 - 40 = -85 dBrads, or equivalently Ф = 10 -82/20 = 56 urads rms or 3.2 milli-degrees rms. While the phase noise reduces by a factor of 20logn after division to the reference, the jitter is a constant. 0 - 15 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL the rms jitter from the phase noise is then given by Tjnp = Tref Ф / 2π in this example if the reference was 50 MHz, Tref = 20 nsec, and hence Tjpn = 178 femto-sec. a normal 3 sigma peak-to-peak variation in the arrival time therefore would be ±3 √ 2Tjpn = 0.756 ps if the synthesizer was in fractional mode, the fractional modulation of the Vco divider will dominate the jitter. the exact standard deviation of the divided Vco signal will vary based upon the modulator chosen, however a typical modulator will vary by about ±3 Vco periods, ±4 Vco periods, worst case. if, for example, a nominal Vco at 5 GHz is divided by 100 to equal the reference at 50 MHz, then the worst case division ratios will vary by 100±4. Hence the peak variation in the arrival times caused by Δ∑ modulation of the fractional synthesizer at the reference will be (EQ 11) 0 PLL - FractionaL-n - SMt 0 - 16 PFD Jitter and Lock Detect Background (Continued) in this example, tjΔ∑pk = ±200 ps(108-92)/2 = ±1600 psec. if we note that the distribution of the delta sigma modulation is approximately gaussian, we could approximate tjΔ∑pk as a 3 sigma jitter, and hence we could estimate the rms jitter of the Δ∑ modulator as about 1/3 of tjΔ∑pk or about 532 psec in this example. Hence the total rms jitter Tj, expected from the delta sigma modulation plus the phase noise of the Vco would be given by the rms sum , where (EQ 12) in this example the jitter contribution of the phase noise calculated previously would add only 0.764psec more jitter at the reference, hence we see that the jitter at the phase detector is dominated by the fractional modulation. Bottom line, we have to expect about ±1.6 nsec of normal variation in the phase detector arrival times when in fractional mode. in addition, lower Vco frequencies with high reference frequencies will have much larger variations., for example, a 1 GHz Vco operating at near the minimum nominal divider ratio of 72, would, according to (EQ 11), exhibit about ±4 nsec of peak variation at the phase detector, under normal operation. the lock detect circuit must not confuse this modulation as being out of lock. PFD Lock Detect lkd_en (Reg01h table 12) enables the lock detect functions of the HMc702LP6cE. the Lock Detect circuit in the HMc702LP6cE places a one shot window around the reference. the one shot window may be generated by either an analog one shot circuit or a digital one shot based upon an internal ring oscillator timer. clearing lkd_ringosc_mono_select (Reg1Ah table 36) will result in a nominal 10nsec ‘analog’ window of fixed length, as shown in Figure 21. Setting lkd_ringosc_mono_select will result in a variable length ’digital’ widow. the digital one shot window is controlled by lkd_ringosc_cfg (Reg1Ah). the resulting lock detect window period is then generated by the number of ring oscillator periods defined in lkd_monost_duration Reg1Ah (table 36). the lock detect ring oscillator may be observed on the GPo2 port by setting ringosc_testmode (Reg1Ah table 36) and configuring the gpo_sel = 0111 in (Reg1Bh table 37). Lock detect does not function when this test mode is enabled. lkd_wincnt_max (Reg1Ah table 36) defines the number of consecutive counts of the Vco that must land inside the lock detect window to declare lock. if for example we set lkd_wincnt_max = 1000 , then the Vco arrival would F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt have to occur inside the selected lock widow 1000 times in a row to be declared locked. When locked the Lock Detect flag ro_lock_detect (Reg1Fh table 41) will be set. a single occurrence outside of the window will result in clearing the Lock Detect flag, ro_lock_detect. the Lock Detect flag ro_lock_detect (Reg1Fh table 41) is a read only register, readable from the serial port. the Lock Detect flag is also output to the LD_SDO pin according to lkd_to_sdo_always (Reg1Ah) and lkd_to_sdo_ automux_en (Reg1Ah), both in table 36. Setting lkd_to_sdo_always will always display the Lock Detect flag on LD_DSO. clearing lkd_to_sdo_always and setting lkd_to_sdo_automux_en will display the Lock Detect flag on LD_SDO except when a serial port read is requested, in which case the pin reverts temporarily to the Serial Data out pin, and returns to the lock detect function after the read is completed. Figure 12. Normal Lock Detect Window Lock Detect with Phase Offset When operating in fractional mode the linearity of the charge pump and phase detector are more critical than in integer mode. the phase detector linearity is worse when operated with zero phase offset. Hence in fractional mode it is necessary to offset the phase of the reference and the Vco at the phase detector. in such a case, for example with an offset delay, as shown in Figure 13, the mean phase of the Vco will always occur after the reference. the lock detect circuit window can be made more selective with a fixed offset delay by setting win_asym_enable and win_asym_up_select (Reg1Ah table 36). Similarly the offset can be in advance of the reference by clearing win_asym_up_select while leaving win_asym_enable Reg1Ah set both in table 36. Figure 13. Delayed Lock Detect Window For most applications the analog one shot window is sufficient. to determine the required Lock Detect one shot window size: required LD one Shot Window = (cP Phase offset (ns) + 8xtvco) x 1.3. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 17 HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL Cycle Slip Prevention (CSP) When changing frequencies the Vco is not yet locked to the reference and the phase difference at the PFD varies rapidly over a range much greater than ±2π radians. Since the gain of the PFD varies linearly with phase up to ±2π, the gain of conventional PFDs will cycle from high gain, when the phase difference approaches a multiple of 2π, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. this phenomena is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically as shown in the red curve in Figure 14. cycle slipping increases the time to lock to a value far greater than that predicted by normal small signal Laplace analysis. the HMc702LP6cE PFD features cycle Slip Prevention (cSP), an ability to virtually eliminate cycle slipping during acquisition. When enabled, the cSP feature essentially holds the PFD gain at maximum until such time as the frequency difference is near zero. cSP allows significantly faster lock times as shown inFigure 14. the use of the cSP feature is enabled with pfds_rstb (Reg01 table 12). the cSP feature may be optimized for a given set of PLL dynamics by adjusting the PFD sensitivity to cycle slipping. this is achieved by adjusting pfds_sat_deltaN (Reg1C table 38). cSP will cause the Vco n divider to momentarily divide by a higher or lower n value in order to pull the divided Vco phase back towards the reference edge. the maximum recommended Vco n divider deviation is no more than 20% of the target n value programmed into register F. For example, if n=50 for the target frequency, then the cSP Magnitude should be 10 or less so register 1ch Bits [3:0] would be programmed to ah. in situations where the target n value is low, for example 36 the cSP behavior will be compromised because the minimum Vco divide value is 32. 0 PLL - FractionaL-n - SMt 0 - 18 Figure 14. Cycle Slip Prevention (CSP) Charge Pump Gain a simplified diagram of the charge pump is shown in Figure 15. charge pump up and down gains are set by cp_ UPcurrent_sel and cp_DNcurrent_sel respectively (Reg07 table 18). normally the registers are set to the same value. Each of the UP and Dn charge pumps consist of 5-bit charge pumps with lsb of 125 µa. the current gain of the pump, in amps/radian, is equal to the gain setting of this register divided by 2π. For example if both cp_UPcurrent_sel and cp_DNcurrent_sel are set to ’01000’ the output current of each pump will be 1ma and the gain Kp = 1ma/2π radians, or 159 ua/rad. Charge Pump Gain Trim in most applications Gain trim is not used. However it is available for special applications. Each of the UP and Dn pumps may be trimmed separately to more precise values to improve current source matching of the UP and Dn values, or to allow finer control of pump gain. the pump trim controls are 3-bits, binary weighted for UP and Dn, in cp_UPtrim_sel and cp_DNtrim_sel respectively (reg 08h table 19). LSB weight is 14.7 ua, x000 = 0 trim, x001 = 14.7 ua added trim, x111 = 100ua. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt Charge Pump Phase Offset Either of the UP or Dn charge pumps may have a Dc leakage or “offset” added. the leakage forces the phase detector to operate with a phase offset between the reference and the divided Vco inputs. it is recommended to operate with a phase offset when using fractional mode to reduce non-linear effects from the UP and Dn pump mismatch. Phase noise in fractional mode is strongly affected by charge pump offset. Dc leakage or “offset” may be added to the UP or Dn pumps using cp_UPoffset_sel and cp_DNoffset_sel (Reg08 table 19). these are 4 bit registers with 28.7ua LSB. Maximum offset is 430ua. as an example, if the main pump gain was set at 1ma, an offset of 373ua would represent a phase offset of about (392/1000)*360 = 133 degrees. For best spectral performance in Fractional Mode the leakage current should be programmed to: required Leakage current (µa) = (2.5E-9 + 8xtvco) x Fcomparison (Hz) x cP current (µa) Figure 15. Charge Pump Gain, Trim and Phase Offset Control Frequency Programming the HMc702LP6cE can operate in either fractional mode or integer mode. in integer mode of operation the delta sigma modulator is disabled. Frequency programming and mode control is described below. Fractional Frequency the fractional frequency synthesizer, when operating in fractional mode, can lock to frequencies which are fractional multiples of the reference frequency. Fractional mode is the default mode. to run in fractional mode ensure that dsm_integer_mode reg12h table 29 is clear and dsm_rstb is set reg01 table 12. then program the frequency as explained below: the output frequency of the synthesizer is given by, fvco, where Fractional Frequency of VCO (EQ 13) 0 - 19 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL where Nint Nfrac R fxtal as an Example: fxtal R fref Nint Nfrac = 50 MHz =1 = 50 MHz = 92 =1 (EQ 14) is the integer division ratio, an integer number between 36 and 65,533 (dsm_intg (Reg0Fh table 26)) is the fractional part, a number from 1 to 224 (dsm_frac Reg10h table 27) is the reference path division ratio, (rfp_div_ratio Reg03h table 14) is the frequency of the crystal oscillator input (XSin or XrEF Figure 10) 0 PLL - FractionaL-n - SMt 0 - 20 in this example the output frequency of 9,600,000,005.96 Hz is achieved by programming the 16-bit binary value of 92d = 5c = 0000 0000 0101 1100 into dsm_intg. Similarly the 24-bit binary value of the fractional word is written into dsm_frac, 1d = 000 001h = 0000 0000 0000 0000 0000 0001 Example 2: Set the output to 12.600 025 GHz using a 100 MHz reference, r=2. Find the nearest integer value, nint, nint = 126, fint = 12.600 000 GHz this leaves the fractional part to be ffrac =25 kHz (EQ 15) Since Nfrac must be an integer number, the actual fractional frequency will be 24,998.19 Hz, an error of 1.81 Hz. Here we program the 16-bit nint = 126d = 7Eh = 0000 0000 0111 1110 and the 24-bit nfrac = 4194d = 1062h = 0000 0100 0001 0010 in addition to the above frequency programming words, the fractional mode must be enabled using the frac register. other DSM configuration registers should be set to the recommended values. register setup files are available on request. Integer Frequency the synthesizer is capable of operating in integer mode. in integer mode the digital Δ∑ modulator is normally shut off and the division ratio of the Vco divider is set at a fixed value. to run in integer mode set dsm_integer_mode (Reg12h table 29) and clear dsm_rstb (Reg01h table 12). then program the integer portion of the frequency, NINT, as explained by (EQ 13), ignoring the fractional part. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt Frequency Hopping Trigger if the synthesizer is in fractional mode, a write to the fractional frequency register, Reg10h table 27, will initiate the frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 19). if the integer frequency register, Reg0Fh table 26, is written when in fractional mode the information will be buffered and only executed when the fractional frequency register is written. if the synthesizer is in integer mode, a write to the integer frequency register, Reg0Fh table 26, will initiate the frequency hop on the falling edge of the 31st clock edge of the serial port write (see Figure 19). Power On Reset (POR) normally all logic cells in the HMc702LP6cE are reset when the device digital power supply, DVDD, is applied. this is referred to as Power on reset, or just Por. Por normally takes about 500us after the DVDD supply exceeds 1.5V, guaranteed to be reset in 1msec. once the DVDD supply exceeds 1.5V, the Por will not reset the digital again unless the supply drops below 100mV. Soft Reset the SPi registers may also be soft reset by an SPi write to strobe global_swrst_regs (Reg00h table 11). all other digital, including the fractional modulator, may be reset with an SPi write to strobe global_swrst_dig (Reg00h table 11). Hardware Reset the SPi registers may also be hardware reset by holding rStB, pin 19, low. Power Down the HMc702LP6cE may be powered down by writing a zero to Reg01h table 12. in power down state the HMc702LP6cE should draw less than 10ua. it should be noted that Reg01h is the Enable and reset register which controls 16 separate functions in the chip. Depending upon the desired mode of operation of the chip, not all of the functions may be enabled when in operation. Hence power up of the chip requires a selective write to Reg01 bits. an easy way to return the chip to its prior state after a power down is to first read Reg01h and save the state, then write a zero to Reg01h for reset and then simply rewrite the previous value to restore the chip to the desired operating mode. CW Sweeper Mode the HMc702LP6cE features a built in frequency sweeper function. this function supports external or automatic triggered sweeps. the maximum sweep range is limited to 510 x Fxtal/r. For example, with a 10 MHz comparison frequency, the maximum sweep range is 5100 MHz. the start and end frequency points must be within 5100 MHz of one another. For sweep operation the Delta-Sigma Modulator mode should be Feed Forward (register 12h Bits [9:8] = 11) otherwise discontinuities may occur when crossing integer-n boundaries (harmonic multiples of the comparison frequency). Sweeper Modes include: a. 2-Way Sweep Mode: alternating positive and negative frequency ramps. b. 1-Way Sweep Mode c. Single Step ramp Mode applications include test instrumentation, FMcW sensors, automotive radars and others. the parameters of the sweep function are illustrated in Figure 16. 0 - 21 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL CW Sweeper Mode (Continued) the sweep generator is enabled with ramp_enable in (Reg14h table 30). the sweep function cycles through a series of discrete frequency values, which may be a. Stepped by an automatic sequencer, or b. Single stepped by individual triggers in Single Step Mode. triggering of each sweep, or step, may be configured to operate: a. Via a serial port write to Reg14h ramp_trigg (if reg 14h = 0 ) b. automatically generated internally, c. triggered via ttL input on GPo3 reg14h = 1. Sweep parameters are set as follows: initial Frequency, fo = current frequency value of the synthesizer, (EQ 15) Final Frequency, ff = Frequency of the synthesizer at the end of the ramp the frequency step size while ramping is controlled by rampstep, (Reg15h table 31). Frequency Step Size Δƒstep = rampstep • fxtal / 2 23 0 PLL - FractionaL-n - SMt 0 - 22 • R where r is the value of the reference divider (rfp_div_ratio in table 14) clearing or setting ramp_startdir_dn, (Reg14h table 30), sets the initial ramp direction to be increasing or decreasing in frequency respectively. Setting ramp_singledir (Reg14h table 30), restricts the direction of the sweep to the initial sweep direction only. the sweeper timebase Tref is the period of the divided reference, fPFD, at the phase detector Tref the total number of ramp steps taken in a single sweep is given by ramp_steps_number in reg16h table 32. the total time to ramp from fo to ff is given by Tramp = Tref the final ramp frequency, ff, is given by ƒƒ = ƒi + Δƒstep • • ramp_steps_number ramp_steps_number Sweeper action at the end of sweep depends upon the mode of the sweep: a. With both ramp_singledir and ramp_repeat_en disabled, at the end of the ramp time, Tramp, the sweeper will dwell at the final frequency ff, until a new trigger is received. the next trigger will reverse the current sequence, starting from ff, and stepping back to fo. odd triggers will ramp in the same direction as the initial ramp, even triggers will ramp in the opposite direction. b. with ramp_singledir enabled and ramp_repeat_en disabled, at the end of the ramp time, Tramp, the sweeper will dwell at the final frequency ff, until a new trigger is received. the second trigger will hop the synthesizer back to the initial frequency, fo. the third trigger will restart the sweep from fo. Hence all odd numbered triggers will start a new ramp in the same direction as the initial ramp, even numbered triggers will hop the synthesizer from the current frequency to fo , where it will wait for a trigger to start a sweep. Ramp Busy in all types of sweeps ramp_busy will indicate an active sweep and will stay high between the 1st and nth ramp step. ramp_busy may be monitored one of two ways. ramp_busy is readable via read only register Reg1Fh table 41. ramp_busy may also be monitored on GPo2, hardware pin 24, by setting Reg1Bh =8h table 37. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt Autosweep Mode the autosweep mode is similar to Figure 16 except that once started, triggers are not required. once enabled, (ramp_ repeat_en=1 Reg14h table 30) the autosweep mode initiates the first trigger, steps n times, one step per ref clock cycle, and then waits for the programmed dwell period and automatically triggers the ramp in the opposite direction. the sweep process continues alternating sweep directions until disabled. dwell_time (Reg17h table 33) controls the number of Tref periods to wait at the end of the ramp before automatically retriggering a new sweep. 2-Way Sweeps if ramp_repeat_en (Reg14h table 30) is cleared, then the ramps are triggered by a. Writing to ramp_trigg (Reg14h table 30), if bit = 0, or b. by rising edge ttL signal input on GPo3, if ramp_trig_ext_en is set, and GPo3 is enabled. all functions are the same in Figure 16 for autosweep or 2-Way triggered sweeps, the only difference is the trigger source is generated internally for autosweep, and is input via serial port or GPo3 for triggered sweeps. Sweep_busy will go high at the start of every ramp and stay high until the nth step in the ramp. Figure 16. 2-Way Sweep Control via Trigger Triggered 1-Way Sweeps 1-Way sweeps are shown in Figure 17. Unlike 2-Way sweeps, 1-Way sweeps require that the Vco hop back to the start frequency after the dwell period. triggered 1-Way sweeps also require a 3rd trigger to start the new sweep. the 3 rd trigger must be timed appropriately to allow the Vco to settle after the large frequency hop back to the start frequency. Subsequent odd numbered triggers will start the 1-Way sweep and repeat the process. 0 - 23 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt 0 - 24 Figure 17. 1-Way Sweep Control Single Step Ramp Mode a Single Step 1-Way ramp is shown in Figure 18. in this mode, a trigger is required for each step of the ramp. Single step will function in either 1-Way or 2-Way ramps. Similar to autosweep, the ramp_busy flag will go high on the first trigger, and will stay high until the nth trigger. the n+1 trigger will cause the ramp to jump to the start frequency in 1-way ramp mode. the n+2 trigger will restart the 1-way ramp. Figure 18. Single Step Ramp Mode the user should be aware that the synthesized ramp is subject to normal phase locked loop dynamics. if the loop bandwidth in use is much wider than the rate of the steps then the locking will be very fast and the ramp will have a staircase shape. if the update rate is higher than the loop bandwidth, as is normally the case, then the loop will not fully settle before a new frequency step is received. Hence the swept output will have a small lag and will sweep in a near continuous fashion. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt MAIN SERIAL PORT the HMc702LP6cE features a four wire serial port for simple communication with the host controller. register types may be read only, Write only, read/Write or Strobe, as described in the registers descriptions. the synthesizer also features an auxiliary 3-wire serial port, known as the Vco Serial Port. the Vco Serial Port is a write only interface from the synthesizer to an optional switched resonator Vco that supports 3-wire serial port control. typical main serial port operation can be run with ScLK at speeds up to 50 MHz. Serial port registers are described in the section rEGiStEr MaP. Serial Port WRITE Operation aVDD = DVDD = 3V ±10%, aGnD = DGnD = 0V Table 4. Timing Characteristics Parameter t1 t2 t3 t4 t5 t6 t7 Conditions SEn to ScLK setup time SDi to ScLK setup time SDi to cLK hold time ScLK high duration ScLK low duration SEn High duration SEn low duration Min. 8 10 10 8 8 640 20 Typ. Max Units nsec nsec nsec nsec nsec nsec nsec a typical WritE cycle is shown in Figure 19. a. the Master (host) both asserts SEn (Serial Port Enable) and clears SDi to indicate a WritE cycle, followed by a rising edge of ScLK. b. the slave (synthesizer) reads SDi on the 1st rising edge of ScLK after SEn. SDi low initiates the WritE cycle (/Wr) c. Host places the six address bits on the next six falling edges of ScLK, MSB first. d. Slave registers the address bits in the next six rising edges of ScLK (2-7). e. Host places the 24 data bits on the next 24 falling edges of ScK, MSB first . f. Slave registers the data bits on the next 24 rising edges of ScK (8-31). g. SEn is de-asserted on the 32nd falling edge of ScLK. h. the 32nd rising edge of ScLK completes the cycle Figure 19. Serial Port Timing Diagram - WRITE 0 - 25 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL Main Serial Port READ Operation the synthesizer uses the multi-purpose pin, LD_SDO, for both Lock Detect and Serial Data out (SDo) functions. the registers lkd_to_sdo_automux_en (Reg1A) and lkd_to_sdo_always (Reg1A table 36) determine how the Data output pin is muxed with the Lock Detect function. if both of the registers are cleared, then the pin is exclusively SDo. if automux is enabled, the pin switches to SDo when the rD function is sensed on the 1st rising edge of ScLK. if lkd_to_sdo_always is set, then the pin LD_SDO is dedicated for Lock Detect only, and it is not possible to read from the synthesizer. a typical rEaD cycle is shown in Figure 20. a. the Master (host) asserts both SEn (Serial Port Enable) and SDi to indicate a rEaD cycle, followed by a rising edge ScLK b. the slave (synthesizer) reads SDi on the 1st rising edge of ScLK after SEn. SDi high initiates the rEaD cycle (rD) c. Host places the six address bits on the next six falling edges of ScLK, MSB first. d. Slave registers the address bits on the next six rising edges of ScLK (2-7). e. Slave places the 24 data bits on the next 24 rising edges of ScK (8-31), MSB first . f. Host registers the data bits on the next 24 falling edges of ScK (8-31). g. SEn is de-asserted on the 32nd falling edge of ScLK. h. the 32nd falling edge of ScLK completes the cycle 0 PLL - FractionaL-n - SMt 0 - 26 Figure 20. Serial Port Timing Diagram - READ F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL 0 PLL - FractionaL-n - SMt REGISTER MAP Reg 00h Chip ID (Read Only) Register Bit [23:0] Type ro chip iD Name Width 24 Default 581504 chip iD Description Table 11. Reg 00h Strobe (Write Only) Register Bit 0 1 2 3 Type Str Str Str Str Name global_swrst_regs global_swrst_dig mcnt_resynch tsens_spi_strobe Width 1 1 1 1 Default 0 0 0 0 Description Strobe to soft reset the SPi registers Strobe to soft reset the rest of digital reserved Strobe to clock the temp measurement on demand Table 12. Reg 01h Enable & Reset Register Bit 0 1 2 Type r/W r/W r/W Name malg_vcobug_en mag_bias_en rfp_div_en 1 1 1 Default 1 1 0 Bias enable Enables / Holds refdiv in reset Holding ref divider in reset is equivalent to bypassing the divider, see Figure 4 Enables clock gate for xtal muxed (sq or sin) reference to digital Enables divided reference clock to the digital see Figure 4 Enables square wave xtal clock to main digital see Figure 4 Enables sine wave xtal clock to main digital see Figure 4 Enables Square wave ref Buffer, see Figure 4 Enables Sine wave ref Buffer, see Figure 4 1= divided Vco as digital, Δ∑ modulator clock 0= Divided ref path as the Enables the prescaler bias Enable / resetb to digital lockdetect circuit and PFD’s lockdetect output gates charge Pump Enable, disable is tri-stated output 1 - Enables fractional modulator see also dsm_integer_mode Reg12h 1 - enables lock detect circuit cSP PFD FF rstb 1 - Enables the cycle Slip Prevention (cSP) feature of the PFD Description Vco Buffer Enable 3 4 5 6 7 8 9 10 11 12 13 14 15 r/W r/W r/W r/W r/W r/W r/W r/W r/W r/W r/W r/W r/W xrefmux_todig_en rfp_div_todig_en rfp_sqr_todig_en rfp_sin_todig_en rfp_bug_sq_en rfp_bug_sin_en vcop_todig_en vcop_presc_en pfd_lkd_en cp_en dsm_rstb lkd_rstb pfds_rstb 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 1 0 1 0 0 1 0 - 27 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC702LP6CE v07.0411 14 GHz 16-BIT FRACTIONAL-N PLL Table 13. Reg 02h Serial Data Out Force Register Bit 0 Type r/W Name malg_sdo_driver_force_val Default 1 Description Serial Data out Force value this value may be forced onto LD_SDo by setting malg_sdo_driver_force_en Serial Data out En Force enable Places value from malg_sdo_driver_force_val on SDo 0 PLL - FractionaL-n - SMt 0 - 28 1 r/W malg_sdo_driver_force_en 1 Table 14. Reg 03h Reference Path Register Bit Type Name Default Description Divides the crystal input by this number ‘r’ if rfp_div_en=1 and rfp_div_select = 1 rfp_div_ratio = 0 not allowed 2