HMC742HFLP5E

HMC742HFLP5E v00.0211t Designer’s Kit Available 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Features -19 to 12.5 dB Gain Control in 0.5 dB Steps Power-up State Selection High Output IP3: +39 dBm TTL/CMOS Compatible Serial, Parallel, or latched Parallel Control ±0.25 dB Typical Gain Step Error Single +5V Supply 32 Lead 5x5mm SMT Package: 25mm2 Typical Applications The HMC742HFLP5E is ideal for: • Cellular/3G Infrastructure • WiBro / WiMAX / 4G • Microwave Radio & VSAT • Test Equipment and Sensors • IF & RF Applications 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT Functional Diagram General Description The HMC742HFLP5E is a digitally controlled variable gain amplifier which operates from 0.5 GHz to 4 GHz, and can be programmed to provide from -19 dB attenuation, to 12.5 dB of gain, in 0.5 dB steps. The HMC742HFLP5E delivers noise figure of 4 dB in its maximum gain state, with output IP3 of up to +39 dBm in any state. The dual mode gain control interface accepts either a three-wire serial input or a 6 bit parallel word. The HMC742HFLP5E also features a user selectable power up state and a serial output for cascading other serially controlled Hittite components. The HMC742HFLP5E is housed in an RoHS compliant 5x5 mm QFN leadless package, and requires minimal external components. Electrical Specifications, TA = +25° C, 50 Ohm System Vdd = +5V, Vs= +5V Parameter Frequency Range Gain (Maximum Gain State) Gain Control Range Input Return Loss Output Return Loss Gain Accuracy: (Referenced to Maximum Gain State) All Gain States Output Power for 1 dB Compression Output Third Order Intercept Point (Two-Tone Output Power= 12 dBm Each Tone) Noise Figure (Max Gain State) Switching Characteristics tRISE, tFall (10 / 90% RF) 130 tON, tOFF (Latch Enable to 10 / 90% RF) Supply Current (Amplifier) Supply Current (Controller) Idd Min. Typ. 500 - 2700 12.5 31.5 14 10 Max. Min. Typ. 2700-4000 9 31.5 12 12 Max. Units MHz dB dB dB dB ± (0.3 + 4% of relative gain setting) Max 21 39 4 30 60 150 0.12 175 0.25 130 22 38 4.5 30 60 150 0.12 175 0.25 dB dBm dBm dB ns ns mA mA 12 - 1 For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC742HFLP5E v00.0211 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Maximum Gain vs. Frequency 16 Relative Gain Setting (Referenced to Maximum Gain State) 0 RELATIVE GAIN (dB) 12 GAIN (dB) -10 8dB 8 +25 C +85 C -40 C -20 31.5dB -30 16dB 4 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FREQUENCY (GHz) -40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FREQUENCY (GHz) 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 12 - 2 Input Return Loss 0 0dB RETURN LOSS (dB) Output Return Loss 0 RETURN LOSS (dB) -10 -10 -20 -20 -30 -30 -40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FREQUENCY (GHz) -40 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FREQUENCY (GHz) Bit Error vs. Frequency 4 3 BIT ERROR (dB) Bit Error vs. Attenuation State 1.5 1 BIT ERROR (dB) 0.5 0 -0.5 2.0 GHz 3.0 GHz -1 -1.5 0.7 GHz 4.0 GHz 2 31.5dB 1 0 -1 -2 16dB 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 0 4 8 12 16 20 24 28 32 FREQUENCY (GHz) ATTENUATION STATE (dB) For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC742HFLP5E v00.0211 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Relative Phase vs. Frequency (Referenced to Maximum Gain State) 40 30 RELATIVE PHASE (DEG) 20 8dB 10 0 -10 -20 -30 31.5dB 16dB Step Attenuation vs. Attenuation State 1.5 0.7 GHz 2.0 GHz 3.0 GHz 4.0 GHz STEP ATTENUATION (dB) 4.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 4 -0.5 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 8 NOISE FIGURE (dB) 6 FREQUENCY (GHz) Noise Figure vs. Frequency [1] Output P1dB vs. Temperature 28 23 P1dB (dBm) 4 18 +25 C +85 C -40 C 2 +25 C +85 C -40 C 13 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FREQUENCY (GHz) 8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FREQUENCY (GHz) Psat vs. Temperature 28 Output IP3 vs. Temperature 50 45 23 Psat (dBm) 40 IP3 (dBm) +25 C +85 C -40 C 18 35 30 25 20 13 +25 C +85 C -40 C 8 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FREQUENCY (GHz) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 FREQUENCY (GHz) [1] Max Gain State For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 12 - 3 HMC742HFLP5E v00.0211 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Serial Control Interface The HMC742HFLP5E contains a 3-wire SPI compatible digital interface (SERIN, CLK, LE). The serial control interrface is activated when P/S is kept high. The 6-bit serial word must be loaded MSB first. The positive-edge sensitive CLK and LE requires clean transitions. If mechanical switches are used, sufficient debouncing should be provided. When LE is high, 6-bit data in the serial input register is transferred to the attenuator. When LE is high CLK is masked to prevent data transition during output loading. When P/S is low, 3-wire SPI interface inputs (SERIN, CLK, LE) are disabled and the input register is loaded with parallel digital inputs (D0-D5). When LE is high, 6-bit parallel data changes the state of the part per truth table. For all modes of operations, the DVGA state will stay constant while LE is kept low. 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT 12 - 4 Parameter Min. serial period, tSCK Control set-up time, tCS Control hold-time, tCH LE setup-time, tLN Min. LE pulse width, tLEW Min LE pulse spacing, tLES Serial clock hold-time from LE, tCKN Hold Time, tPH. Latch Enable Minimum Width, tLEN Setup Time, tPS Typ. 100 ns 20 ns 20 ns 10 ns 10 ns 630 ns 10 ns 0 ns 10 ns 2 ns Timing Diagram (Latched Parallel Mode) Parallel Mode (Direct Parallel Mode & Latched Parallel Mode) Note: The parallel mode is enabled when P/S is set to low. Direct Parallel Mode - The attenuation state is changed by the control voltage inputs D0-D5 directly. The LE (Latch Enable) must be at a logic high at all times to control the attenuator in this manner. Latched Parallel Mode - The attenuation state is selected using the control voltage inputs D0-D5 and set while the LE is in the Low state. The attenuator will not change state while LE is Low. Once all Control Voltage Inputs are at the desired states the LE is pulsed. See timing diagram above for reference. For price, delivery and to place orders: Hittite Microwave Corporation, 20 Alpha Road, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com HMC742HFLP5E v00.0211 0.5 dB LSB GaAs MMIC 6-BIT DIGITAL VARIABLE GAIN AMPLIFIER, 0.5 - 4 GHz Power-Up States If LE is set to logic LOW at power-up, the logic state of PUP1 and PUP2 determines the power-up state of the part per PUP truth table. If the LE is set to logic HIGH at power-up, the logic state of D0-D5 determines the power-up state of the part per truth table. The DVGA latches in the desired power-up state approximately 200 ms after power-up. PUP Truth Table LE 0 0 0 0 1 PUP1 0 1 0 1 X PUP2 0 0 1 1 X Gain Relative to Maximum Gain -31.5 -24 -16 Insertion Loss 0 to -31.5 dB Power-On Sequence 12 VARIABLE GAIN AMPLIFIERS - DIGITAL - SMT The ideal power-up sequence is: GND, Vdd, digital inputs, RF inputs. The relative order of the digital inputs are not important as long as they are powered after Vdd / GND Note: The logic state of D0 - D5 determines the power-up state per truth table shown below when LE is high at power-up. Absolute Maximum Ratings RF Input Power at Max Gain [1] Truth Table Control Voltage Input D5 High High High High High High Low Low D4 High High High High High Low High Low D3 High High High High Low High High Low D2 High High High Low High High High Low D1 High High Low High High High High Low D0 High Low High High High High High Low Gain Relative to Maximum Gain 0 dB -0.5 dB -1 dB -2 dB -4 dB -8 dB -16 dB -31.5 dB 17.5 dBm (T = +85 °C) -0.5 to Vdd +0.5V 5.6V 5.5V 175 °C 1.2 W 75.6 °C/W -65 to +150 °C -40 to +85 °C Class 1A Digital Inputs (LE, SERIN, CLK, P/S, DO-D5, PUP1, PUP2) Controller Bias Voltage (Vdd) Amplifier Bias Voltage (Vcc) Channel Temperature Continuous Pdiss (T = 85 °C) (derate 13.3 mW/°C above 85 °C) [2] Thermal Resistance [3] Storage Temperature Operating Temperature ESD Sensitivity (HBM) [1] The maximum RF input power increases by the same amount the gain is reduced. The maximum input power at any state is no more than 28 dBm. [2] This value does not include the RF power dissipation in the attenuator. The loss in the attenuator depends on the state of the attenuator. The loss in the attenuator should be included to determine the total power dissipation in the part. [3] This value does not include the RF power dissipation in the attenuator. The thermal resistance at different states of the attenuator can be determined based on note [2] Any combination of the above states will provide a reduction in gain approximately equal to the sum of the bits selected. Control Voltage Table State Low High Vdd = +3V 0 to 0.5V @