HMC960LP4E

v00.0211 HMC960LP4E DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer typical Applications The HMC960LP4E is suitable for: • Baseband I/Q Transceivers • Direct Conversion & Low IF Transceivers • Diversity Receivers • ADC Drivers • Adaptive Gain Control features Low Noise: 6 dB NF High Linearity: Output IP3 +30 dBm Variable Gain: 0 to 40 dB High Bandwidth: DC to 100 MHz Precise Gain Accuracy: 0.5 dB Gain Step Excellent Magnitude and Phase Response Externally Controlled Common Mode Output Level Parallel or Serial Gain Control Read/Write Serial Port Interface (SPI) 14 IF/BASEBAND PROCESSING - SMT functional Diagram 24 Lead 4x4 mm SMT Package 16 mm2 Programmable Input Impedance (400 Ω Differential or 100 Ω Differential) general Description The HMC960LP4E is a digitally programmable dual channel variable gain amplifier. It supports discrete gain steps from 0 to 40 dB in precise 0.5 dB steps. It features a glitch free architecture to provide exceptionally smooth gain transitions. The device has matched gain paths which provide excellent quadrature balance over a wide signal bandwidth. The HMC960LP4E provides an SPI programmable input impedance of 100 Ω differential or 400 Ω differential (default). Externally controlled common mode output feature enables the HMC960LP4E to provide a flexible output interface to other parts in the signal path. Gain can be controlled via either a parallel interface (GC[6:0]) or via the read/write serial port (SPI). Housed in a compact 4x4mm (LP4) SMT QFN package, the HMC960LP4E requires minimal external components and provides a low cost alternative to more complicated switched amplifier architectures. 14 - 1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer table 1. electrical Specifications TA = +25°C, VDDI, VDDQ, DVDD = 5V +/-10%, GND = 0V, 400 Ω differential load unless otherwise stated. Parameter Analog Performance Gain Range Gain Step Size Gain Step Error Gain Absolute Error DC Offset [4] Signal Bandwidth 0.5 dB bandwidth 3 dB bandwidth Noise Figure 100 Ω Input Impedance (100 Ohm source) f = 40 MHz f = 40 MHz measured over all gain settings over all gain settings Gain: 0 dB (min gain) 10 dB 20 dB 30 dB 40 dB (max gain) 0 dB (min gain) 10 dB 20 dB 30 dB 40 dB (max gain) measured at f = 1 MHz 100 Ω matched input load using two tones near 20 MHz at 2 Vppd output using two tones near 20 MHz at 2 Vppd output using two tones near 20 MHz at 2 Vppd output using two tones near 20 MHz at 2 Vppd output tested at 20 MHz over all gains tested at 20 MHz 0.02 0.15 60 70 dB degrees dB 40 50 100 0 0.5 0.05 0.1 0 90 180 23 14 7.5 6.5 6 17.5 11 6.7 6.3 6.1 9 125 32 33 -75 -80 73 73 -80 -80 55 ±0.2 ±0.2 ±50 40 dB dB dB dB mV MHz MHz dB dB dB dB dB dB dB dB dB dB nV/rtHz nV/rtHz dBm dBm dBc dBc dBm dBm dBc dBc dB Conditions Min. Typ. Max. Units 14 IF/BASEBAND PROCESSING - SMT 14 - 2 400 Ω Input Impedance (400 Ohm source) Output noise 0 dB gain 40 dB gain Output IP3 0 dB gain 40 dB gain IM3 0 dB gain 40 dB gain Output IP2 0 dB gain 40 dB gain IM2 0 dB gain 40 dB gain Sideband Suppression (Uncalibrated)[1] I/Q Channel Gain Phase Balance[1] I/Q Channel Isolation Analog I/O Differential input impedance Full Scale Differential Input 400 Ω Differential Load 100 Ω Differential Load Input Common Mode Voltage Range 100 Ω Mode 400 Ω Mode min / max gain setting min / max gain setting 80 320 100 400 120 480 2/0.02 1/0.02 Ω Ω Vppd Vppd V 1 4 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer table 1. electrical Specifications, tA = +25°C (Continued) Parameter Full Scale Differential Output 400 Ω Differential Load 100 Ω Differential Load Output Voltage Range Output Common Mode Voltage Range Digital I/O Logic Levels Digital Input Low Level (VIL) Digital Input High Level (VIH) 1.5 0.4 Vdd - 0.4 0.4 V V V V [2] Conditions Min. Typ. Max. 2 1 Units Vppd Vppd V V 0.5 1 Tested at 30 MHz Operation Vdd/2 Vdd - 0.5 3 14 IF/BASEBAND PROCESSING - SMT Digital Output Low Level (VOL) Digital Output High Level (VOH) Supply Related Digital I/O Power Supply Supply Current [3] Analog & Digital Supplies Both I/Q channels 4.5 5 70 5.5 V mA [1] Sideband Rejection is only measured in dB, but relates to phase/magnitude channel imbalance as follows, for a mismatch of 1 degree phase and 0.1 dB magnitude: SBR = -10Log[(1+A^2-2Acosx)/(1+A^2+2Acosx)] where A = 10^(0.1/20) (linear magnitude) and x = 1*pi/180 (radians) [2] Output common mode voltage range is specified for worst case temperature, supply voltage, and bias settings with 2 Vppd signal amplitude. For 5 V supply and recommended biasing (op-amp bias =1 and driver bias=2), over 3.5 V is typical. See “Output IP3 vs. Common Mode Voltage vs. Driver Bias Setting[1]” in Figure 12 [3] Recommend bias setting (op-amp bias =1 and driver bias=2) [4] Standard deviation = 15 mV table 2. test Conditions Unless otherwise specified, the following test conditions were used Parameter Temperature Gain Setting Output Signal Level Input/Output Common Mode Level Programmed Impedance Output Load Supplies Driver Bias Setting Op-Amp Bias Setting Condition +27 °C 0 dB 2 Vppd 2.5 V 200 Ω per input (400 Ω differential) 200 Ω per output (400 Ω differential) Analog: +5 V, Digital +5 V ‘10’ ‘01’ (Standard Setting) 14 - 3 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer figure 1. gain vs. temperature (40 MHz) 40 35 30 MEASURED GAIN (dB) 25 20 15 10 5 0 0 5 10 15 20 25 PROGRAMMED GAIN (dB) 30 35 40 27 C 85 C -40 C -0.1 0 5 10 15 20 25 PROGRAMMED GAIN (dB) 30 35 40 GAIN ERROR (dB) 0.05 figure 2. gain error, Absolute & Step (40 MHz) 0.1 0 -0.05 ABSOLUTE GAIN RELATIVE GAIN 40 35 30 MEASURED GAIN (dB) 25 20 15 10 5 0 0 5 10 15 20 25 PROGRAMMED GAIN (dB) 30 35 40 27 C 85 C -40 C 0.5 0.25 GAIN ERROR (dB) 0 -0.25 ABSOLUTE GAIN RELATIVE GAIN -0.5 0 5 10 15 20 25 PROGRAMMED GAIN (dB) 30 35 40 figure 5. frequency response vs. gain [1] 50 40dB GAIN 40 30 20 GAIN (dB) 10 0 0dB GAIN -10 -20 -30 0.1 1 10 FREQUENCY (MHz) 100 1000 figure 6. Channel isolation vs. gain [2] -20 -30 -40 ISOLATION (dBfs) -50 -60 0 dB Gain -70 -80 -90 40 dB Gain -100 0.1 1 10 FREQUENCY (MHz) 100 1000 0dB 10dB 20dB 30dB 40dB [1] 2 dB Gain step increments [2] 10 dB Gain step increments For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 14 - 4 IF/BASEBAND PROCESSING - SMT figure 3. gain vs. temperature (100 MHz) figure 4. gain error, Absolute & Step (100 MHz) 14 HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer figure 7. iM2 vs. frequency & gain [4] -95 figure 8. Output ip2 vs. frequency & gain [4] 110 0 dB 10 dB 20 dB 30 dB 40 dB 100 -100 90 IM2 (dBc) -105 0 dB 10 dB 20 dB 30 dB 40 dB OIP2 (dBm) 80 -110 70 -115 10 20 30 60 14 IF/BASEBAND PROCESSING - SMT -40 -50 -60 IM3 (dBc) 40 50 FREQUENCY (MHz) 60 70 80 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 figure 9. iM3 vs. frequency and gain, Standard bias Setting [5][7] 0dB 5dB 10dB 15dB 20dB 25dB 30dB 35dB 40dB Gain Settings Less Than 30 dB figure 10. iM3 vs. frequency & gain, High Linearity bias Setting [6][7] -40 0dB 5dB 10dB 20dB 15dB 25dB 30dB 35dB 40dB -50 Gain Settings Less Than 30 dB -60 IM3 (dBc) -70 -70 -80 Gain Settings 30 dB or Greater -80 Gain Settings 30 dB or Greater -90 -90 -100 10 FREQUENCY (MHz) 100 -100 10 FREQUENCY (MHz) 100 figure 11. Output ip3 vs. frequency & gain, Standard bias Setting [5] [7] 45 40 35 OIP3 (dBm) 30 25 20 15 10 10 FREQUENCY (MHz) 100 0dB 5dB 10dB 15dB 20dB 25dB 30dB 35dB 40dB Greater Than 30 dB Gain Setting figure 12. Output ip3 vs. frequency & gain, High Linearity bias Setting [6] [7] 45 40 Greater Than 30 dB Gain Setting 35 OIP3 (dBm) 30 25 20 0dB 5dB 10dB 15dB 20dB 25dB 30dB 35dB 40dB Less Than 30 dB Gain Setting Less Than 30 dB Gain Setting 15 10 10 100 FREQUENCY (MHz) [3] VGA Gain = 0 dB, 2 Vpp differential output [4] 300 mVppd output, load impedance = 400 Ω differential [5] Amplifier bias setting = ‘01’ (Standard Setting) [6] Amplifier bias setting = ‘10’ (High Linearity Setting) 14 - 5 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer figure 13. Output ip3 vs. frequency & bias, gain = 10 db [5][6] [7] [9] 45 40 35 OIP3 (dBm) OIP3 (dBm) 30 25 20 15 10 10 FREQUENCY (MHz) 100 Standard Bias Setting Hight Linearity Bias Setting figure 14. Output ip3 vs. frequency & bias, gain = 30 db [5][6] [7] [9] 45 40 35 30 25 20 15 10 10 FREQUENCY (MHz) 100 Standard Bias Setting High Linearity Bias Setting 36 36 34 34 OIP3 (dBm) 30 Vdd = 4.5 Vdd = 4.75 Vdd = 5 Vdd = 5.25 Vdd = 5.5 4.5 V OIP3 (dBm) 32 32 5.5 V 30 28 28 Vdd = 4.5 Vdd = 4.75 Vdd = 5 Vdd = 5.25 Vdd = 5.5 4.5 V 5.5 V 26 0.5 1 1.5 2 2.5 3 COMMON MODE VOLTAGE (V) 3.5 4 26 0.5 1 1.5 2 2.5 3 3.5 COMMON MODE VOLTAGE (V) 4 4.5 figure 17. Output Voltage vs. input Voltage for Various gains 10 figure 18. Output vs. expected Output Over gain [8] 18 16 14 12 10 8 6 4 2 0 -2 -4 -6 -8 -10 1Vppd / -5dBm 0dB 5dB 10dB 15dB 20dB 25dB 30dB 35dB 40dB refP1dB 40 dB Gain OUTPUT VOLTAGE (Vppd) OUTPUT POWER (dBm) 40 dB Gain 0 dB Gain 1 2Vppd / 1dBm 0 dB Gain 0.1 0.01 0.1 1 INPUT VOLTAGE (Vppd) 0dB 5dB 10dB 15dB 20dB 25dB 30dB 35dB 40dB 10 -10 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 18 20 EXPECTED OUTPUT POWER (dBm) [7] Load Impedance = 400 Ω differential, 2 Vppd output [8] Output Power (dBm) is measured into 400 Ω output load [9] Use the following formulas conversion between dBm, dBVrms, and Vppd, using a 400 Ω differential load: dBVrms = 20log(Vppd/2.8284), dBm = 10log((Vppd/2.8284)2/400x10-3), dBm = dBVrms - 10log(400x10-3) For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 14 - 6 IF/BASEBAND PROCESSING - SMT figure 15. Output ip3 vs. Output Common Mode, Standard bias Setting [3][5] figure 16. Output ip3 vs. Output Common Mode, High Linearity bias Settings [3][6] 14 HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer figure 19. Output noise vs. Low frequency, 100 Ω rin [10] 1000 figure 20. noise figure vs. gain & input impedance at 1 MHz 25 400 Ohm 100 Ohm 20 NOISE FIGURE (dB) 100 NOISE (nv/rtHz) 40 dB Gain 100 15 10 10 0 dB Gain 0.001 0.01 0.1 1 10 5 14 IF/BASEBAND PROCESSING - SMT 75 SIDEBAND REJECTION (dBc) 70 65 FREQUENCY (MHz) 0 5 10 15 20 25 30 PROGRAMMED GAIN (dB) 35 40 figure 21. Sideband rejection vs. gain 1 MHz 40 MHz figure 22. transient behavior, 10 MHz, 6 db gain increase 0.4 0.3 0.2 OUTPUT (V) 0.1 0 -0.1 -0.2 6 dB gain increase 60 55 50 -0.3 -0.4 4000 45 0 5 10 15 20 25 PROGRAMMED GAIN (dB) 30 35 40 4500 5000 TIME (nsec) 5500 6000 [10] 5 dB Gain step increments 14 - 7 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer table 3. Absolute Maximum ratings Nominal 5 V Supply to GND VDDI, VDDQ, DVDD Common Mode Inputs Pins (CMI, CMQ) Input and Output Pins IIP, IIN, IQP, IQN, OIP, OIN, OQP, OQN Digital Pins SEN, SDI, SCK, SDO, GC[6:0] SDO min load impedance Operating Temperature Range Storage Temperature Maximum Junction Temperature Thermal Resistance (Rth) (junction to ground paddle) -0.3 to 5.5 V -0.3 to 5.5 V Reflow Soldering Peak Temperature Time at Peak Temperature ESD Sensitivity (HBM) 260 °C 40 µs 1 kV Class 1 C -0.3 to 5.5 V -0.3 to 5.5 V 1 kΩ -40 to +85 °C -65 to +125 °C 125 °C 10 °C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTROSTATIC SENSITIVE DEVICE OBSERVE HANDLING PRECAUTIONS 14 IF/BASEBAND PROCESSING - SMT 14 - 8 Outline Drawing NOTES: [1] PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED. [2] LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY. [3] LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN. [4] DIMENSIONS ARE IN INCHES [MILLIMETERS]. [5] LEAD SPACING TOLERANCE IS NON-CUMULATIVE. [6] PAD BURR LENGTH SHALL BE 0.15mm MAX. PAD BURR HEIGHT SHALL BE 0.25m MAX. [7] PACKAGE WARP SHALL NOT EXCEED 0.05mm [8] ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND. [9] REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN. package information Part Number HMC960LP4E Package Body Material RoHS-compliant Low Stress Injection Molded Plastic Lead Finish 100% matte Sn MSL Rating [2] MSL1 Package Marking [1] H960 XXXX [1] 4-Digit lot number XXXX [2] Max peak reflow temperature of 260 °C For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer table 4. pin Descriptions Pin Number Function Description Interface Schematic 1 CMQ Quadrature (Q) channel output common mode level 2, 3 OQN, OQP Quadrature (Q) channel positive and negative differential outputs 14 IF/BASEBAND PROCESSING - SMT 4 - 10 GC[6:0] Gain Control Input Pins Gain is defined as: GC[6:0] = 0d —> Gain = 0 dB GC[6:0] = 1d —> Gain = 0.5 dB GC[6:0] = 2d —> Gain = 1 dB GC[6:0] = 79d —> Gain = 39.5 dB GC[6:0] = 80d —> Gain = 40 dB 11 DVDD Digital 5V Supply. Must be locally decoupled to GND. 12, 14, 15 SCLK, SDI, SEN SPI Data clock, data input and enable respectively. 13 SDO SPI Data Output 16, 17 OIP, OIN Inphase (I) channel negative and positive differential outputs respectively 18 CMI Inphase (I) channel output common mode level 14 - 9 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer table 4. pin Descriptions (Continued) Pin Number Function Description Interface Schematic 19, 20 IIP, IIN Inphase (I) channel positive and negative differential inputs respectively 21 22 VDDI VDDQ Inphase (I) Channel 5 V Supply. Must be locally decoupled to GND Quadrature (Q) Channel 5 V Supply. Must be locally decoupled to GND 23, 24 IQN, IQP Quadrature (Q) channel negative and positive differential inputs respectively 14 IF/BASEBAND PROCESSING - SMT For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 14 - 10 HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer evaluation pCb 14 IF/BASEBAND PROCESSING - SMT The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. table 5. evaluation Order information Item Evaluation PCB Only Contents HMC960LP4E Evaluation PCB HMC960LP4E Evaluation PCB USB Interface Board 6’ USB A Male to USB B Female Cable CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software) Part Number 131109-HMC960LP4E Evaluation Kit 131191-HMC960LP4E 14 - 11 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer evaluation Setup 14 HMC960Lp4e Application information The wide bandwidth, large dynamic range, and excellent noise-linearity trade-off make the HMC960LP4E ideal for Automatic Gain Control applications in the baseband section of a direct down-conversion receiver. Matched dual amplifier design provides excellent gain and phase balance between the two channels. Externally controlled common mode voltage, and SPI programmable input impedance simplify the interface between the HMC960LP4E and other components in the signal path. The HMC960LP4E can be cascaded with HMC900LP5E without the need of any matching circuitry. Together, these two components provide a complete baseband line-up that can directly drive ADC’s such as the 12-bit, dual channel, 320 MSPS HMCAD1520. Figure 1. Typical Receive Path Block Diagram Showing HMC960LP4E For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 14 - 12 IF/BASEBAND PROCESSING - SMT HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer theory of Operation The HMC960LP4E consists of the following functional blocks 1. Input Match & Gain Stage 2. Second Gain Stage 3. Output Driver & Gain Stage 4. Bias Circuit 5. Serial Port Interface 6. Parallel Port Interface input Match & gain Stage The HMC960LP4E input stage consists of a user selectable 100 Ω or 400 Ω differential input impedance and a programmable gain of 0, 10 or 20 dB. A block diagram showing input impedance of the I channel is presented below, Q channel is similar. 14 IF/BASEBAND PROCESSING - SMT Figure 2. Input Stage Block Diagram Second gain Stage The HMC960LP4E second stage consists of a series of carefully scaled resistors to generate up to 10 dB of gain in 0.5 dB steps. The gain step is fully determined by resistor ratios and as such the gain precision is relatively independent of both temperature and process variation. 14 - 13 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer Output Driver & gain Stage The HMC960LP4E output driver consists of a differential class AB driver which is designed to drive typical ADC loads directly or can drive up to 200 Ω in parallel with 50 pF to AC ground per differential output. The stage provides a programmable 0 dB or 10 dB gain via switched resistors. Note that the output common mode of the driver is controlled directly via an input pin and can be set as per “Table 1. Electrical Specifications”. 14 IF/BASEBAND PROCESSING - SMT 14 - 14 Figure 3. Output Driver Block Diagram For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer gain Decode Logic The decode logic automatically allocates gain to the three stages so as to minimize output noise and optimize noise figure. Without using decode logic gain can be allocated arbitrarily, as shown in Table 11. Decode logic gain allocation, shown in Figure 4, can be controlled via the parallel port or the SPI, and reflects gain control shown in Table 10. 14 IF/BASEBAND PROCESSING - SMT Figure 4. Decode Logic Gain Allocation bias Circuit A band gap reference circuit generates the reference currents used by the different sections. The bias circuit is enabled or disabled as required with the I or Q channel as appropriate. 14 - 15 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer Serial port interface The HMC960LP4E features a four wire serial port for simple communication with the host controller. Typical serial port operation can be run with SCK at speeds up to 30 MHz. The details of SPI access for the HMC960LP4E is provided in the following sections. Note that the READ operation below is always preceded by a WRITE operation to Register 0 to define the register to be queried. Also note that every READ cycle is also a WRITE cycle in that data sent to the SPI while reading the data will also be stored by the HMC960LP4E when SEN goes high. If this is not desired then it is suggested to write to Register 0 during the READ operation so that the status of the device will be unaffected. power on reset and Soft reset The HMC960LP4E has a built in Power On Reset (POR) and a serial port accessible Soft Reset (SR). POR is accomplished when power is cycled for the HMC960LP4E while SR is accomplished via the SPI by writing 20h to Reg 0h followed by writing 00h to Reg 0h. All chip registers will be reset to default states approximately 250 us after power up. 14 IF/BASEBAND PROCESSING - SMT 14 - 16 Serial port Write Operation The host changes the data on the falling edge of SCK and the HMC960LP4E reads the data on the rising edge. A typical WRITE cycle is shown in Figure 5. It is 32 clock cycles long. 1. The host both asserts SEN (active low Serial Port Enable) and places the MSB of the data on SDI followed by a rising edge on SCK. 2. HMC960LP4E reads SDI (the MSB) on the 1st rising edge of SCK after SEN. 3. HMC960LP4E registers the data bits, D23:D0, in the next 23 rising edges of SCK (total of 24 data bits). 4. Host places the 5 register address bits, A4:A0, on the next 5 falling edges of SCK (MSB to LSB) while the HMC960LP4E reads the address bits on the corresponding rising edge of SCK. 5. Host places the 3 chip address bits, CA2:CA0=[110], on the next 3 falling edges of SCK (MSB to LSB). Note the HMC960LP4E chip address is fixed as “6d” or “110b”. 6. SEN goes from low to high after the 32th rising edge of SCK. This completes the WRITE cycle. 7. HMC960LP4E also exports data back on the SDO line. For details see the section on READ operation. Serial port reAD Operation The SPI can read from the internal registers in the chip. The data is available on SDO pin. This pin itself is tri-stated when the device is not being addressed. However when the device is active and has been addressed by the SPI master, the HMC960LP4E controls the SDO pin and exports data on this pin during the next SPI cycle. HMC960LP4E changes the data to the host on the rising edge of SCK and the host reads the data from HMC960LP4E on the falling edge. A typical READ cycle is shown in Figure 5. Read cycle is 32 clock cycles long. To specifically read a register, the address of that register must be written to dedicated Reg 0h. This requires two full cycles, one to write the required address, and a 2nd to retrieve the data. A read cycle can then be initiated as follows; 1. The host asserts SEN (active low Serial Port Enable) followed by a rising edge SCK. 2. HMC960LP4E reads SDI (the MSB) on the 1st rising edge of SCK after SEN. 3. HMC960LP4E registers the data bits in the next 23 rising edges of SCK (total of 24 data bits). The LSBs of the data bits represent the address of the register that is intended to be read. 4. Host places the 5 register address bits on the next 5 falling edges of SCK (MSB to LSB) while the HMC960LP4E reads the address bits on the corresponding rising edge of SCK. For a read operation this is “00000”. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer 5. Host places the 3 chip address bits on the next 3 falling edges of SCK (MSB to LSB). Note the HMC960LP4E chip address is fixed as “6d” or “110b”. 6. SEN goes from low to high after the 32nd rising edge of SCK. This completes the first portion of the READ cycle. 7. The host asserts SEN (active low Serial Port Enable) followed by a rising edge SCK. 8. HMC960LP4E places the 24 data bits, 5 address bits, and 3 chip id bits, on the SDO, on each rising edge of the SCK, commencing with the first rising edge beginning with MSB. 9. The host de-asserts SEN (i.e. sets SEN high) after reading the 32 bits from the SDO output. The 32 bits consists of 24 data bits, 5 address bits, and the 3 chip id bits. This completes the read cycle. Note that the data sent to the SPI during this portion of the READ operation is stored in the SPI when SEN is de-asserted. This can potentially change the state of the HMC960LP4E. If this is undesired it is recommended that during the second phase of the READ operation that Reg 0h is addressed with either the same address or the address of another register to be read during the next cycle. 14 IF/BASEBAND PROCESSING - SMT Figure 5. SPI Timing Diagram 14 - 17 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer DVDD = 5 V ±10%, GND = 0 V table 6. Main Spi timing Characteristics Parameter t1 t2 t3 t4 t5 t6 t7 t8 Conditions SDI to SCK Setup Time SDI to SCK Hold Time SCK High Duration [1] SCK Low Duration SEN Low Duration SEN High Duration SCK to SEN [2] SCK to SDO out [3] Min 8 8 10 10 20 20 8 Typ Max Units nsec nsec nsec nsec nsec nsec nsec 8 nsec [1] The SPI is relatively insensitive to the duty cycle of SCK. [2] SEN must rise after the 32nd falling edge of SCK but before the next rising SCK edge. If SCK is shared amongst several devices this timing must be respected. [3] Typical load to SDO is 10 pF, maximum 20 pF 14 IF/BASEBAND PROCESSING - SMT 14 - 18 parallel port interface The HMC960LP4E features a seven bit parallel port to aid in real time gain selection. The dynamic performance of the parallel port is specified below. table 7. gain Control parallel port timing Characteristics Parameter fSSP tSSP Conditions Gain control switching rate Allowable skew between GC[6:0] input transitions Min. Typ. Max. 20 10 Units MHz nsec For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer register Map Three registers provide all the required functionality via the SPI port. table 8. reg 01h - enable register Bit [0] [1] [2:3] [23:4] Name VGA_I_enable VGA_Q_enable spare unused Width 1 1 2 Default 0 0 0 VGA I channel enable bit VGA Q channel enable bit Description 14 IF/BASEBAND PROCESSING - SMT table 9. reg 02h - Settings register Bit Name Width Default Description Opamp bias setting. 00 -- min bias 11 -- max bias opamp_bias[1:0]=01 recommended for low frequency operation or 10 for improved linearity for higher frequency operation. Driver bias setting. 00 -- min bias 11 -- max bias drvr_bias[1:0]=10 recommended (characterized on recommended setting only) Input impedance setting: 0: Rin of 200 ohms selected 1: Rin of 50 ohms selected Source of Gain Control Input 0: Gain control taken from parallel port (pins) 1: Gain control taken from SPI register 3 Bypass gain decoder 0: Decoded gain taken from register 3, bits 1: Undecoded gain taken from register 3, bits (SPI gain control must be selected) Bypass gain deglitcher 0: Gain control deglitching active 1: Gain control deglitching disabled (applies to SPI and parallel port gain control) [1:0] opamp_bias[1:0] 2 01 [3:2] drvr_bias[1:0] 2 01 [4] Rin_50ohm_select 1 0 [5] Gain_Control_from_SPI 1 0 [6] Gain_Decode_Disable 1 0 [7] Gain_Deglitching_Disable 1 0 [23:8] unused 14 - 19 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC960LP4E v00.0211 DC - 100 MHz DUAL DigitAL VAriAbLe gAin AMpLifier with DriVer table 10. reg 03h - gain Control register WHen USing decode logic [1][2] Bit Name Width Default Description Reg 02h[5]=1 and Reg 02h[6]=0 (i.e. SPI gain control & gain decode enabled) gain[6:0] defines teh VGA channel I and Q gain of 0-40dB as follows... 0000000 - 0 dB, minimum gain setting 0000001 - 0.5 dB gain 0000010 - 1.0 dB gain ... 1001110 - 39 dB gain 1001111 - 39.5 dB gain 1010000 - 40 dB, maximum gain setting Reg 02h[5] = 1 and Reg 02h[6] = 1 (i.e. SPI gain control & gain decode bypassed) [23:7] unused [6:0] gain[6:0] 7 0000000 14 IF/BASEBAND PROCESSING - SMT 14 - 20 table 11. reg 03h - gain Control register, WHen nOt using decode logic [3][4] Bit Name Width Default Description gain[8:0] define the VGA I and Q channel gain when Reg 02h[5] = 1 and Reg 02h[6] = 1 (i.e. SPI gain control and gain decode bypassed) Generally the first 4 bits control the 1st and 3rd stage while the last 5 bits control the 2nd stage gain. x001nnnnn - 1st stage set to 0 dB x010nnnnn - 1st stage set to 10 dB x100nnnnn - 1st stage set to 20 dB [8:0] gain[8:0] 9 000000000 0xxxnnnnn - 3rd stage set to 0 dB 1xxxnnnnn - 3rd stage set to 10 dB xxxxnnnnn - 2nd stage set as follows: nnnnn = 00000 - set to 0 dB nnnnn = 00001 - set to 0.5 dB nnnnn = 10011 - set to 9.5 dB nnnnn = 10100 - set to 10 dB [23:9] unused [1] Reg 03h bit assignment depends on the setting of bits 5 and 6 in Reg 02h. If Reg 02h[5]=0, then all Reg 03h bits are ignored (parallel port selected) [2] For Reg 02h[5]=1 and Reg 02h[6]=0, gain control is via an SPI register with decode, and Reg 03h[6:0] are used as follows. [3] Note that the Parallel Port gain logic always uses the gain decode logic, and therefore the bit encoding is the same as Reg 03h - Gain Control Register WHEN USING decode logic. [4] For Reg 02h[5]=1 and Reg 02h[6]=1, gain control is via an SPI register without decode, and Reg 03h[6:0] are used as follows. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com