HMC987LP5E

v00.0611 HMC987LP5E LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Typical Applications The HMC987LP5E is suitable for: Features Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz Wideband: DC - 8 GHz Operating Frequency Flexible Input Interface: LVPECL, LVDS, CML, CMOS Compatible AC or DC Coupling On-Chip Termination 50 or 150 Ω (100/300 Ω Diff.) Multiple Output Drivers: Up to 8 Differential or 16 Single-Ended LVPECL Outputs: 800 mVpp into 50 Ω Single-Ended (+3 dBm Fo) One Adjustable Power CML/RF Output: -9 to 3 dBm Single-Ended Serial or Parallel Control, Hardware Chip-Enable Power-Down Current < 1 uA 32 Lead 5x5 mm SMT Package 25 mm2 • • • • • • • • SONET, Fibre Channel, GigE Clock Distribution ADC/DAC Clock Distribution Low Skew and Jitter Clock or Data Fanout Wireless/Wired Communications Level Translation High Performance Instrumentation Medical Imaging Single-Ended to Differential Conversion 3 HIGH SPEED LOGIC - SMT Functional Diagram General Description The HMC987LP5E 1-to-9 fanout buffer is designed for low noise clock distribution. It is intended to generate relatively square wave outputs with rise/ fall times < 100 ps. The low skew and jitter outputs of the HMC987LP5E, combined with its fast rise/ fall times, leads to controllable low-noise switching of downstream circuits such as mixers, ADCs/DACs or SERDES devices. The noise floor is particularly important in these applications, when the clocknetwork bandwidth is wide enough to allow squarewave switching. Driven at 2 GHz, outputs of the HMC987LP5E have a noise floor of -166 dBc/Hz, corresponding to a jitter density of 0.6 asec/rtHz - or 50 fs over an 8 GHz bandwidth. The input stage can be driven single-ended or differentially, in a variety of signal formats (CML, LVDS, LVPECL or CMOS), AC or DC coupled. The input stage also features adjustable input impedance. It has 8 LVPECL outputs, and 1 CML output with adjustable swing/power-level in 3 dB steps. Individual output stages may be enabled or disabled for power-savings when not required using either hardware control pins, or under control of a serial-port interface. 3-1 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Table 1. Electrical Specifications Unless otherwise specified: T = 27 °C, Regulated VDD of 3.3 V, 2 GHz, 6 dBm in, AC coupled single ended input and output, 120 Ω/leg DC termination, AC coupled into 50 Ω measuring load. Effects of customer eval board (“Evaluation PCB Schematic”) are de-embedded. For convenience, all voltages are referenced to GND (0V), but negative supply references are acceptable. Parameter DC Input Characteristics VDD (VCCHF=VCCA=VCCB=VCCRF) Input Common Mode Voltage Input Swing (Single Ended) Input Capacitance 3.0 1.35 0.2 0.5 3.3 2 3.6 VDD - 0.2 2 V V Vpp pF Conditions Min. Typ. Max. Units 3 HIGH SPEED LOGIC - SMT Input Impedance Single-Ended Differential Input Bias Current Logic Inputs Switching Threshold (Vsw) LVPECL DC Output Characteristics Output Voltage High Level Ouput Voltage Common Mode Output Voltage Low Level Output Voltage, Single-Ended AC Performance Input/Output Frequency [1] 3 dB Bandwidth Output Rise/Fall Time Typical Channel Skew Small Signal Gain S21 1000 MHz 4000 MHz Input P1dB 1000 MHz 4000 MHz Saturated Power in fundamental tone (Single-Ended) 1000 MHz 4000 MHz Output Voltage Swing (Vppd into 100 Ω) 700 MHz 2000 MHz 1.5 1.2 1.6 1.3 1.7 1.4 V V 2.5 -0.5 dBm dBm -20 -10 dBm dBm 26 15 dB dB 20% to 80% Across all LVPECL outputs relative to channel 1 0 > 400 Vpp single-ended DC 4000 65 1.5 3.1 8000 MHz MHz ps ps @ 3.3 V = 2.25 @ 3.3 V = 1.82 @ 3.3 V = 1.42 VDD - 1.2 VDD - 1.7 VDD - 2.1 VDD - 1.0 VDD - 1.5 VDD - 1.9 800 VDD - 0.8 VDD - 1.3 VDD - 1.7 V V V mVpp VIH/VIL within 50 mV of Vsw 38 47 54 %VDD Selectable Selectable Base current under external DC bias, Internal termination open. 50 / 150 100 / 300 165 Ω Ω µA [1] For frequencies < 700 MHz, square wave signals should be used to maintain high quality phase noise performance. 3-2 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Table 1. Electrical Specifications (Continued...) Parameter 4000 MHz Harmonics Fo 2Fo 3Fo 4Fo 5Fo SSB Phase Noise at 100 Hz Offset 622.08 MHz Carrier Frequency 1750 MHz Carrier Frequency 4000 MHz Carrier Frequency SSB Phase Noise Floor [2] 100 MHz Carrier Frequency 622.08 MHz Carrier Frequency 1750 MHz Carrier Frequency 2000 MHz Carrier Frequency 4000 MHz Carrier Frequency 4200 MHz Carrier Frequency Floor Jitter Density 622.08 MHz Carrier Frequency 1750 MHz Carrier Frequency 4000 MHz Carrier Frequency Integrated RMS Jitter 100 Hz to 100 MHz 12 kHz to 20 MHz 622.08 MHz Carrier Frequency 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz 100 Hz to 100 MHz 12 kHz to 20 MHz 1750 MHz Carrier Frequency 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz 100 Hz to 100 MHz 12 kHz to 20 MHz 4000 MHz Carrier Frequency 20 kHz to 80 MHz 50 kHz to 80 MHz 4 MHz to 80 MHz Output Return Loss 500 MHz to 4 GHz -16 17 8 17 17 16 7 3 6 6 6 4 2 4 4 4 -12 -8 fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms dB 1.8 0.7 0.5 asec/√Hz asec/√Hz asec/√Hz -167 -167 -166 -166 -163 -162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -147 -147 -147 dBc/Hz dBc/Hz dBc/Hz 2 -25 -8 -28 -12 dBm dBc dBc dBc dBc Conditions Min. 1.1 Typ. 1.2 Max. 1.3 Units V 3 HIGH SPEED LOGIC - SMT 3-3 [2] CML buffer has similar phase noise characteristics at maximum output power level. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Table 1. Electrical Specifications (Continued...) Parameter Isolation In to Out - Chip Disabled Off isolation - Relative to Power of neighboring driven port 700 MHz 4000 MHz 60 50 48 32 dB dB 47 dB Conditions Min. Typ. Max. Units Output to Output Isolation with 500 MHz Aggressor Signal Injected into Output Port To Locally paired output buffer To other buffers RF Output Buffer 25 45 dB dB 3 HIGH SPEED LOGIC - SMT 3 dB Bandwidth Max Output Power (vs Temperature at 2 GHz) Power Control Range (3 dB steps) Delay Relative to LVPECL Output Power Supply Rejection FM/Phase Pushing AM Rejection Current Consumption (3.3 V Unloaded Outputs) Chip Disabled 1 Output 2 Outputs 3 Outputs 4 Outputs 5 Outputs 6 Outputs 7 Outputs 8 Outputs 8 + RF Buffer (Min to Max Power) 198 Single-Ended Single-Ended 3 -9 5000 3.2 3 -140 MHz dBm dBm ps 0.8 7 ps/V dB 1 60 71 97 108 134 144 170 180 234 µA mA mA mA mA mA mA mA mA mA 3-4 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: T = 27 °C, Regulated VDD = 3.3 V, 2 GHz, 6 dBm in, AC coupled single ended input and output, 120 Ω/leg DC termination, AC coupled into 50 Ω measuring load. Figure 1. LVPECL Output vs. Frequency [1] 0.4 4 GHz OUTP 0.3 4 GHz OUTN 2 GHz OUTP Figure 2. LVPECL Output vs. Frequency [1] 0.6 0.4 OUTPUT VOLTAGE (V) 0.2 AMPLITUDE (V differential) 0.1 0 -0.1 -0.2 -0.3 -0.4 -800 2 GHz OUTN -600 -400 -200 0 1 GHz OUTP 200 400 1 GHz OUTN 600 800 0.2 0 -0.2 -0.4 -0.6 -0.8 0 20 40 60 TIME (ps) 80 100 120 4 GHz 2 GHz 1 GHz TIME (picoseconds) 3 HIGH SPEED LOGIC - SMT 3-5 Figure 3. Current Consumption vs. Num. of Enabled Buffers & Load Resistors[2] 500 120 Ohm DC Termination 400 Figure 4. Skew of LVPECL Outputs Relative to Output Channel 1 [4] 15 10 RELATIVE DELAY (psec) 200 Ohm DC Termination CURRENT (mA) 5 300 300 Ohm DC Termination 200 0 -5 100 Ground Current (Does not depend on termination) 0 1 2 3 4 5 5 6 7 8 RF Min RF Max -10 -15 P1 P2 P3 P4 P5 P6 P7 P8 NUMBER OF OUTPUTS SUCCESSIVELY TURNED ON OUTPUT CHANNEL Figure 5. Fundamental Output Power vs. Input Power [3] 5 0 OUTPUT POWER (dBm) 400 MHz Figure 6. Evaluation Board LVPECL Output Trace Loss vs. Frequency [5] 0 -1 OUTPUT TRACE LOSS (dB) -2 -3 -4 -5 -6 -7 2 GHz -5 3 GHz 4 GHz 5 GHz -15 6 GHz -20 -30 -24 -18 -12 -6 INPUT POWER (dBm) 0 6 -10 100 1000 OUTPUT FREQUENCY (MHz) 10000 [1] +2dBm input, Uncorrected for board loss. Measurement is band limited by the trace bandwidth of 7 GHz. [2] Buffers 1 through 8 are successively turned on. RF Min - RF buffer turned on with minimum gain, RF Max - RF buffer turned on with maximum gain [3] 200 Ω Termination, Corrected for board loss. [4] Characterized at 2 GHz, Effects of customer evaluation board skew and loss are embedded. [5] The graph shows only output trace distortion. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Figure 7. RF Buffer Fo Output Power vs. Frequency & Temperature (Max Gain) 4 3 OUTPUT POWER (dBm) OUTPUT POWER (dBm) Figure 8. RF Output Power Control 6 Reg04h[2:0]= 5d 3 Reg04h[2:0] = 4d 0 Reg04h[2:0] = 3d -3 Reg04h[2:0] = 2d -6 Reg04h[2:0] = 1d -9 2 1 0 -1 -2 -3 100 -40 C 27 C 85 C -12 3 HIGH SPEED LOGIC - SMT 1000 FREQUENCY (MHz) 10000 100 1000 FREQUENCY (MHz) 10000 Figure 9. Fundamental Output Power vs. Frequency & Temperature [6] 4 3 OUTPUT POWER (dBm) Figure 10. Fundamental Output Power vs. Frequency & Supply Voltage at 27 °C [6] 4 3 OUTPUT POWER (dBm) 2 1 3.6 V 0 -1 -2 -3 3.5 V 3.3 V 3.2 V 3.0 V 2 1 0 -1 -2 -3 100 1000 OUTPUT FREQUENCY (MHz) 10000 -40 C 27 C 85 C 100 1000 OUTPUT FREQUENCY (MHz) 10000 Figure 11. Fundamental Output Power vs. Frequency & Termination at 27 °C [6] 3 2 OUTPUT POWER (dBm) Figure 12. Signal Swing vs. Frequency [7] 1.6 1.4 1.2 SIGNAL SWING (Vppd) 1 Corrected For Evaluation Board Loss 1 0.8 0.6 0.4 0.2 0 Observed and Not Corrected For Evaluation Board Loss 0 -1 120 Ohms 200 Ohms 300 Ohms -2 -3 100 1000 OUTPUT FREQUENCY (MHz) 10000 0 1000 2000 3000 4000 5000 FREQUENCY (MHz) 6000 7000 8000 [6] Measured single-ended. Corrected for trace loss. 200 Ω DC termination, 3.3 V +6 dBm single-ended input. HMC987LP5E AC coupled to 50 Ω instrument. [7] Input signal power = + 6 dBm. 120 Ω/leg DC termination. AC coupled via 50 pF to 26 GHz Oscilloscope (50 Ohm/leg termination). 3-6 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Figure 13. Phase Noise Performance at 2 GHz (Differential Drive) [9] -110 -120 PHASE NOISE (dBc/Hz) -130 -140 -150 -160 -170 HMC830LP6GE Used as Source -180 10 3 Figure 14. Phase Noise Floor vs. Slew Rate -161 -162 Pin = -3 dBm Source + Fanout Output Noise PHASE NOI SE (dBc/Hz) -163 -164 -165 -166 100 MHz -167 -168 -169 Pin = 10 dBm 0 2 4 6 SLEW RATE (V/nsec) 8 Pin = 0 dBm Pin = 0 dBm 4 GHz Pin = 3 dBm 2 GHz Pin = 10 dBm 10 4 10 10 FREQUENCY OFFSET (Hz) 5 6 10 7 10 8 10 12 -156 -248 -158 PHASE NOISE (dBc/Hz) -250 FOM (dBc/Hz) -160 -252 -162 -254 -164 -256 -166 -258 -168 -15 -10 -5 0 INPUT POWER (dBm) 5 10 -260 0 500 1000 1500 SINUSOIDAL INPUT FREQUENCY (MHz) 2000 Figure 17. Phase Noise Floor at 2 GHz vs. VDD and DC Termination -162 200 Ohm Termination Figure 18. Phase Noise Floor vs. Temperature -160 -162 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) -164 Frequency = 4.2 GHz -164 -166 120 Ohm Termination -166 Frequency = 2 GHz 300 Ohm Termination -168 -168 Frequency = 100 MHz -170 2.7 2.8 2.9 3 3.1 VDD 3.2 3.3 3.4 3.5 -170 -50 0 50 100 TEMPERATURE (Deg. C) [8] Input power = 10 dBm single-ended. Phase Noise Floor (dBc/Hz) = FOM (dBc/Hz)) + 10log(Fout [Hz]) [9] HMC830LP6GE used as signal source, Driving +9 dBm differentially. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 3-7 HIGH SPEED LOGIC - SMT Figure 15. Phase Noise Floor at 1.6 GHz vs. Input Power Figure 16. Phase Noise Performance with Low Frequency Sinusoidal Inputs [8] 3 HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Figure 19. Harmonic Performance (Single-Ended Input & Output) [10] 10 0 -10 POWER (dBm) -20 -30 -40 -50 -60 -70 100 1000 FREQUENCY (MHz) 10000 4Fo 5Fo -25 2Fo 3Fo 3f0 S11 (dB) -10 Fo Figure 20. S-Parameters - S11 [11] 0 -5 Differential -15 Single-Ended -20 -30 0 2000 4000 6000 FREQUENCY (MHz) 8000 10000 3 HIGH SPEED LOGIC - SMT -30 -40 -50 -60 S12 (dB) -70 -80 -90 Differential -100 -110 0 2000 Single-Ended Figure 21. S-Parameters - S12 [11] Figure 22. S-Parameters - S22 [11] 0 -5 Single-Ended -10 S22 (dB) -15 Differential -20 -25 -30 4000 6000 8000 10000 0 2000 4000 6000 8000 10000 FREQUENCY (MHz) FREQUENCY (MHz) [10] Not corrected for board/cable loss. [11] Effects of the customer evaluation board are not corrected. Improvements in S11 and S22 are possible under different evaluation board configurations 3-8 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Table 2. Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Function VCCHF CLKP Differential clock inputs CLKN SDI SDO PMODE-SEL RFOUTP Differential signal output RFOUTN VCCRF SCLK SEN OUTP8 Differential signal output OUTN8 OUTP7 Differential signal output OUTN7 VCCB OUTN6 Differential signal output OUTP6 OUTN5 Differential signal output OUTP5 OUTP4 Differential signal output OUTN4 OUTP3 Differential signal output OUTN3 VCCA OUTN2 Differential signal output OUTP2 OUTN1 Differential signal output OUTP1 RFBUFEN CEN NC Active high RF buffer enable. The polarity of this control input can be swapped via SPI bit Reg03h[4]. Hardware chip enable No Connect Power supply Power supply Power supply Serial port clock Serial port latch enable Serial port data input Serial port data output Parallel mode select. If 1, pins (SCLK, SDI, SEN) are interpreted as a control-word which enables different buffers. See section Parallel Port Control Power Supply Description 3 HIGH SPEED LOGIC - SMT 3-9 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Table 3. Absolute Maximum Ratings Parameter Max Vdc to paddle on supply pins 1, 9, 16, 25 Max RF Power CLKP, CLKN CLKP, CLKN LVPECL Min Output Load Resistor LVPECL Output Load Current Digital Load Digital Input Voltage Range Thermal Resistance (junction to ground paddle) Operating Temperature Range Rating -0.3 V to +4 V 15 dBm single-ended - 0.3 V to 3.6 V 100 Ohms to GND 40 mA/leg 1 kΩ min -0.3 to 3.6 V 25 0C/W -40 OC to +85 OC -65 OC to + 125 OC +125 OC 3 HIGH SPEED LOGIC - SMT Storage Temperature Range Maximum Junction Temperature Reflow Soldering Peak Temperature Time at Peak Temperature ESD Sensitivity HBM 260 OC 40 sec Class 1B Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 - 10 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Outline Drawing 3 HIGH SPEED LOGIC - SMT Package Marking [1] H987 XXXX NOTES: [1] PACKAGE BODY MATERIAL: LOW STRESS INJECTION MOLDED PLASTIC SILICA AND SILICON IMPREGNATED. [2] LEAD AND GROUND PADDLE MATERIAL: COPPER ALLOY. [3] LEAD AND GROUND PADDLE PLATING: 100% MATTE TIN. [4] DIMENSIONS ARE IN INCHES [MILLIMETERS]. [5] LEAD SPACING TOLERANCE IS NON-CUMULATIVE. [6] PAD BURR LENGTH SHALL BE 0.15 mm MAX. PAD BURR HEIGHT SHALL BE 0.05 mm MAX. [7] PACKAGE WARP SHALL NOT EXCEED 0.05 mm [8] ALL GROUND LEADS AND GROUND PADDLE MUST BE SOLDERED TO PCB RF GROUND. [9] REFER TO HITTITE APPLICATION NOTE FOR SUGGESTED PCB LAND PATTERN. Table 4. Package Information Part Number HMC987LP5E Package Body Material RoHS-compliant Low Stress Injection Molded Plastic Lead Finish 100% matte Sn MSL Rating MSL1[2] [1] 4-Digit lot number XXXX [2] Max peak reflow temperature of 260°C For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 3 - 11 HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Evaluation PCB 3 HIGH SPEED LOGIC - SMT The circuit board used in the application should use RF circuit design techniques. Signal lines should have 50 Ohms impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. A sufficient number of via holes should be used to connect the top and bottom ground planes. The evaluation circuit board shown is available from Hittite upon request. Table 5. Evaluation Order Information Item Evaluation PCB Contents HMC987LP5E Evaluation PCB HMC987LP5E Evaluation PCB USB Interface Board 6’ USB A Male to USB B Female Cable CD ROM (Contains User Manual, Evaluation PCB Schematic, Evaluation Software, Part Number EVAL01- HMC987LP5E Evaluation Kit EKIT01- HMC987LP5E 3 - 12 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 6 5 4 3 2 1 TP1 REV A PRODUCTION RELEASE CP110719 CHANGER32,R35,R36,R63,R38,R39,R41,R42,R44,R45,R47,R48,R49,R50,R51,R52,R53,R54,R56,R57CP110885 D. ACEVAL 06/23/11 CP110719 CP110885 -------V.VADUVA 05/25/11 B 3.3V 350mA ECN# ZONE DESCRIPTION NAME DATE VCCRF 12 11 10 9 0.1uF 0 0 REVISIONS +5V MAX 16 15 14 13 NC NC VDD 82K NC 1 2 3 4 VRX NC REF NC RD BAND GAP 400 VR EN NC C1 R3 R62 C20 DEPOP 0 200 TP2 R17 R37 R38 DEPOP 100pF DEPOP 100pF 0.1uF U1 J16 C18 C19 D C17 OUT1-P C16 J13 VCCA VCCHF VCCB GND C4 0.1uF C3 4.7uF D C7 C108 R41 C31 DEPOP 200 DEPOP R61 HV NC 7 8 NC NC DEPOP 5 C6 6 4.7uF 4.7uF HMC976LP3E C2 NC R16 DEPOP DEPOP 0 C32 C30 OUT1-N 100pF 100pF C29 C28 J15 VCCRF 0 R15 VCCHF DEPOP C40 C39 DEPOP 100pF C38 J18 OUT2-P C42 C107 R47 200 DEPOP 100pF DEPOP 0 200 DEPOP 100pF Evaluation PCB Schematic R43 C41 R44 R4 200K 200K 200K 200K 200K 200K 0 R1 C101 100pF 0.1uF DEPOP DEPOP R5 C21 VCCA 0 0 200K R6 R21 C52 C50 C51 C49 C48 100pF R8 R9 R10 R7 R2 2 J30 J20 OUT2-N 1 4 3 6 5 8 7 v00.0611 C RFBUF_EN NC PMOD_SEL C109 R51 200 DEPOP 1 1 1 1 1 1 DEPOP 0 200 DEPOP 100pF 0 0.1uF NC NC NC NC C100 C60 R55 C63 100pF 10 9 12 11 SCK SDI SDO SEN CEN C53 R49 R23 C62 C68 DEPOP C69 100pF J22 OUT3-N C SSW-106-01-T-D HEADER TOUSB BOARD R63 C64 DEPOP 32 31 30 29 28 27 26 25 NC CEN OUTP1 OUTN1 OUTP2 OUTN2 VCCA 1 1K J5 2 2 2 2 2 2 RFBUFEN 0 OUTN3 OUTP3 OUTN4 OUTP4 OUTP5 OUTN5 OUTP6 18 17 0 HMC987LP5E 19 20 DEPOP 21 22 0 23 24 1 2 3 CLKP CLKN SDI SDO PMODE_SEL RFOUTP RFOUTN 4 5 6 VCCHF J6 R25 C71 R59 C110 C72 DEPOP DEPOP 0 J8 J10 J11 J9 J7 U2 R24 C70 DEPOP C79 100pF C78 DEPOP C88 100pF J23 OUT3-P C81 C89 J24 2 R52 200 C80 DEPOP J1 R11 0 C10 C8 100pF DEPOP VCCRF SCLK SEN OUTP8 OUTN8 OUTP7 OUTN7 100pF C90 DEPOP OUT4-N 100pF CLK-P C11 DEPOP 8 7 R33 R12 0 10 11 12 13 14 15 16 DEPOP DEPOP 100pF 9 J12 C12 SPI VCCB OUTN6 R56 200 J2 C103 VCCRF VCCB C104 DEPOP R26 C82 DEPOP C92 100pF C91 DEPOP C98 100pF J25 OUT4-P C94 C99 J26 CLK-N R27 0 R34 R31 DEPOP DEPOP B C22 C13 DEPOP 100pF 0.1uF 100pF J3 R13 C5 C102 C106 DEPOP DEPOP 0 C14 C9 DEPOP 100pF C73 DEPOP R60 C111 0 R57 200 C83 DEPOP 100pF C93 DEPOP OUT5-P 100pF B C74 R53 C84 C95 RFOUT-P R14 0 100pF R35 C15 C105 J4 DEPOP C54 RFOUT-N 0.1uF R28 0 DEPOP DEPOP 200 DEPOP C85 100pF DEPOP C96 100pF J27 OUT5-N R29 C86 0 R36 R32 DEPOP C25 R20 C24 0 DEPOP 200 0 DEPOP DEPOP C97 C65 DEPOP J28 R58 C112 R30 C61 DEPOP 0 DEPOP 0 J14 C26 DEPOP 100pF C27 R39 C23 R42 200 DEPOP DEPOP R54 200 OUT8-P R40 C114 C33 0 C75 DEPOP 100pF C87 DEPOP OUT6-P 100pF 100pF R50 200 C66 DEPOP C67 100pF C76 DEPOP C77 100pF J29 OUT6-N J17 DEPOP 100pF C37 DEPOP C36 C35 C34 OUT8-N C45 C44 DEPOP 200 R19 A C46 DEPOP 100pF J19 R45 R48 200 DEPOP 100pF C47 R46 C113 0 OUT7-P R18 C43 DEPOP 0 HITTITE MICROWAVE CORPORATION 20 Alpha Rd Chelmsford, MA 01824 TITLE C55 DEPOP PROJECT A 100pF SCH, EVAL CUSTOMER R22 0 NOTICE OF PROPRIETARY PROPERTY: THIS DOCUMENT AND THE INFORMATION CONTAINED IN IT ARE THE PROPRIETARY PROPERTY OF HITTITE MICROWAVE CORPORATION. IT MAY NOT BE COPIED OR USED IN ANY MANNER NOR MAY ANY OF THE INFORMATION IN OR UPON IT BE USED FOR ANY PURPOSE WITHOUT THE EXPRESSED WRITTEN CONSENT OF AN AUTHORIZED AGENT OF HITTITE MICROWAVE CORPORATION. J21 DEPOP 100pF C59 DEPOP C58 C57 C56 HMC987LP5E DRAWING#: DRAWN BY SHEET OUT7-N 5 130-00080-00 D.YOUNG DATE CODE ID NO. 1 11/18/2010 OF SIZE 1 REV 100pF 1CN88 4 3 2 1 C 29-06-2011_13:34 B For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz HMC987LP5E 6 3 3 - 13 HIGH SPEED LOGIC - SMT HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Theory of Operation HMC987LP5E Parallel Port Control The various outputs of the HMC987LP5E can be enabled/disabled by using parallel pin control, or via the SPI. In parallel-mode (PMODE-SEL = 1), the SPI input pins (SCLK, SKI, SEN) are re-interpreted as a 3-bit control bus, and enable the LVPECL drivers according to the following truth table. SCLK, SDI, SEN 000: OUT2 001: OUT2 + OUT7 010: OUT2 + OUT7 + OUT4 011: OUT2 + OUT7 + OUT4 + OUT6 100: OUT2 + OUT7 + OUT4 + OUT6 + OUT5 101: OUT2 + OUT7 + OUT4 + OUT6 + OUT5 + OUT3 110: OUT2 + OUT7 + OUT4 + OUT6 + OUT5 + OUT3 + OUT8 111: OUT2 + OUT7 + OUT4 + OUT6 + OUT5 + OUT3 + OUT8 + OUT1 Under SPI control (PMODE-SEL = 0, see section “Register Map” for the register map and SPI protocol details), there is slightly more flexibility in that any combination of buffers can be enabled or disabled via the individual buffer enable bits in Reg02h. The part features switches on both the input and output signals, so that when the part is disabled (via either the CEN pin, or the SPI control bit Reg01h[0]), the power-down current drops to < 2 µA, regardless of the IO termination scheme. 3 HIGH SPEED LOGIC - SMT 3 - 14 HMC987LP5E Input Stage The HMC987LP5E input stage, Figure 23, is flexible. It can be driven single-ended or differential, with LVPECL, LVDS, or CML signals. If driven single-ended, a large AC coupling cap to ground should be used on the undriven input. The input impedance is selectable, via Reg03h[3], between 50 Ω or 150 Ω (100 Ω or 300 Ω differential). The DC bias level of 2.0 V can be generated internally by programming Reg03h[1] =1 (default configuration), supplied externally, or generated via an LVPECL termination network inside the part. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz 3 Figure 23. HMC987LP5E Input Stage Figure 24 to Figure 28 illustrate common HMC987LP5E input interface configurations. Figure 24. HMC987LP5E DC Coupled CML Interface Figure 25. HMC987LP5E DC Coupled CMOS Interface For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 3 - 15 HIGH SPEED LOGIC - SMT HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz 3 HIGH SPEED LOGIC - SMT Figure 26. HMC987LP5E DC Coupled LVPECL Interface Figure 27. HMC987LP5E AC Coupled Differential CML / LVPECL / LVDS / CMOS Interface Figure 28. HMC987LP5E AC Coupled Single-Ended CML / LVPECL / LVDS / CMOS Interface HMC987LP5E LVPECL Output Stage The LVPECL output driver produces up to 1.6 Vppd swing into 50 Ω loads. LVPECL drivers are terminated with off-chip resistors that provide the DC current through the emitter-follower output stage. The output stage has a switch which disconnects the output driver from the load when not used. The switch series resistor significantly improves the output match when driving into 50 Ω transmission lines. The switch series resistor causes a small DC level shift and swing degradation, depending on the termination current. If unused, disabled LVPECL outputs can be left floating, terminated, or grounded. 3 - 16 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz 3 Figure 30 to Figure 32 illustrate common HMC987LP5E output interface configurations. Figure 30. HMC987LP5E DC Coupled to LVPECL Interface Figure 31. HMC987LP5E AC coupled to LVDS / CML / LVPECL / CMOS For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 3 - 17 HIGH SPEED LOGIC - SMT Figure 29. HMC987LP5E Output Stage HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz 3 HIGH SPEED LOGIC - SMT Figure 32. HMC987LP5E DC Coupled to CMOS Interface The user has a number of choices in how they connect LVPECL drivers and receivers, and there are great number of resources that deal in detail with this issue. As a quick introduction, there are compromises between matching performance, common mode levels, and signal swing. For clocking applications, the user often has the luxury of using AC coupling, unlike in many data-path situations. Figure 33 shows a simplified interface schematic between an LVPECL output and input stage - where various options and trade-offs for the termination components are provided in Table 6. The Hittite evaluation board has a great deal of flexibility in how the I/Os are configured, and allows the configuration in Figure 33, among many others. Figure 33. Recommended HMC987LP5E Interface Diagram Table 6. HMC987LP5E Interface Values Rs - Used to increase Ro to match to 50 Ω environment. HMC987LP5E already has ~ 10 Ω internally. 0Ω 10 Ω Hittite EVB: Largest signal swing, lowest common mode shift Better S22 RL - DC current termination for LVPECL output stage 120 Ω 200 Ω 300 Ω OPEN Cac - AC coupling cap BIG CAP SHORT Hittite EVB default: If using AC coupling If using internal DC termination network at the Rx Hittite EVB default: Standard LVPECL termination voltages Reduced current, no performance degradation Further reduced current, lower output power but flatter frequency response If using internal DC termination network at the Rx 3 - 18 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz HMC987LP5E RF Output Stage The RF output buffer is a CML output stage with 50 Ω impedance (single-ended) and adjustable power. In parallel mode (the PMODE_SEL pin = 1), it is at max gain (~ +3 dBm single-ended), whereas under SPI control, the gain can be lowered in ~3 dB steps down to -9 dBm single-ended. See Reg04h for more information. 3 Figure 34. HMC987LP5E Output Stage HMC987LP5E Serial Port Interface (SPI) Control HMC987LP5E can be controlled via SPI or parallel port control (for more information on parallel control see “ HMC987LP5E Parallel Port Control”). SPI control offers more flexibility. External pin PMODE-SEL = 1 configures the HMC987LP5E for parallel port operation, while PMODE-SEL = 0 will enable the SPI control of HMC987LP5E. The SPI control is required in order to re-configure the input bias network from its’ default state (Reg03h), to adjust the output power control on the RF/CML buffer, and to individually enable arbitrary LVPECL outputs. Operational Modes Serial Port Interface features: a. b. Compatibility with general serial port protocols that use a shift and strobe approach to communication. Compatible with HMC multi-Chip solutions, useful to address multiple chips of various types from a single serial port bus. For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 3 - 19 HIGH SPEED LOGIC - SMT HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Serial Port Write Operation Table 7. SPI Open Mode - Write Timing Characteristics Parameter t1 t2 t3 t4 t5 t6 SDI setup time SDI hold time SEN low duration SEN high duration SCLK 9 Rising Edge to SEN Rising Edge Serial port Clock Speed SEN to SCLK Recovery Time Conditions Min. 3 3 10 10 10 DC 10 50 Typ. Max. Units ns ns ns ns ns MHz ns 3 HIGH SPEED LOGIC - SMT A typical WRITE cycle is shown in Figure 35. a. b. c. d. e. f. g. h. The Master (host) places 9 bit data, d8:d0, MSB first, on SDI on the first 9 falling edges of SCLK. The slave (HMC987LP5E) shifts in data on SDI on the first 9 rising edges of SCLK Master places 4 bit register address to be written to, r3:r0, MSB first, on the next 4 falling edges of SCLK (10-13) Slave shifts the register address bits on the next 4 rising edges of SCLK (10-13). Master places 3 bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (14-16). The HMC987LP5E chip address is fixed at 001. Slave shifts the chip address bits on the 3 rising edges of SCLK (14-16). Master asserts SEN after the 16th rising edge of SCLK. Slave registers the SDI data on the rising edge of SEN. Figure 35. SPI Timing Diagram, Write Operation Serial Port Read Operation In order ensure correct read operation a pull-down resistor to ground (~1-2kOhm) is recommended on the Serial Data Out line from the part. A typical READ cycle is shown in Figure 36. In general, SDO line is always active during the WRITE cycle. SDO will contain the data from the addresses pointed to by Reg00h. If Reg00h is not changed, the same data will always be present on the SDO. If it is desired to READ from a specific address, it is necessary in the first SPI cycle to write the desired address to Reg00h, then in the next SPI cycle the desired data will be available on the SDO. An example of the two cycle procedure to read from any random address is as follows: For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 3 - 20 HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz The Master (host), on the first 9 falling edges of SCLK places 9 bit data, d8:d0, MSB first, on SDI as shown in Figure 36. d8:d0 should be set to zero. d3:d0 = address of the register to be READ on the next cycle. a. b. The slave (HMC987LP5E) shifts in data on SDI on the first 9 rising edges of SCLK Master places 4 bit register address , r3:r0, ( the address the WRITE ADDRESS register), MSB first, on the next 4 falling edges of SCLK (10-13). r3:r0=0000. c. Slave shifts the register bits on the next 4 rising edges of SCLK (10-13). d. Master places 3 bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCLK (14-16). The HMC987LP5E chip address is fixed at 001. e. Slave shifts the chip address bits on the next 3 rising edges of SCLK (14-16). f. Master asserts SEN after the 16th rising edge of SCLK. g. Slave registers the SDI data on the rising edge of SEN. h. Master clears SEN to complete the address transfer of the two part READ cycle. i. If we do not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on SDI to Register zero on the READ back part of the cycle. j. Master places the same SDI data as the previous cycle on the next 16 falling edges of SCLK. k. Slave (HMC987LP5E) shifts the SDI data on the next 16 rising edges of SCLK. l. Slave places the desired data (i.e. data from address in Reg00h[3:0]) on SDO on the next 16 rising edges of SCLK. m. Master asserts SEN after the 16th rising edge of SCLK to complete the cycle. Note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the SDO output to prevent a possible bus contention issue. 3 HIGH SPEED LOGIC - SMT 3 - 21 Table 8. SPI Open Mode - Read Timing Characteristics Parameter t1 t2 t3 t4 t5 t6 t7 SDI setup time SDI hold time SEN low duration SEN high duration SCLK Rising Edge to SDO time SEN to SCLK Recovery Time SCLK 16 Rising Edge to SEN Rising Edge 10 10 Conditions Min. 3 3 10 10 8.2+0.2ns/pF Typ. Max. Units ns ns ns ns ns ns ns For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz 3 HIGH SPEED LOGIC - SMT Figure 36. SPI Diagram, Read Operation 2- Cycles 3 - 22 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Register Map Table 9. Reg00h ID Register (Read Only) Bit [3:0] [4] [4:0] Name Read Control Soft Reset Chip ID (Read Only) Width 4 Default (Write Only) Description Table 10. Reg01h Master Enable Bit [0] Name Master Chip Enable Width 1 Default 1 Description Table 11. Reg02h Individual Enables Bit [0] [1] [2] [3] [4] [5] [6] [7] Name en1 en2 en3 en4 en5 en6 en7 en8 Width 1 1 1 1 1 1 1 1 Default 1 1 1 1 1 1 1 1 Enable Buffer 1 Description 3 HIGH SPEED LOGIC - SMT 3 - 23 Enable Buffer 2 Enable Buffer 3 Enable Buffer 4 Enable Buffer 5 Enable Buffer 6 Enable Buffer 7 Enable Buffer 8 Table 12. Reg03h Rx Buffer Configuration Bit [0] [1] [2] [3] [4] [8:5] DC Internal DC LVPECL Zin 50 RFBUF XOR Name Width 1 1 1 1 1 4 Default 0 1 0 1 0 0 Reserved 0 Use internal DC bias string Use internal LVPECL Rx termination Input termination select 1 - 50 Ω single-ended, 100 Ω differential 0- 150 Ω single-ended, 300 Ω differential Toggle (XOR with RFBUFEN pin) the internal RF Buffer on/off Reserved 0 Description Table 13. Reg04h Gain Select Bit Name Width Default 0: Disabled 1: -9 dBm single-ended 2: -6 dBm single-ended 3: -3 dBm single-ended 4: 0 dBm single-ended >4: 3 dBm single-ended Description [2:0] RF Buffer Gain 3 7 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMC987LP5E v00.0611 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz Table 14. Reg05h Biases Bit [1:0] [3:2] [5:4] [8:6] Name Reserved Reserved Reserved Reserved Width 2 2 2 3 Default 2 2 3 0 Reserved - 2 Reserved - 2 Reserved - 3 Reserved - 0 Description 3 HIGH SPEED LOGIC - SMT 3 - 24 For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com