HMCAD1100

HMCAD1100 v03.0611 Octal 13/12-Bit 20/40/50 MSPS a/D cOnverter Features • 50 MsPs Maximum sampling rate • Ultra Low Power Dissipation 23 mW/Channel at 20MsPs 35 mW/Channel at 40MsPs 41 mW/Channel at 50MsPs • 72.2 dB snr at 8 MHz FIn • 0.5 µs startup from sleep, 15 µs from Power Down • reduced Power Dissipation Modes Available • Internal reference Circuitry with no external Components required typical applications • Medical Imaging • Wireless Infrastructure • test and Measurement • Instrumentation Pin compatible Parts • HMCAD1101 • HMCAD1102 0 A / D Converters - sMt • Coarse and Fine Gain Control • Internal offset Correction • 1.8v supply voltage • serial LvDs output • 12 and 14-bit output Available • 64 Lead 9 x 9 mm sMt Package Functional Diagram Figure 1. Functional Block Diagram F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 0-1 HMCAD1100 v03.0611 Octal 13/12-Bit 20/40/50 MSPS a/D cOnverter General Description HMCAD1100 is a high performance low power octal analog-to-digital converter (ADC). the ADC is based on a proprietary structure and employs internal reference circuitry, a serial control interface and serial LvDs output data. Data and frame synchronization output clocks are supplied for data capture at the receiver. various modes and configuration settings can be applied to the ADC through the serial control interface (sPI). each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. register settings determine the exact function of this external pin. there are two options for the serial LvDs outputs, 12- bit or 14-bit. In 12-bit mode, the LsB bit from the ADCs are removed in the output stream. In 14-bit mode, a ‘0’ is added in the LsB position. the HMCAD1100 is designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors. the very low start up times for the HMCAD1100 allows significant power reduction in duty-cycled systems, by utilizing the sleep Modes or Power Down Mode when the receive path is idle. electrical Specifications Dc electrical Specifications AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, 50MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 14 bit output, unless otherwise noted Parameter DC accuracy no Missing Codes offset error Gain error Gain Matching DnL InL vCM Analog Input Input Common Mode Full scale range Input Capacitance Bandwidth Power Supply Analog supply voltage Digital supply voltage ovDD supply voltage temperature operating temperature operating free-air temperature -40 85 °C Digital and output driver supply voltage Digital CMos Input supply voltage 1.7 1.7 1.7 1.8 1.8 1.8 2 2 3.6 v v v Analog input common mode voltage Differential input voltage range Differential input capacitance Input Bandwidth 500 vCM -0.1 2 2 vCM +0.2 v vpp pF MHz Gain matching between channels. ±3sigma value at worst case conditions Differential nonlinearity (12-bit level) Integral nonlinearity (12-bit level) Common mode voltage output ±0.5 ±0.2 ±0.6 vAvDD/2 offset error after internal digital offset correction Guaranteed 1 ±6 LsB %Fs %Fs LsB LsB Description Min typ Max Unit 0 A / D Converters - sMt 0-2 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1100 v03.0611 Octal 13/12-Bit 20/40/50 MSPS a/D cOnverter ac electrical Specifications - 20 MSPS AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, 20 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 14 bit output, unless otherwise noted Parameter Performance snr     sInAD     sFDr signal to noise ratio FIn = 8 MHz FIn = 30 MHz signal to noise and Distortion ratio FIn = 8 MHz FIn = 30 MHz spurious Free Dynamic range FIn = 8 MHz FIn = 30 MHz second order Harmonic Distortion FIn = 8 MHz FIn = 30 MHz third order Harmonic Distortion FIn = 8 MHz FIn = 30 MHz effective number of Bits FIn = 8 MHz FIn = 30 MHz signal applied to 7 channels (FIn0). Measurement taken on one channel with full scale at FIn1. FIn1 = 8 MHz, FIn0 = 9.9 MHz 11.6 11.5 95 bits bits dBc 75 82 77 dBc dBc 85 95 95 dBc dBc 75 82 77 dBc dBc 69 71.5 70.7 dBFs dBFs 70 72.2 71.5 dBFs dBFs Description Min typ Max Unit 0 A / D Converters - sMt     HD2     HD3     enoB     Crosstalk Power Supply Analog supply Current Digital supply Current Analog Power Dissipation Digital Power Dissipation total Power Dissipation Power Down Dissipation sleep Mode Dissipation sleep Channel Mode Dissipation sleep Channel savings Clock Inputs Max. Conversion rate Min. Conversion rate 47 Digital and output driver supply 54 84 97 180 Power down mode dissipation Deep sleep mode power dissipation Power dissipation with all channels in sleep channel mode (Light sleep) Power dissipation savings per channel off 10 30 46 17 mA mA mW mW mW µW mW mW mW 20 15 MsPs MsPs 0-3 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1100 v03.0611 Octal 13/12-Bit 20/40/50 MSPS a/D cOnverter ac electrical Specifications - 40 MSPS AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, 40 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 14 bit output, unless otherwise noted Parameter Performance snr     sInAD     sFDr     HD2     HD3     enoB     Crosstalk Power Supply Analog supply Current Digital supply Current Analog Power Dissipation Digital Power Dissipation total Power Dissipation Power Down Dissipation sleep Mode Dissipation sleep Channel Mode Dissipation sleep Channel savings Clock Inputs Max. Conversion rate Min. Conversion rate 40 20 MsPs MsPs Power down mode dissipation Deep sleep mode power dissipation Power dissipation with all channels in sleep channel mode (Light sleep) Power dissipation savings per channel off Digital and output driver supply 90 67 162 120 280 10 41 71 26 mA mA mW mW mW µW mW mW mW signal to noise ratio FIn = 8 MHz FIn = 30 MHz signal to noise and Distortion ratio FIn = 8 MHz FIn = 30 MHz spurious Free Dynamic range FIn = 8 MHz FIn = 30 MHz second order Harmonic Distortion FIn = 8 MHz FIn = 30 MHz third order Harmonic Distortion FIn = 8 MHz FIn = 30 MHz effective number of Bits FIn = 8 MHz FIn = 30 MHz signal applied to 7 channels (FIn0). Measurement taken on one channel with full scale at FIn1. FIn1 = 8 MHz, FIn0 = 9.9 MHz 11.6 11.5 95 bits bits dBc 75 82 77 dBc dBc 85 95 95 dBc 75 82 77 dBc dBc 69 71.5 70.7 dBFs dBFs 70 72.2 71.5 dBFs dBFs Description Min typ Max Unit 0 A / D Converters - sMt 0-4 dBc F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1100 v03.0611 Octal 13/12-Bit 20/40/50 MSPS a/D cOnverter ac electrical Specifications - 50 MSPS AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, 50 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 14 bit output, unless otherwise noted Parameter Performance snr     sInAD     sFDr signal to noise ratio FIn = 8 MHz FIn = 30 MHz signal to noise and Distortion ratio FIn = 8 MHz FIn = 30 MHz spurious Free Dynamic range FIn = 8 MHz FIn = 30 MHz second order Harmonic Distortion FIn = 8 MHz FIn = 30 MHz third order Harmonic Distortion FIn = 8 MHz FIn = 30 MHz effective number of Bits FIn = 8 MHz FIn = 30 MHz signal applied to 7 channels (FIn0). Measurement taken on one channel with full scale at FIn1. FIn1 = 8 MHz, FIn0 = 9.9 MHz 11.6 11.5 95 bits bits dBc 75 82 77 dBc dBc 85 95 95 dBc dBc 75 82 77 dBc dBc 69 71.5 70.7 dBFs dBFs 70 72.2 71.5 dBFs dBFs Description Min typ Max Unit 0 A / D Converters - sMt     HD2     HD3     enoB     Crosstalk Power Supply Analog supply Current Digital supply Current Analog Power Dissipation Digital Power Dissipation total Power Dissipation Power Down Dissipation sleep Mode Dissipation sleep Channel Mode Dissipation sleep Channel savings Clock Inputs Max. Conversion rate Min. Conversion rate 111 Digital and output driver supply 73 200 132 331 Power down mode dissipation Deep sleep mode power dissipation Power dissipation with all channels in sleep channel mode (Light sleep) Power dissipation savings per channel off 10 46 83 31 mA mA mW mW mW µW mW mW mW 50 20 MsPs MsPs 0-5 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1100 v03.0611 Octal 13/12-Bit 20/40/50 MSPS a/D cOnverter Digital and Switching Specifications AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, unless otherwise noted Parameter Clock Inputs Duty Cycle Compliance Input range, diff Input range, sine Input range, CMos Input common mode voltage Input capacitance Logic inputs (CMOS) vHI vHI vLI vLI IHI ILI CI Data outputs (LVDS) Compliance voUt vCM output coding Timing Characteristics Aperture delay Aperture jitter start up time from Power Down Mode and Deep sleep Mode to Active Mode. references have reached 99% of final value. see section “Clock Frequency” start up time from Power Down Mode and Deep sleep Mode to Active Mode in µs. tsLPCH tovr tLAt LVDS Output Timing Characteristics tdata tProP LCLK to data delay time (excluding programmable phase shift) Clock propagation delay. LvDs bit-clock duty-cycle Frame clock cycle-to-cycle jitter teDGe tCLKeDGe Data rise- and fall time 20% to 80% Clock rise- and fall time 20% to 80% 0.4 0.4 7*tLvDs + 2.6 45 250 7*tLvDs + 3.5 7*tLvDs + 4.2 55 2.5 ps ns %LCLK cycle %LCLK cycle ns ns start up time from sleep Channel Mode to Active Mode out of range recovery time Pipeline delay 0.8