HMCAD1102

HMCAD1102 v03.0611 Octal 12-Bit 80 MSPS a/D cOnverter Features • 80 MsPs Maximum sampling rate • Ultra Low Power Dissipation 59 mW/Channel at 80MsPs • 70.1 dB snr at 8 MHz FIn • 0.5 µs startup from sleep 15 µs from Power Down • reduced Power Dissipation Modes Available • Internal reference Circuitry with no external Components required typical applications • Medical Imaging • Wireless Infrastructure • test and Measurement • Instrumentation Pin compatible Parts • HMCAD1101 • HMCAD1100 • HMCAD1100/01-AC specifications are also valid for HMCAD1102 0 A / D Converters - sMt • Coarse and Fine Gain Control • Internal offset Correction • 1.8v supply voltage • serial 12-Bit LvDs output • 14-bit LvDs output Available Up to 65MsPs • 64 Lead 9 x 9 mm sMt Package Functional Diagram Figure 1. Functional Block Diagram 0-1 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1102 v03.0611 Octal 12-Bit 80 MSPS a/D cOnverter General Description HMCAD1102 is a high performance low power octal analog-to-digital converter (ADC). the ADC is based on a proprietary structure and employs internal reference circuitry, a serial control interface and serial LvDs output data. Data and frame synchronization output clocks are supplied for data capture at the receiver. various modes and configuration settings can be applied to the ADC through the serial control interface (sPI). each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. register settings determine the exact function of this external pin. the HMCAD1102 is designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors. the very low start up times for the HMCAD1102 allows significant power reduction in duty-cycled systems, by utilizing the sleep Modes or Power Down Mode when the receive path is idle. electrical Specifications Dc electrical Specifications Parameter DC accuracy no Missing Codes offset error Gain error Gain Matching DnL InL vCM Analog Input Input Common Mode Full scale range Input Capacitance Bandwidth Power Supply Analog supply voltage Digital supply voltage Digital supply voltage ovDD supply voltage temperature operating temperature operating free-air temperature -40 85 °C Digital and output driver supply voltage (up to 65 MsPs) Digital and output driver supply voltage (above 65 MsPs) Digital CMos Input supply voltage 1.7 1.7 1.8 1.7 1.8 1.8 1.9 1.8 2 2 2 3.6 v v v v Analog input common mode voltage Differential input voltage range Differential input capacitance Input Bandwidth 500 vCM -0.1 2 2 vCM +0.2 v vpp pF MHz Gain matching between channels. ±3sigma value at worst case conditions Differential nonlinearity (12-bit level) Integral nonlinearity (12-bit level) Common mode voltage output ±0.5 ±0.2 ±0.6 vAvDD/2 offset error after internal digital offset correction Guaranteed 1 ±6 LsB %Fs %Fs LsB LsB Description Min typ Max Unit AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, 80 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 12 bit output, unless otherwise noted 0 A / D Converters - sMt 0-2 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1102 v03.0611 Octal 12-Bit 80 MSPS a/D cOnverter ac electrical Specifications - 80 MSPS AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, 80 MsPs clock, 50% clock duty cycle, -1 dBFs 8 MHz input signal, 12 bit output, unless otherwise noted Parameter Performance snr signal to noise ratio FIn = 8 MHz FIn = 30 MHz sInAD signal to noise and Distortion ratio FIn = 8 MHz FIn = 30 MHz sFDr spurious Free Dynamic range FIn = 8 MHz FIn = 30 MHz HD2 second order Harmonic Distortion FIn = 8 MHz FIn = 30 MHz HD3 third order Harmonic Distortion FIn = 8 MHz FIn = 30 MHz enoB effective number of Bits FIn = 8 MHz FIn = 30 MHz Crosstalk Power Supply Analog supply Current Digital supply Current Analog Power Digital Power total Power Dissipation Power Down sleep Mode sleep Channel Mode sleep Channel savings Clock Inputs Max. Conversion rate Min. Conversion rate 80 20 MsPs MsPs Power down mode dissipation Deep sleep mode power dissipation Power dissipation with all channels in sleep channel mode (Light sleep) Power dissipation savings per channel off Digital and output driver supply 173 88 312 158 470 10 56 116 44 mA mA mW mW mW µW mW mW mW signal applied to 7 channels (FIn0). Measurement taken on one channel with full scale at FIn1. FIn1=8MHz, FIn0=9.9MHz 11.3 11.3 95 bits bits dBc 75 77 76 dBc dBc 85 90 90 dBc dBc 74 77 76 dBc dBc 68 69.6 69.5 dBFs dBFs 68.5 70.1 70 dBFs dBFs Description Min typ Max Unit 0 A / D Converters - sMt 0-3 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1102 v03.0611 Octal 12-Bit 80 MSPS a/D cOnverter Digital and Switching Specifications AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, unless otherwise noted Parameter Clock Inputs Duty Cycle Compliance Input range, diff Input range, sine Input range, CMos Input common mode voltage Input capacitance Logic inputs (CMOS) vHI vHI vLI vLI IHI ILI CI Data outputs (LVDS) Compliance voUt vCM output coding Timing Characteristics Aperture delay Aperture jitter start up time from Power Down Mode and Deep sleep Mode to Active Mode. references have reached 99% of final value. see section “Clock Frequency” start up time from Power Down Mode and Deep sleep Mode to Active Mode in µs. tsLPCH tovr tLAt LVDS Output Timing Characteristics tdata tProP LCLK to data delay time (excluding programmable phase shift) Clock propagation delay. LvDs bit-clock duty-cycle Frame clock cycle-to-cycle jitter teDGe tCLKeDGe Data rise- and fall time 20% to 80% Clock rise- and fall time 20% to 80% 0.4 0.4 7*tLvDs + 2.6 45 250 7*tLvDs + 3.5 7*tLvDs + 4.2 55 2.5 ps ns %LCLK cycle %LCLK cycle ns ns start up time from sleep Channel Mode to Active Mode out of range recovery time Pipeline delay 0.8