HMCAD1511

HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter Features • 8-bit High speed single/ Dual/ Quad ADC single Channel Mode: Fsmax = 1000 MsPs Dual Channel Mode: Fsmax = 500 MsPs Quad Channel Mode: Fsmax = 250 MsPs • Integrated Cross Point switches (Mux Array) • 1X to 50X Digital Gain no Missing Codes up to 32X • 1X Gain: 49.8 dB snr. 10X Gain: 48 dB snr • Internal Low Jitter Programmable Clock Divider • Ultra Low Power Dissipation 710 mW including I/o at 1000 MsPs • 0.5 µs start-up time from sleep, 15 µs from Power Down • Internal reference Circuitry with no external Components required • Coarse and Fine Gain Control • Digital Fine Gain Adjustment for each ADC • Internal offset Correction • 1.8v supply voltage • 1.7 - 3.6v CMos Logic on Control Interface Pins • serial LvDs/rsDs output • 7x7 mm QFn 48 (LP7D) Package typical Applications • UsB Powered oscilloscopes • Digital oscilloscopes • satellite receivers 0 A / D Converters - sMt pin compatible parts • HMCAD1511 is pin compatible with HMCAD1520 • HMCAD1511 is pin compatible and can be configured to operate as HMCAD1510, with functionality and performance as described in HMCAD1510 datasheet Functional diagram Figure 1. Functional Block Diagram F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 0-1 HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter general description the HMCAD1511 is a versatile high performance low power analog-to-digital converter (ADC), utilizing time-interleaving to increase sampling rate. Integrated Cross Point switches activate the input selected by the user. In single channel mode, one of the four inputs can be selected as a valid input to the single ADC channel. In dual channel mode, any two of the four inputs can be selected to each ADC channel. In quad channel mode, any input can be assigned to any ADC channel. An internal, low jitter and programmable clock divider makes it possible to use a single clock source for all operational modes. the HMCAD1511 is based on a proprietary structure, and employs internal reference circuitry, a serial control interface and serial LvDs/rsDs output data. Data and frame synchronization clocks are supplied for data capture at the receiver. Internal 1 to 50X digital coarse gain with enoB > 7.5 up to 16X gain, allows digital implementation of oscilloscope gain settings. Internal digital fine gain can be set separately for each ADC to calibrate for gain errors. various modes and configuration settings can be applied to the ADC through the serial control interface (sPI). each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. register settings determine the exact function of this pin. HMCAD1511 is designed to easily interface with Field Programmable Gate Arrays (FPGAs) from several vendors. 0 A / D Converters - sMt 0-2 electrical Specifications dC Specifications AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, Fs = 125 MsPs, Quad Channel Mode, 50% clock duty cycle, -1 dBFs 70 MHz input signal, 1x/0 dB digital gain (fine and coarse), unless otherwise noted Parameter DC accuracy no missing codes offset Gabs Grel DnL InL vCM,out Analog Input vCM,in Fsr Cin,Q Cin,D Cin,s Power Supply vAvDD vDvDD vovDD Temperature tA operating free-air temperature -40 85 °C Analog supply voltage Digital and output driver supply voltage Digital CMos Input supply voltage 1.7 1.7 1.7 1.8 1.8 1.8 2 2 3.6 v v v Analog input common mode voltage Differential input voltage full scale range Differential input capacitance, Quad channel mode Differential input capacitance, Dual channel mode Differential input capacitance, single channel mode vCM - 0.1 2 5 7 11 vCM +0.2 v vpp pF pF pF offset error after internal digital offset correction Gain error Gain matching between channels. ±3 sigma value at worst case conditions Differential non linearity Integral non linearity Common mode voltage output ±0.5 ±0.2 ±0.5 vAvDD/2 Guaranteed 0.05 ±6 LsB %Fs %Fs LsB LsB Description Min Typ Max Unit F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter AC Specifications AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, 50% clock duty cycle, -1 dBFs 71 MHz input signal, Gain = 1X, rsDs output data levels unless otherwise noted Parameter Performance snr signal to noise ratio, excluding interleaving spurs single Ch Mode, Fs = 1000 MsPs single Ch Mode, Fs = 1000 MsPs, FIn = 170 MHz single Ch Mode, Fs = 1000 MsPs, Gain = 10X single Ch Mode, Fs = 500 MsPs single Ch Mode, Fs = 500 MsPs, Gain = 10X Dual Ch Mode, Fs = 500 MsPs Quad Ch Mode, Fs = 250 MsPs 48.5 48.5 48.5 48.5 49.8 49.7 48.1 49.8 48.2 49.8 49.9 dBFs dBFs dBFs dBFs dBFs dBFs dBFs Description Min Typ Max Unit 0 A / D Converters - sMt sInADincl signal to noise and Distortion ratio, including interleaving spurs single Ch Mode, Fs = 1000 MsPs Dual Ch Mode, Fs = 500 MsPs Quad Ch Mode, Fs = 250 MsPs 45.7 44 49.2 dBFs dBFs dBFs sInADexcl signal to noise and Distortion ratio, excluding interleaving spurs single Ch Mode, Fs = 1000 MsPs single Ch Mode, Fs = 1000 MsPs, FIn = 170 MHz single Ch Mode, Fs = 1000 MsPs, Gain = 10X single Ch Mode, Fs = 500 MsPs single Ch Mode, Fs = 500 MsPs, Gain = 10X Dual Ch Mode, Fs = 500 MsPs Quad Ch Mode, Fs = 250 MsPs 48 48 48 48 49.3 46.5 47.5 49.4 47.7 49 49.3 49 44 57 55 64 63 62 56 55 58 60 65 65 63 70 65 65 63 60 57 50 65 65 63 70 7.9 7.4 7.6 7.9 7.6 7.8 7.9 dBFs dBFs dBFs dBFs dBFs dBFs dBFs dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc bits bits bits bits bits bits bits sFDrincl spurious Free Dynamic range, including interleaving spurs single Ch Mode, Fs = 1000 MsPs Dual Ch Mode, Fs = 500 MsPs Quad Ch Mode, Fs = 250 MsPs sFDrexcl spurious Free Dynamic range, excluding interleaving spurs single Ch Mode, Fs = 1000 MsPs single Ch Mode, Fs = 1000 MsPs, FIn = 170 MHz single Ch Mode, Fs = 1000 MsPs, Gain = 10X single Ch Mode, Fs = 500 MsPs single Ch Mode, Fs = 500 MsPs, Gain = 10X Dual Ch Mode, Fs = 500 MsPs Quad Ch Mode, Fs = 250 MsPs HD2/3 Worst of HD2/HD3 single Ch Mode, Fs = 1000 MsPs single Ch Mode, Fs = 1000 MsPs, FIn = 170 MHz single Ch Mode, Fs = 1000 MsPs, Gain = 10X single Ch Mode, Fs = 500 MsPs single Ch Mode, Fs = 500 MsPs, Gain = 10X Dual Ch Mode, Fs = 500 MsPs Quad Ch Mode, Fs = 250 MsPs enoBexcl effective number of Bits, excluding interleaving spurs single Ch Mode, Fs = 1000 MsPs single Ch Mode, Fs = 1000 MsPs, FIn = 170 MHz single Ch Mode, Fs = 1000 MsPs, Gain = 10X single Ch Mode, Fs = 500 MsPs single Ch Mode, Fs = 500 MsPs, Gain = 10X Dual Ch Mode, Fs = 500 MsPs Quad Ch Mode, Fs = 250 MsPs 0-3 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter AC Specifications AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, 50% clock duty cycle, -1 dBFs 71 MHz input signal, Gain = 1X, rsDs output data levels unless otherwise noted Parameter Xtlk,2 Description Crosstalk Dual Ch Mode. signal applied to 1 channel (FIn0). Measurement taken on one channel with full scale at FIn1. FIn1 = 71 MHz, FIn0 = 70 MHz Crosstalk Quad Ch Mode. signal applied to 1 channel (FIn0). Measurement taken on one channel with full scale at FIn1. FIn1 = 71 MHz, FIn0 = 70 MHz single Ch: Fs = 1 GsPs, Dual Ch: Fs = 500 MsPs, Quad Ch: Fs = 250 MsPs. Analog supply Current Digital and output driver supply Current Analog Power Digital Power total Power Dissipation Power Down Mode dissipation Deep sleep Mode power dissipation Power dissipation with all channels in sleep channel mode (Light sleep) Power dissipation savings per channel off (Quad Channel mode) Full Power Bandwidth Max. Conversion rate in Modes: single Ch Dual Ch / Quad Ch Min. Conversion rate in Modes: single Ch Dual Ch / Quad Ch 1000 / 500 / 250 120 / 60 / 30 270 125 486 224 710 15 72 153 139 mA mA mW mW mW µW mW mW mW Min Typ 65 Max Unit dBc Xtlk,4 Power Supply IAvDD IDvDD PAvDD PDvDD Ptot PPD PsLP PsLPCH PsLPCH_sAv Analog Input FPBW Clock Inputs Fsmax 70 dBc 0 A / D Converters - sMt 0-4 650 MHz MsPs Fsmin MsPs digital and Switching Specifications AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, rsDs output data levels, unless otherwise noted Parameter Clock Inputs DC Compliance vCK,sine vCK,CMos vCM,CK CCK Logic inputs (CMOS) vHI vHI vLI vLI IHI ILI CI Data Outputs Compliance LvDs / rsDs High Level Input voltage. vovDD ≥ 3.0v High Level Input voltage. vovDD = 1.7v – 3.0v Low Level Input voltage. vovDD ≥ 3.0v Low Level Input voltage. vovDD = 1.7v – 3.0v High Level Input leakage Current Low Level Input leakage Current Input Capacitance 3 2 0.8 ·vovDD 0 0 0.8 0.2 ·vovDD +/-10 +/-10 v v v v µA µA pF Duty Cycle LvDs supported up to 700 MHz Differential input voltage swing, sine wave clock input voltage input range CMos (CLKn connected to ground) Input common mode voltage. Keep voltages within ground and voltage of ovDD Differential Input capacitance 0.3 3 45 1500 vovDD vovDD -0.3 v pF 55 % high mvpp LvPeCL, sine wave, CMos, LvDs Description Min Typ Max Unit F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter digital and Switching Specifications AvDD = 1.8v, DvDD = 1.8v, ovDD = 1.8v, rsDs output data levels, unless otherwise noted Parameter voUt voUt vCM output coding Timing Characteristics tA tj tskew tsU Aperture delay Aperture jitter, one bit set to ‘1’ in jitter_ctrl timing skew between ADC channels start up time from Power Down Mode and Deep sleep Mode to Active Mode in µs. see section “Clock Frequency” for details. start up time from sleep Channel Mode to Active Mode out of range recovery time Pipeline delay, Quad Channel Mode Pipeline delay, Dual Channel Mode Pipeline delay, single Channel Mode LCLK to data delay time (excluding programmable phase shift) Clock propagation delay. LvDs bit-clock duty-cycle Frame clock cycle-to-cycle jitter teDGe tCLKeDGe Data rise- and fall time 20% to 80% Clock rise- and fall time 20% to 80% 0.7 0.7 6*tLvDs +2.2 45 1 32 64 128 50 7*tLvDs +3.5 7*tLvDs +5.0 55 2.5 1.5 160 2.5 15 ns fsrms psrms µs µs clock cycles clock cycles clock cycles clock cycles ps ns % LCLK cycle % LCLK cycle ns ns Description Differential output voltage, LvDs Differential output voltage, rsDs output common mode voltage Default/optional Min Typ 350 150 1.2 offset Binary/ 2’s complement Max Unit mv mv v 0 A / D Converters - sMt tsLPCH tovr tLAtHsMQ tLAtHsMD tLAtHsMs tdata tProP LVDS Output Timing Characteristics table 1: Maximum voltage ratings Pin AvDD DvDD ovDD Avss / Dvss Analog inputs and outputs CLKx LvDs outputs Digital inputs Reference pin Avss Dvss Avss Dvss / Avss Avss Avss Dvss Dvss Rating -0.3v to +2.3v -0.3v to +2.3v -0.3v to +3.9v -0.3v to +0.3v -0.3v to +2.3v -0.3v to +3.9v -0.3v to +2.3v -0.3v to +3.9v table 2: Maximum temperature ratings operating temperature storage temperature Maximum Junction temperature thermal resistance (rth) soldering Profile Qualification esD sensivity HBM esD sensivity CDM -40 to +85 °C -60 to +150 °C 110 °C 29 °C/W J-stD-020 Class 1C Class III Applying voltages to the pins beyond those specified in table 1 could cause permanent damage to the circuit. eLeCtrostAtIC sensItIve DevICe oBserve HAnDLInG PreCAUtIons stresses above those listed under Absolute Maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 0-5 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter pin Configuration and description 0 A / D Converters - sMt 0-6 Figure 2: Package diagram table 3: pin descriptions Pin Name AvDD Csn sDAtA sCLK resetn PD DvDD Dvss DP1A Dn1A DP1B Dn1B DP2A Dn2A DP2B Dn2B LCLKP LCLKn Description Analog power supply, 1.8v Chip select enable. Active low serial data input serial clock input reset sPI interface. Active low Power-down input. Activate after applying power in order to initialize the ADC correctly. Alternatively use the sPI power down feature Digital and I/o power supply, 1.8v Digital ground LvDs channel 1A, positive output LvDs channel 1A, negative output LvDs channel 1B, positive output LvDs channel 1B, negative output LvDs channel 2A, positive output LvDs channel 2A, negative output LvDs channel 2B, positive output LvDs channel 2B, negative output LvDs bit clock, positive output LvDs bit clock, negative output Pin Number 1, 36 2 3 4 5 6 7, 30 8, 29 9 10 11 12 13 14 15 16 17 18 # Of Pins 2 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter table 3: pin descriptions Pin Name FCLKP FCLKn DP3A Dn3A DP3B Dn3B DP4A Dn4A DP4B Dn4B Description LvDs frame clock (1X), positive output LvDs frame clock (1X), negative output LvDs channel 3A, positive output LvDs channel 3A, negative output LvDs channel 3B, positive output LvDs channel 3B, negative output LvDs channel 4A, positive output LvDs channel 4A, negative output LvDs channel 4B, positive output LvDs channel 4B, negative output Analog ground domain 2 Analog power supply domain 2, 1.8v Digital CMos Inputs supply voltage negative differential input clock. Positive differential input clock negative differential input signal, channel 4 Positive differential input signal, channel 4 Analog ground negative differential input signal, channel 3 Positive differential input signal, channel 3 negative differential input signal, channel 2 Positive differential input signal, channel 2 negative differential input signal, channel 1 Positive differential input signal, channel 1 Common mode output pin, 0.5*AvDD Pin Number 19 20 21 22 23 24 25 26 27 28 31 32 33 34 35 37 38 39, 42, 45 40 41 43 44 46 47 48 # Of Pins 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 1 0 A / D Converters - sMt Avss2 AvDD2 ovDD CLKn CLKP In4 IP4 Avss In3 IP3 In2 IP2 In1 IP1 vCM 0-7 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter Start up initialization As part of the HMCAD1511 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. Make sure that the supply voltages are properly settled before the start up initialization is being performed. reset can be done in one of two ways: 1. By applying a low-going pulse (minimum 20 ns) on the resetn pin (asynchronous). 2. By using the serial interface to set the ‘rst’ bit high. Internal registers are reset to default values when this bit is set. the ‘rst’ bit is self-reset to zero. When using this method, do not apply any low-going pulse on the resetn pin. Power down cycling can be done in one of two ways: 1. By applying a high-going pulse (minimum 20 ns) on the PD pin (asynchronous). 2. By cycling the ‘pd’ bit in register 0Fhex to high (reg value ‘0200’hex) and then low (reg value ‘0000’hex). Serial interface the HMCAD1511 configuration registers can be accessed through a serial interface formed by the pins sDAtA (serial interface data), sCLK (serial interface clock) and Csn (chip select, active low). the following occurs when Csn is set low: • Serial data are shifted into the chip • At every rising edge of SCLK, the value present at SDATA is latched • SDATA is loaded into the register every 24th rising edge of SCLK Multiples of 24-bit words data can be loaded within a single active Csn pulse. If more than 24 bits are loaded into sDAtA during one active Csn pulse, only the first 24 bits are kept. the excess bits are ignored. every 24-bit word is divided into two parts: • The first eight bits form the register address • The remaining 16 bits form the register data Acceptable sCLK frequencies are from 20MHz down to a few hertz. Duty-cycle does not have to be tightly controlled. 0 A / D Converters - sMt 0-8 timing diagram Figure 4 shows the timing of the serial port interface. table 4 explains the timing variables used in figure 4. tcs thi tlo A5 A4 A3 A2 A1 A0 CSN SCLK SDATA A7 tck ts th D8 D7 D6 D5 D4 D3 D2 tch tchi A6 D15 D14 D13 D12 D11 D10 D9 D1 D0 Figure 3: serial Port Interface timing table 4: Serial port interface timing definitions Parameter tcs tch thi tlo tck ts th Description setup time between Csn and sCLK Hold time between Csn and sCLK sCLK high time sCLK low time sCLK period Data setup time Data hold time Minimum value 8 8 20 20 50 5 5 Unit ns ns ns ns ns ns ns F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter timing diagrams N+31 Analog input N+32 N+33 N+34 Input clock LCLKP LCLKN FCLKP FCLKN TLVDS N+35 0 A / D Converters - sMt DxnA DxnB D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 N-4 N-4 N-4 N-4 N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N D1 N D2 N D3 N D4 N D5 N D6 N D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-3 N-3 N-3 N-3 N-3 N-3 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 TPROP Figure 4: Quad channel - LvDs timing 8-bit output N+62 Analog input N+63 N+64 N+65 N+66 N+67 N+68 N+70 N+69 Input clock LCLKP LCLKN FCLKP FCLKN Dx1A / Dx3A Dx1B / Dx3B Dx2A / Dx4A Dx2B / Dx4B TLVDS D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 N-8 N-8 N-8 N-8 N-8 N-8 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N D1 N D2 N D3 N D4 N D5 N D6 N D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-7 N-7 N-7 N-7 N-7 N-7 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N+1 N+1 N+1 N+1 N+1 N+1 N+1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-6 N-6 N-6 N-6 N-6 N-6 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-5 N-5 N-5 N-5 N-5 N-5 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+3 N+3 N+3 N+3 N+3 N+3 N+3 TPROP Figure 5: Dual channel - LvDs timing 8-bit output 0-9 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter N+124 N+126 N+128 Analog input N+130 N+132 N+134 N+136 N+138 N+140 Input clock LCLKP LCLKN FCLKP FCLKN Dx1A Dx1B Dx2A Dx2B Dx3A Dx3B Dx4A Dx4B TLVDS D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 N-16 N-16 N-16 N-16 N-16 N-16 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N-8 N D1 N D2 N D3 N D4 N D5 N D6 N D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-15 N-15 N-15 N-15 N-15 N-15 N-7 N-7 N-7 N-7 N-7 N-7 N-7 N-7 N+1 N+1 N+1 N+1 N+1 N+1 N+1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-14 N-14 N-14 N-14 N-14 N-14 N-6 N-6 N-6 N-6 N-6 N-6 N-6 N-6 N+2 N+2 N+2 N+2 N+2 N+2 N+2 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-13 N-13 N-13 N-13 N-13 N-13 N-5 N-5 N-5 N-5 N-5 N-5 N-5 N-5 N+3 N+3 N+3 N+3 N+3 N+3 N+3 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-12 N-12 N-12 N-12 N-12 N-12 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N-4 N+4 N+4 N+4 N+4 N+4 N+4 N+4 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-11 N-11 N-11 N-11 N-11 N-11 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N-3 N+5 N+5 N+5 N+5 N+5 N+5 N+5 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-10 N-10 N-10 N-10 N-10 N-10 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N+6 N+6 N+6 N+6 N+6 N+6 N+6 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 N-9 N-9 N-9 N-9 N-9 N-9 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N-1 N+7 N+7 N+7 N+7 N+7 N+7 N+7 0 A / D Converters - sMt 0 - 10 TPROP Figure 6: single channel - LvDs timing 8-bit output TLVDS LCLKP LCLKN Dxxx TLVDS /2 tdata Figure 7: LvDs data timing F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter register Map Summary table 5: register Map Name rst * sleep4_ch sleep2_ch sleep1_ch1 sleep pd pd_pin_cfg ilvds_lclk ilvds_frame Description self-clearing software reset. Channel-specific sleep mode for a Quad Channel setup. Channel-specific sleep mode for a Dual Channel setup. Channel-specific sleep mode for a single Channel setup. Go to sleep-mode. Go to power-down. Configures the PD pin function. LvDs current drive programmability for LCLKP and LCLKn pins. LvDs current drive programmability for FCLKP and FCLKn pins. LvDs current drive programmability for output data pins. enables internal termination for LvDs buffers. Programmable termination for LCLKn and LCLKP buffers. Programmable termination for FCLKn and FCLKP buffers. Programmable termination for output data buffers. Channel specific swapping of the analog input signal for a Quad Channel setup. Channel specific swapping of the analog input signal for a Dual Channel setup. Channel specific swapping of the analog input signal for a single Channel setup. enables a repeating full-scale ramp pattern on the outputs. enable the mode wherein the output toggles between two defined codes. enables the mode wherein the output is a constant specified code. Bits for the single custom pattern and for the first code of the dual custom pattern. Bits for the second code of the dual custom pattern. Programmable coarse gain channel 1 in a Quad Channel setup. Programmable coarse gain channel 2 in a Quad Channel setup. Programmable coarse gain channel 3 in a Quad Channel setup. Programmable coarse gain channel 4 in a Quad Channel setup. Default Inactive Inactive Inactive Inactive Inactive Inactive PD pin configured for power-down mode 3.5 mA drive 3.5 mA drive 3.5 mA drive termination disabled termination disabled termination disabled termination disabled IPx is positive input IPx is positive input IPx is positive input Inactive X 1 1 1 X X X X X X X X X 0x12 X X X X X X X X X X X X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X Hex Address 0x00 0x0F 0 A / D Converters - sMt X X X 0x11 ilvds_dat en_lvds_ term term_lclk term_frame term_dat invert4_ch invert2_ch X X X X X X 0x24 invert1_ch1 X en_ramp dual_ custom_pat single_ custom_pat bits_custom1 bits_custom2 cgain4_ch1 cgain4_ch2 cgain4_ch3 cgain4_ch4 X 0 0 Inactive 0 X 0 0x25 Inactive 0 0 X 0x00 X X X X X X X X 0x26 0x00 1x gain 1x gain 1x gain 1x gain X X X X X X X X X X X X X X X X 0x27 0x2A X X X X X X X X 0 - 11 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter table 5: register Map Name cgain2_ch1 cgain2_ch2 cgain1_ch1 jitter_ctrl channel_ num * clk_divide * coarse_ gain_cfg fine_gain_en fgain_ branch1 fgain_ branch2 fgain_ branch3 fgain_ branch4 fgain_ branch5 fgain_ branch6 fgain_ branch7 fgain_ branch8 inp_sel_adc1 inp_sel_adc2 inp_sel_adc3 inp_sel_ adc4 phase_ddr pat_deskew pat_sync btc_mode msb_first adc_curr ext_vcm_bc lvds_pd_ mode Description Programmable coarse gain channel 1 in a Dual Channel setup. Programmable coarse gain channel 2 in a Dual Channel setup. Programmable coarse gain channel 1 in a single Channel setup. Clock jitter adjustment. set number of channels: 1, 2 or 4 channels. Define clock divider factor: 1, 2, 4 or 8 Configures the coarse gain setting enable use of fine gain. Programmable fine gain for branch1. Default 1x gain 1x gain 1x gain 160 fsrms 4 channels Divide by 1 x-gain enabled Disabled 0dB gain X X X X X X X X X X X 0x33 X X X X X X X X X X X X X X X 0x31 0x30 X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 X D2 D1 D0 X X X 0x2B Hex Address 0 A / D Converters - sMt 0 - 12 0x34 Programmable fine gain for branch 2. 0dB gain X X X X X X X Programmable fine gain for branch 3. 0dB gain X X X X X X X 0x35 Programmable fine gain for branch 4. 0dB gain X X X X X X X Programmable fine gain for branch 5. 0dB gain X X X X X X X 0x36 Programmable fine gain for branch 6. 0dB gain X X X X X X X Programmable fine gain for branch 7. 0dB gain X X X X X X X 0x37 Programmable fine gain for branch 8. 0dB gain signal input: IP1/In1 signal input: IP2/ In2 signal input: IP3/ In3 signal input: IP4/ In4 90 degrees Inactive Inactive straight offset binary LsB first nominal nominal High z-mode X X X X X X X Input select for adc 1. Input select for adc 2. Input select for adc 3. Input select for adc 4. Controls the phase of the LCLK output relative to data. enable deskew pattern mode. enable sync pattern mode. Binary two’s complement format for ADC output data. serialized ADC output data comes out with MsB first. ADC current scaling. vCM buffer driving strength control. Controls LvDs power down mode X X X X X 0 X X X X X 0 X X X X X 0 0x3A X X X 0 0x3B 0x42 0 X X 0x46 X X X X 0x50 X 0x45 0 X X X 0x52 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter table 5: register Map Name low_clk_ freq * lvds_ advance lvds_delay fs_cntrl startup_ctrl * Description Low clock frequency used. Advance LvDs data bits and frame clock by one clock cycle Delay LvDs data bits and frame clock by one clock cycle Fine adjust ADC full scale range Controls start-up time. Default Inactive Inactive Inactive 0% change ‘000’ 0 X X X 0 X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 X D2 D1 D0 0 0 0 X X 0 0 0 X X 0 0 0 X X 0x55 0x56 0x53 Hex Address Undefined register addresses must not be written to; incorrect behavior may be the result. 0 A / D Converters - sMt Unused register bits (blank table cells) must be set to ‘0’ when programming the registers. All registers can be written to while the chip is in power down mode. * these registers require a power down cycle when written to (see start up Initialization). register description Software reset Name rst Description self-clearing software reset. Default Inactive D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Hex Address 0x00 setting the rst register bit to ‘1’, restores the default value of all the internal registers including the rst register bit itself. Modes of operation and Clock divide Factor Name channel_ num clk_divide Description set number of channels: 1, 2 or 4 channels. Define clock divider factor: 1, 2, 4 or 8 Default 4 channels Divide by 1 X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X 0x31 Hex Address the HMCAD1511 has three main operating modes controlled by the register bits channel_num as defined in table 6. Power down mode, as described in section ‘startup Initialization’, must be activated after or during a change of operating mode to ensure correct operation. All active operating modes utilize interleaving to achieve high sampling speed. Quad channel mode interleaves 2 ADC branches, dual channel mode interleaves 4 ADC branches, while single channel mode interleave all 8 ADC branches. table 6: Modes of operation channel_num 0 0 0 1 1 0 Mode of operation single channel Dual channel Description single channel by interleaving ADC1 to ADC4 Dual channel where channel 1 is made by interleaving ADC1 and ADC2, channel 2 by interleaving ADC3 and ADC4 Quad channel where channel 1 corresponds to ADC1, channel2 to ADC2, channel3 to ADC3 and channel 4 to ADC4 1 0 0 Quad channel only one of the 3bits should be activated at the same time. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 13 HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter clk_divide allows the user to apply an input clock frequency higher than the sampling rate. the clock divider will divide the input clock frequency by a factor of 1, 2, 4, or 8, defined by the clk_divide register. By setting the clk_divide value relative to the channel_num value, the same input clock frequency can be used for all settings on number of channels. e.g: When increasing the number of channels from 1 to 4, the maximum sampling rate is reduced by a factor of 4. By letting clk_divide follow the channel_num value, and change it from 1 to 4, the internal clock divider will provide the reduction of the sampling rate without changing the input clock frequency. table 7: Clock divider Factor clk_divide 00 (default) 01 10 11 Clock Divider Factor 1 2 4 8 Sampling rate (FS) Input clock frequency / 1 Input clock frequency / 2 Input clock frequency / 4 Input clock frequency / 8 input Select Name inp_sel_adc1 inp_sel_adc2 inp_sel_adc3 inp_sel_adc4 Description Input select for adc 1. Input select for adc 2. Input select for adc 3. Input select for adc 4. Default signal input: IP1/In1 signal input: IP2/In2 signal input: IP3/In3 signal input: IP4/In4 X X X X 0 X X X X 0 X X X X 0 0x3B D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 X D3 X D2 X D1 X D0 0 0x3A Hex Address 0 A / D Converters - sMt 0 - 14 each ADC is connected to the four input signals via a full flexible cross point switch, set up by inp_sel_adcx. In single channel mode, any one of the four inputs can be selected as valid input to the single ADC channel. In dual channel mode, any two of the four inputs can be selected to each ADC channel. In quad channel mode any input can be assigned to any ADC channel. the switching of inputs can be done during normal operation, and no additional actions are needed. the switching will occur instantaneously at the end of each sPI command. table 8: Select inp_sel_adcx 0001 0 0010 0 0100 0 1000 0 other Selected Input IP1/In1 IP2/In2 IP3/In3 IP4/In4 Do not use F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter inp_sel_adc1 IP1 / IN1 inp_sel_adc2 IP2 / IN2 inp_sel_adc3 IP3 / IN3 inp_sel_adc4 IP4 / IN4 ADC 1 ADC 2 ADC 3 Cross Point Switch (Analog Mux) ADC 4 0 A / D Converters - sMt Full-Scale Control Name fs_cntrl Description Figure 8: ADC input signals through Cross Point switch Default 0% change D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 X D4 X D3 X D2 D1 D0 X X X Hex Address 0x55 Fine adjust ADC full scale range the full-scale voltage range of HMCAD1511 can be adjusted using an internal 6-bit DAC controlled by the fs_cntrl register. Changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. this leads to a maximum range of ±10% adjustment. table 9 shows how the register settings correspond to the full-scale range. note that the values for full-scale range adjustment are approximate. the DAC is, however, guaranteed to be monotonous. the full-scale control and the programmable gain features differ in two major ways: 1. the full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2. the programmable gain feature has much coarser gain steps and larger range than the full-scale control. table 9: register values with Corresponding Change in Full-Scale range fs_cntrl 111111 111110 100001 100000 011111 000001 000000 Full-Scale Range Adjustment 9.70% 9.40% 0.30% 0% -0.3% -9.7% -10% 0 - 15 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter Current Control Name adc_curr ext_vcm_bc Description ADC current scaling. vCM buffer driving strength control. Default nominal nominal X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X Hex Address 0x50 there are two registers that impact performance and power dissipation. the adc_curr register scales the current consumption in the ADC core. the performance is guaranteed at the nominal setting. Lower power consumption can be achieved by reducing the adc_curr value, see table 10. the impact on performance is low for settings down to minimum, but will depend on the ADC sampling rate. table 10: AdC Current Control Settings adc_curr 100 101 110 111 000 (default) 001 010 011 ADC Core Current -40% (lower performance) -30% -20% -10% nominal Do not use Do not use Do not use 0 A / D Converters - sMt 0 - 16 the ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the vCM pin. If this pin is not in use, the buffer can be switched off. If current is drawn from the vCM pin, the driving strength can be increased to keep the voltage on this pin at the correct level. table 11: external Common Mode voltage Buffer driving Strength ext_vcm_bc 00 01 (default) 10 11 VCM buffer driving strength (µA) Max current sinked/sourced from vCM pin with < 20 mv voltage change. off (vCM floating) ±20 ±400 ±700 Start-up and Clock Jitter Control Name startup_ctrl jitter_ctrl Description Controls start-up time. Clock jitter adjustment. Default '000' 160 fsrms X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 X X D1 X X D0 X X Hex Address 0x56 0x30 to optimize start up time, a register is provided where the start-up time in number of clock cycles can be set. some internal circuitry have start up times that are clock frequency independent. Default counter values are set to accommodate these start up times at the maximum clock frequency (sampling rate). this will lead to increased start up times at low clock frequencies. setting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better fit the actual start up time, such that the start up time will be reduced. the start up times from power down and sleep modes are changed by this register setting. If the clock divider is used (set to other than 1), the input clock frequency must be divided by the divider factor to find the correct clock frequency range (see table 7). F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter table 12: Start-up time Control Settings Quad Channel startup_ctrl 100 000 001 101 011 other Clock Frequency Range (MSPS) 160 - 250 100 - 160 65 - 100 40 - 65 30 - 40 Do not use Single Channel Startup Delay (clock cycles) 3072 1984 1280 840 520 Startup Delay (µs) 12.3 - 19.2 12.4 - 19.8 12.8 - 19.7 12.9 - 21 13 - 17.3 startup_ctrl 100 000 001 101 011 other Dual Channel Clock Frequency Range (MSPS) 320 - 500 200 - 320 130 – 200 80 - 130 60 – 80 Do not use Startup Delay (clock cycles) 6144 3968 2560 1680 1040 Startup Delay (µs) 12.3 - 19.2 12.4 - 19.8 12.8 - 19.7 12.9 - 21 13 - 17.3 - 0 A / D Converters - sMt startup_ctrl 100 000 001 101 011 other Clock frequency range (MSPS) 640 - 1000 400 - 640 260 - 400 160 - 260 120 - 160 Do not use Startup Delay (clock cycles) 12288 7936 5120 3360 2080 - Startup delay (µs) 12.3 - 19.2 12.4 - 19.8 12.8 - 19.7 12.9 - 21 13 - 17.3 - jitter_ctrl allows the user to set a trade-off between power consumption and clock jitter. If all bits in the register is set low, the clock signal is stopped. the clock jitter depends on the number of bits set to ‘1’ in the jitter_ctrl register. Which bits are set high does not affect the result. table 13: Clock Jitter performance Number of bits to '1' in jitter_ctrl 1 2 3 4 5 6 7 8 0 Clock Jitter Performance (fsrms) 160 150 136 130 126 124 122 120 Clock stopped Module Current Consumption (mA) 1 2 3 4 5 6 7 8 0 - 17 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter lvdS output Configuration and Control Name low_clk_freq lvds_advance Description Low clock frequency used. Advance LvDs data bits and frame clock by one clock cycle Delay LvDs data bits and frame clock by one clock cycle Controls the phase of the LCLK output relative to data. Binary two's complement format for ADC output data. serialized ADC output data comes out with MsB first. Default Inactive Inactive 0 X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 X D2 0 0 D1 0 0 D0 0 0 Hex Address 0x53 lvds_delay Inactive X 0 0 0 0 phase_ddr btc_mode msb_first 90 degrees straight offset binary LsB first X X X 0x42 0x46 X the HMCAD1511 uses an 8-bit serial LvDs output interface as shown in the timing Diagrams section. the different selection of number of channels uses the LvDs outputs as defined by table 14. 0 A / D Converters - sMt 0 - 18 table 14: use of lvdS outputs Channel Set-Up single channel Dual channel, channel 1 Dual channel, channel 2 Quad channel, channel 1 Quad channel, channel 2 Quad channel, channel 3 Quad channel, channel 4 LVDS Outputs Used D1A, D1B, D2A, D2B, D3A, D3B, D4A, D4B D1A, D1B, D2A, D2B D3A, D3B, D4A, D4B D1A, D1B D2A, D2B D3A, D3B D4A, D4B Maximum data output bit-rate for HMCAD1511 is 1 Gb/s. the maximum sampling rate for the different configurations is given by table 15. the sampling rate is set by the frequency of the input clock (Fs). the frame-rate, i.e. the frequency of the FCLK signal on the LvDs outputs, depends on the selected mode and the sampling frequency (Fs) as defined in table 16. table 15: Maximum Sampling rate for different HMCAd1511 Configurations Product HMCAD1511 Single Channel (MSPS) 1000 Dual Channel (MSPS) 500 Quad Channel (MSPS) 250 table 16: output data Frame rate Mode of Operation single channel Dual channel Quad channel Frame-Rate (FCLK Frequency) Fs / 8 Fs / 4 Fs / 2 If the HMCAD1511 device is used at a low sampling rate the register bit low_clk_freq has to be set to ‘1’. see table 17 for when to use this register bit for the different modes of operation. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter table 17: use of register Bit low_clk_freq Mode of Operation single channel Dual channel Quad channel Limit When low_clk_freq Should Be Activated Fs < 240 MHz Fs < 120 MHz Fs < 60 MHz to ease timing in the receiver when using multiple HMCAD1511, the device has the option to adjust the timing of the output data and the frame clock. the propagation delay with respect to the ADC input clock can be moved one LvDs clock cycle forward or backward, by using lvds_delay and lvds_advance, respectively. see figure 10 for details. note that LCLK is not affected by lvds_delay or lvds_advance settings. Input clock LCLKP LCLKN 0 A / D Converters - sMt default: TLVDS TPROP FCLKN FCLKP Dxxx D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N D1 N D2 N D3 N D4 N D5 N D6 N TPROP lvds_delay = '1': FCLKP FCLKN Dxxx D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 N-4 N-4 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 TLVDS D0 N D1 N D2 N D3 N D4 N D5 N TPROP TLVDS lvds_advance = '1': FCLKP FCLKN Dxxx D0 D1 D2 D3 D4 D5 D6 D7 D0 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N-2 N D1 N D2 N D3 N D4 N D5 N D6 N D7 N Figure 9: LvDs output timing adjustment the LvDs output interface of HMCAD1511 is a DDr interface. the default setting is with the LCLK rising and falling edge transitions in the middle of alternate data windows. the phase for LCLK can be programmed relative to the output frame clock and data bits using phase_ddr. the LCLK phase modes are shown in figure 11. the default timing is identical to setting phase_ddr=’10’. 0 - 19 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter PHASE_DDR='00' (270 deg) FCLKN FCLKP LCLKP LCLKN Dxx PHASE_DDR='10' (90 deg) FCLKN FCLKP LCLKN LCLKP Dxx PHASE_DDR='01' (180 deg) FCLKN FCLKP LCLKN LCLKP Dxx PHASE_DDR='11' (0 deg) FCLKN FCLKP LCLKP LCLKN Dxx Figure 10: Phase programmability modes for LCLK the default data output format is offset binary. two’s complement mode can be selected by setting the btc_mode bit to ‘1’ which inverts the MsB. the first bit of the frame (following the rising edge of FCLKP) is the LsB of the ADC output for default settings. Programming the msb_first mode results in reverse bit order, and the MsB is output as the first bit following the FCLKP rising edge. 0 A / D Converters - sMt 0 - 20 lvdS drive Strength programmability Name ilvds_lclk ilvds_frame ilvds_dat Description LvDs current drive programmability for LCLKP and LCLKn pins. LvDs current drive programmability for FCLKP and FCLKn pins. LvDs current drive programmability for output data pins. Default 3.5 mA drive 3.5 mA drive 3.5 mA drive X X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 X D1 X D0 X 0x11 Hex Address the current delivered by the LvDs output drivers can be configured as shown in table 18. the default current is 3.5mA, which is what the LvDs standard specifies. to reduce power consumption in the HMCAD1511, reduced swing Data signaling (rsDs), is recommended. the output current drive setting should then be 1.5 mA. setting the ilvds_lclk register controls the current drive strength of the LvDs clock output on the LCLKP and LCLKn pins. setting the ilvds_frame register controls the current drive strength of the frame clock output on the FCLKP and FCLKn pins. setting the ilvds_dat register controls the current drive strength of the data outputs on the D[8:1]P and D[8:1]n pins. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter table 18: lvdS output drive Strength for lClK, FClK & data ilvds_* 000 001 101 011 100 101 110 111 LVDS Drive Strength 3.5 mA (default) 2.5 mA 1.5 mA (rsDs) 0.5 mA 7.5 mA 6.5 mA 5.5 mA 4.5 mA 0 A / D Converters - sMt lvdS internal termination programmability Name en_lvds_term term_lclk term_frame term_dat Description enables internal termination for LvDs buffers. Programmable termination for LCLKn and LCLKP buffers. Programmable termination for FCLKn and FCLKP buffers. Programmable termination for output data buffers. Default termination disabled termination disabled termination disabled termination disabled D15 D14 D13 D12 D11 D10 D9 X 1 1 1 X X X X X X X X X 0x12 D8 D7 D6 D5 D4 D3 D2 D1 D0 Hex Address the off-chip load on the LvDs buffers may represent a characteristic impedance that is not perfectly matched with the PCB traces. this may result in reflections back to the LvDs outputs and loss of signal integrity. this effect can be mitigated by enabling an internal termination between the positive and negative outputs of each LvDs buffer. Internal termination mode can be selected by setting the en_lvds_term bit to ‘1’. once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers can be independently programmed using sets of three bits. table 19 shows how the internal termination of the LvDs buffers are programmed. the values are typical values and can vary by up to ±20% from device to device and across temperature. table 19: lvdS output internal termination for lClK, FClK and data term_* 000 001 101 011 100 101 110 111 LVDS Internal Termination termination disabled 260Ω 150Ω 94Ω 125Ω 80Ω 66Ω 55Ω 0 - 21 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter power Mode Control Name sleep4_ch sleep2_ch sleep1_ch1 sleep pd pd_pin_cfg Description Channel-specific sleep mode for a Quad Channel setup. Channel-specific sleep mode for a Dual Channel setup. Channel-specific sleep mode for a single Channel setup. Go to sleep-mode. Go to power-down. Configures the PD pin function. Default Inactive Inactive Inactive Inactive Inactive PD pin configured for power-down mode High z-mode X X X 0x52 X X X 0x0F X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 X D2 D1 D0 X X X Hex Address lvds_pd_mode Controls LvDs power down mode setting sleep4_ch = ‘1’ sets channel in a Quad Channel setup in sleep mode. setting sleep2_ch = ‘1’ sets channel in a Dual Channel setup in sleep mode. setting sleep1_ch1 = ‘1’ sets the ADC channel in a single Channel setup in sleep mode. this is a light sleep mode with short start up time. setting sleep = ‘1’, puts all channels to sleep, but keeps FCLK and LCLK running to maintain LvDs synchronization. the start up time is the same as for complete power down. Power consumption is significantly lower than for setting all channels to sleep by using the sleep*_ch register. setting pd = ‘1’ completely powers down the chip, including the band-gap reference circuit. start-up time from this mode is significantly longer than from the sleep*_ch mode. the synchronization with the LvDs receiver is lost since LCLK and FCLK outputs are put in high-Z mode. setting pdn_pin_cfg = ‘x1’ configures the circuit to enter sleep channel mode (all channels off) when the PD pin is set high. this is equal to setting all channels to sleep by using sleep*_ch. the channels can not be powered down separately using the PD pin. setting pdn_pin_cfg = ‘10’ configures the circuit to enter (deep) sleep mode when the PD pin is set high (equal to setting sleep=’1’). When pdn_pin_cfg = ‘00’, which is the default, the circuit enters the power down mode when the PD pin is set high. the lvds_pd_mode register configures whether the LvDs data output drivers are powered down or kept alive in sleep and sleep channel modes. LCLK and FCLK drivers are not affected by this register, and are always on in sleep and sleep channel modes. If lvds_pd_mode is set low (default), the LvDs output is put in high Z mode, and the driver is completely powered down. If lvds_pd_mode is set high, the LvDs output is set to constant 0, and the driver is still on during sleep and sleep channel modes. F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com 0 - 22 A / D Converters - sMt the HMCAD1511 device has several modes for power management, from sleep modes with short start up time to full power down with extremely low power dissipation. there are two sleep modes, both with the LvDs clocks (FCLK, LCLK) running, such that the synchronization with the receiver is maintained. the first is a light sleep mode (sleep*_ ch) with short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down. 0 HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter programmable gain Name cgain_cfg fine_gain_en cgain4_ch1 cgain4_ch2 cgain4_ch3 cgain4_ch4 cgain2_ch1 Description Configures the coarse gain setting enable use of fine gain. Programmable coarse gain channel 1 in a Quad Channel setup. Programmable coarse gain channel 2 in a Quad Channel setup. Programmable coarse gain channel 3 in a Quad Channel setup. Programmable coarse gain channel 4 in a Quad Channel setup. Programmable coarse gain channel 1 in a Dual Channel setup. Programmable coarse gain channel 2 in a Dual Channel setup. Programmable coarse gain channel 1 in a 1 channel setup. Programmable fine gain for branch1. Programmable fine gain for branch 2. Programmable fine gain for branch 3. Programmable fine gain for branch 4. Programmable fine gain for branch 5. Programmable fine gain for branch 6. Programmable fine gain for branch 7. Programmable fine gain for branch 8. Default x-gain enabled Disabled 1x gain 1x gain 1x gain 1x gain 1x gain 1x gain 1x gain 0dB gain 0dB gain 0dB gain 0dB gain 0dB gain 0dB gain 0dB gain 0dB gain X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0x34 X X X X X X X X X X X X 0x2B X X X X X X X X 0x2A X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X Hex Address 0x33 0 A / D Converters - sMt cgain2_ch2 cgain1_ch1 fgain_branch1 fgain_branch2 fgain_branch3 fgain_branch4 fgain_branch5 fgain_branch6 fgain_branch7 fgain_branch8 0x35 0x36 0x37 the device includes a digital programmable gain in addition to the Full-scale control. the programmable gain of each channel can be individually set using a four bit code, indicated as cgain*. the gain is configured by the register cgain_cfg, when cgain_cfg equals ‘0’ a gain in dB steps is enabled as defined in table 20 otherwise if cgain_cfg equals ‘1’ the gain is defined by table 21. there will be no missing codes for gain settings lower than 32x (30dB), due to higher than 8 bit resolution internally. table 20: gain setting – dB Step cgain_cfg 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 cgain* 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Implemented Gain (dB) 0 1 2 3 4 5 6 7 8 9 10 11 12 not used not used not used 0 - 23 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter table 21: gain Setting – x Step cgain_cfg 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 cgain* 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Implemented Gain Factor (x) 1 1.25 2 2.5 4 5 8 10 12.5 16 20 25 32 not used not used 50 0 A / D Converters - sMt 0 - 24 there is a digital fine gain implemented for each ADC to adjust the fine gain errors between the ADCs. the gain is controlled by fgain_branch* as defined in table 22. there will be no missing codes when using digital fine gain, due to higher resolution internally. to enable the fine gain function the register bit fine_gain_en has to be activated, set to ‘1’. table 22: Fine gain Setting fgain_branchx 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Arithmetic Function oUt = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-12 + 2-13) * In oUt = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-12) * In oUt = (1 + 2-8 + 2-9 + 2-10 + 2-11 + 2-13) * In oUt = (1 + 2-8 + 2-9 + 2-10 + 2-11) * In oUt = (1 + 2-12 + 2-13) * In oUt = (1 + 2-12) * In oUt = (1 + 2-13) * In oUt = In oUt = In oUt = (1 - 2-13) * In oUt = (1 - 2-12) * In oUt = (1 - 2-12 - 2-13) * In oUt = (1 - 2-8 - 2-9 - 2-10 - 2-11) * In oUt = (1 - 2 - 2 - 2 -8 -9 -10 Implemented Gain (x) 1.0077 1.0076 1.0074 1.0073 1.0004 1.0002 1.0001 1.0000 1.0000 0.9999 0.9998 0.9996 0.9927 0.9926 0.9924 0.9923 Gain (dB) 0.0665 0.0655 0.0644 0.0634 0.0031 0.0021 0.001 0.0000 0.0000 -0.0011 -0.0021 -0.0032 -0.0639 -0.0649 -0.0660 -0.0670 -2 -11 - 2 ) * In -13 oUt = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-12) * In oUt = (1 - 2-8 - 2-9 - 2-10 - 2-11 - 2-12 - 2-13) * In F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter Analog input invert Name invert4_ch invert2_ch invert1_ch1 Description Channel specific swapping of the analog input signal for a Quad Channel setup. Channel specific swapping of the analog input signal for a Dual Channel setup. Channel specific swapping of the analog input signal for a 1 channel setup. Default IPx is positive input IPx is positive input IPx is positive input X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X 0x24 Hex Address the IPx pin represents the positive analog input pin, and Inx represents the negative (complementary) input. setting the bits marked invertx_ch (individual control for each channel) causes the inputs to be swapped. Inx would then represent the positive input, and IPx the negative input. 0 A / D Converters - sMt lvdS test patterns Name en_ramp dual_custom_pat single_custom_ pat bits_custom1 bits_custom2 pat_deskew pat_sync Description enables a repeating full-scale ramp pattern on the outputs. enable the mode wherein the output toggles between two defined codes. enables the mode wherein the output is a constant specified code. Bits for the single custom pattern and for the first code of the dual custom pattern. is the LsB. Bits for the second code of the dual custom pattern. enable deskew pattern mode. enable sync pattern mode. Default Inactive Inactive Inactive D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X 0 0 0 X 0 0 0 X 0x25 Hex Address 0x00 X X X X X X X X 0x26 0x00 Inactive Inactive X X X X X X X X 0 X X 0 0x27 0x45 to ease the LvDs synchronization setup of HMCAD1511, several test patterns can be set up on the outputs. normal ADC data are replaced by the test pattern in these modes. setting en_ramp to ‘1’ sets up a repeating full-scale ramp pattern on all data outputs. the ramp starts at code zero and is increased 1LsB every clock cycle. It returns to zero code and starts the ramp again after reaching the full-scale code. A constant value can be set up on the outputs by setting single_custom_pat to ‘1’, and programming the desired value in bits_custom1. In this mode, bits_custom1 replaces the ADC data at the output, and is controlled by LsBfirst and MsB-first modes in the same way as normal ADC data are. the device may also be made to alternate between two codes by programming dual_custom_pat to ‘1’. the two codes are the contents of bits_custom1 and bits_custom2. two preset patterns can also be selected: 1. Deskew pattern: set using pat_deskew, this mode replaces the ADC output with ‘01010101’ 2. sync pattern: set using pat_sync, the normal ADC word is replaced by a fixed ‘11110000’ word note: only one of the above patterns should be selected at the same time. 0 - 25 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter theory of operation HMCAD1511 is a multi Mode high-speed, CMos ADC, consisting of 8 ADC branches, configured in different channel modes, using interleaving to achieve high speed sampling. For all practical purposes, the device can be considered to contain 4 ADCs. Fine gain is adjusted for each of the eight branches separately. HMCAD1511 utilizes a LvDs output, described in ‘register Description, LvDs output Configuration and Control’. the clocks needed (FCLK, LCLK) for the LvDs interface are generated by an internal PLL. the HMCAD1511 operate from one clock input, which can be differential or single ended. the sampling clocks for each of the four channels are generated from the clock input using a carefully matched clock buffer tree. Internal clock dividers are utilized to control the clock for each ADC during interleaving. the clock tree is controlled by the Mode of operations. HMCAD1511 uses internally generated references. the differential reference value is 1v. this results in a differential input of −1v to correspond to the zero code of the ADC, and a differential input of +1v to correspond to the full-scale code (code 255). the ADC employs a Pipeline converter architecture. each Pipeline stage feeds its output data into the digital error correction logic, ensuring excellent differential linearity and no missing codes. HMCAD1511 operates from two sets of supplies and grounds. the analog supply and ground set is identified as AvDD and Avss, while the digital set is identified by DvDD and Dvss. Interleaving Effects and Sampling Order Interleaving ADCs will generate interleaving artifacts caused by gain, offset and timing mismatch between the ADC branches. the design of HMCAD1511 has been optimized to minimize these effects. It is not possible, though, to eliminate mismatch completely, such that additional compensation may be needed, especially when using high digital gain settings. the internal digital fine gain control may be used to compensate for gain errors between the ADC branches. Due to the optimization of HMCAD1511 there is not a one-to-one correspondence between the sampling order, LvDs output order and the branch number. tables 23, 24 and 25 give an overview of the corresponding branches, LvDs outputs and sampling order for the different high speed modes. table 23: Quad Channel Mode Channel # 1 2 3 4 Sampling Order 1 2 1 2 1 2 1 2 LVDS Output D1A D1B D2A D2B D3A D3B D4A D4B Fine Gain Branch 1 2 3 4 5 6 7 8 table 24: dual Channel Mode Channel # Sampling Order 1 1 2 3 4 1 2 2 3 4 LVDS Output D1A D1B D2A D2B D3A D3B D4A D4B Fine Gain Branch 1 2 4 5 7 6 8 3 0 A / D Converters - sMt 0 - 26 table 25: Single Channel Mode Channel # Sampling Order 1 2 3 1 4 5 6 7 8 LVDS Output D1A D1B D2A D2B D3A D3B D4A D4B Fine Gain Branch 1 6 2 5 8 3 7 4 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter recommended usage Analog Input the analog input to HMCAD1511 ADC is a switched capacitor track-and-hold amplifier optimized for differential operation. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. the vCM pin provides a voltage suitable as common mode voltage reference. the internal buffer for the vCM voltage can be switched off, and driving capabilities can be changed programming the ext_vcm_bc register. Figure 12: DC coupled input the input amplifier could be inside a companion chip or it could be a dedicated amplifier. several suitable single ended to differential driver amplifiers exist in the market. the system designer should make sure the specifications of the selected amplifier is adequate for the total system, and that driving capabilities comply with HMCAD1511 input specifications. Detailed configuration and usage instructions must be found in the documentation of the selected driver, and the values given in figure 13 must be adjusted according to the recommendations for the driver. AC-Coupling 0 A / D Converters - sMt Figure 11: Input configuration Figure 12 shows a simplified drawing of the input network. the signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. A small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. A small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve performance. the resistors form a low pass filter with the capacitor, and values must therefore be determined by requirements for the application. DC-Coupling Figure 13 shows a recommended configuration for DC-coupling. note that the common mode input voltage must be controlled according to specified values. Preferably, the CM_eXt output should be used as reference to set the common mode voltage. Figure 13: transformer coupled input A signal transformer or series capacitors can be used to make an AC-coupled input network. Figure 14 shows a recommended configuration using a transformer. Make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should preferably exceed the sampling rate of the ADC several times. It is also important to minimize phase mismatch between the differential ADC inputs for good HD2 performance. this type of transformer coupled input is the preferred configuration for high frequency signals as most differential amplifiers do not have adequate performance at high frequencies. Magnetic coupling between the transformers and PCB traces may impact channel crosstalk, and must hence be taken into account during PCB layout. 0 - 27 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter If the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the ADC will also travel along this distance. If these kick-backs are not terminated properly at the source side, they are reflected and will add to the input signal at the ADC input. this could reduce the ADC performance. to avoid this effect, the source must effectively terminate the ADC kick-backs, or the traveling distance should be very short. the quality of the input clock is extremely important for high-speed, high-resolution ADCs. the contribution to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1. SNRjitter = 20 · log (2 · π · ƒIN · єt) (1) where fIn is the signal frequency, and εt is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal ADC circuitry. For applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifications) and make sure the clock distribution is well controlled. It might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. It is of utmost importance to avoid crosstalk between the ADC output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. Hence, optimum jitter performance is obtained with LvDs or LvPeCL clock with fast edges. CMos and sine wave clock inputs will result in slightly degraded jitter performance. If the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the ADC clock input. 0 A / D Converters - sMt 0 - 28 Figure 14: AC coupled input Figure 15 shows AC-coupling using capacitors. resistors from the CM_eXt output, rCM, should be used to bias the differential input signals to the correct voltage. the series capacitor, CI, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. note that start Up time from sleep Mode and Power Down Mode will be affected by this filter as the time required to charge the series capacitors is dependent on the filter cut-off frequency. Clock Input and Jitter Considerations typically high-speed ADCs use both clock edges to generate internal timing signals. In HMCAD1511 only the rising edge of the clock is used. the input clock can be supplied in a variety of formats. the clock pins are AC-coupled internally, hence a wide common mode voltage range is accepted. Differential clock sources such as LvDs, LvPeCL or differential sine wave can be utilized. LvDs/LvPeCL clock signals must be appropriately terminated as close to the ADC clock pins as possible. For CMos inputs, the CLKn pin should be connected to ground, and the CMos clock signal should be connected to CLKP. CMos input clock is not recommended above 200 MHz clock frequency. For differential sine wave clock input the amplitude must be at least ± 0.8 vpp. no additional configuration is needed to set up the clock source format. Application usage example this section gives an overview on how HMCAD1511 can be used in an application utilizing all active modes with a single clock source. the example assumes that a 1 GHz clock source is applied. A differential clock should be used, and can be generated from a single ended crystal oscillator, using a transformer or balun in conjunction with ac-coupling to convert from single ended to differential signal. Start-up Initialization the start-up sequence will be as follows: • Apply power • Apply reset (RESETN low, then high, or SPI command 0x00 0x0001) • Set power down (PD pin high or SPI command 0x0F 0x0200) F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter • Set LVDS bit clock phase (phase_ddr, register 0x42)) if other than default must be used (depends on the receiver). • Select operating mode, for instance dual channel mode, and clock divider factor (sPI command 0x31 0x0102). • Set active mode (PD pin low or SPI command 0x0F 0x0000) • Select analog inputs, for instance input 1 on channel 1 and input 3 on channel 2 (sPI commands 0x3A 0202 and 0x3B 0808) table 26: overview of operating Modes and Setup Conditions Operating Mode single channel Dual channel Quad channel Sampling Speed (MSPS) 1000 500 250 Clock Divider Factor 1 2 4 SPI command for Mode Selection and Clock Divider 0x31 0x0001 0x31 0x0102 0x31 0x0204 0 A / D Converters - sMt Change Mode When changing operational mode, power down must be activated due to internal synchronization routines. A typical mode change will then be like this: • Set power down (PD pin high or SPI command 0x0F 0x0200) • Change mode to for example Single channel mode (sPI command 0x31 0x0001) • Set active mode (PD pin low or SPI command 0x0F 0x0000) • Select analog inputs, for instance Input 1 (SPI commands 0x3A 0202 and 0x3B 0202) table 26 gives an overview of the operational modes in this example and the sPI commands to apply for each mode. Select Analog Input When an operational mode is selected, the analog inputs can be changed ‘on-the-fly’. to change analog input one merely have to apply the dedicated sPI commands. the change will occur instantaneously at the end of each sPI command. table 27: example of Some Analog input Selections Operating Mode single channel Dual channel Signal Input Selection IP4/In4 Ch1: IP2/In2 Ch2: IP3/In3 Ch1: IP4/In4 Quad channel Ch2: IP3/In3 Ch3: IP2/In2 Ch4: IP1/In1 0x3A 1008, 0x3B 0402 SPI Commands 0x3A 1010, 0x3B 1010 0x3A 0404, 0x3B 0808 0 - 29 F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com HMCAD1511 v03.0711 HigH Speed Multi-Mode 8-Bit 30 MSpS to 1 gSpS A/d Converter outline drawing 0 A / D Converters - sMt 0 - 30 table 28: 7x7 mm QFn 48 pin (lp7) dimensions symbol A A1 A2 b D D2 L e F 0.2 5.15 0.3 0.18 Millimeter Min 0.8 0 typ 0.9 0.02 0.2 0.25 7.00 bsc 5.3 0.4 0.50 bsc 0.008 5.4 0.5 0.203 0.012 0.3 0.007 Max 1 0.05 Min 0.031 0 Inch typ 0.035 0.0008 0.008 0.01 0.276 bsc 0.209 0.016 0.020 bsc 0.213 0.02 0.012 Max 0.039 0.002 package information Part Number HMCAD1511 Package Body Material roHs-compliant Low stress Injection Molded Plastic Lead Finish 100% matte sn MSL [1] Level 2A Package Marking [2] HAD1511 XXXX [1] MsL, Peak temp: the moisture sensitivity level rating classified according to the JeDeC industry standard and to peak solder temperature. [2] Proprietary marking XXXX, 4-Digit lot number XXXX F or price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 978-250-3343 tel • 978-250-3373 fax • Order On-line at www.hittite.com Application Support: apps@hittite.com