BS85C20-3

厂商：
HOLTEK(合泰)
封装：
描述：
BS85C20-3 - Touch Key Flash Type 8-Bit MCU with LCD/LED Driver - Holtek Semiconductor Inc

数据手册：

下载BS85C20-3.pdf

立即购买

数据手册
价格&库存

BS85C20-3 数据手册

Touch Key Flash Type 8-Bit MCU with LCD/LED Driver BS85B12-3/BS85C20-3 Revision: V1.00 Date: February 1, 2011 Contents Table of Contents Technical Document ...........................................................................1 Features ...............................................................................................1 CPU Features ........................................................................................................1 Peripheral Features ................................................................................................1 General Description ............................................................................2 Selection Table ....................................................................................2 Block Diagram .....................................................................................2 Pin Assignment ...................................................................................3 Pin Description ....................................................................................4 BS85B12-3.............................................................................................................4 BS85C20-3.............................................................................................................7 Absolute Maximum Ratings .............................................................11 D.C. Characteristics ..........................................................................11 A.C. Characteristics ..........................................................................13 Power-on Reset Characteristics ......................................................14 Oscillator Temperature/Frequency Characteristics .......................14 System Architecture .........................................................................17 Clocking and Pipelining ........................................................................................17 Program Counter..................................................................................................18 Stack ....................................................................................................................18 Arithmetic and Logic Unit - ALU ...........................................................................19 Flash Program Memory ....................................................................21 Structure...............................................................................................................21 Special Vectors.....................................................................................................22 Look-up Table.......................................................................................................22 Table Program Example .....................................................................................22 In Circuit Programming.........................................................................................23 RAM Data Memory.............................................................................22 Structure...............................................................................................................22 i Contents Special Function Register Description ...........................................23 Indirect Addressing Registers - IAR0, IAR1..........................................................23 Memory Pointers - MP0, MP1 ..............................................................................23 Bank Pointer - BP ................................................................................................25 Accumulator - ACC ..............................................................................................26 Program Counter Low Register - PCL..................................................................26 Look-up Table Registers - TBLP, TBHP, TBLH.....................................................26 Status Register - STATUS ...................................................................................26 EEPROM Data Memory .....................................................................28 EEPROM Data Memory Structure ........................................................................28 Reading Data from the EEPROM .........................................................................30 Writing Data to the EEPROM ...............................................................................30 Write Protection ....................................................................................................30 EEPROM Interrupt ...............................................................................................30 Programming Considerations ...............................................................................31 Programming Examples .......................................................................................31 Oscillator............................................................................................32 Oscillator Overview...............................................................................................32 System Clock Configurations................................................................................32 Internal High Speed RC Oscillator - HIRC............................................................32 Internal Low Speed RC Oscillator - LIRC .............................................................33 Operating Modes and System Clocks .............................................34 System Clocks......................................................................................................34 Control Register ...................................................................................................35 System Operation Modes .....................................................................................36 Operating Mode Switching....................................................................................37 NORMAL Mode to SLOW Mode Switching...........................................................38 SLOW Mode to NORMAL Mode Switching...........................................................38 Entering the SLEEP Mode....................................................................................38 Entering the IDLE0 Mode .....................................................................................39 Entering the IDLE1 Mode .....................................................................................39 Standby Current Considerations...........................................................................39 Wake-up...............................................................................................................40 Programming Considerations ...............................................................................40 Watchdog Timer ................................................................................41 Watchdog Timer Clock Source .............................................................................41 Watchdog Timer Control Register.........................................................................41 Watchdog Timer Operation...................................................................................42 Reset and Initialisation .....................................................................43 Reset Functions ...................................................................................................43 Reset Initial Conditions .........................................................................................44 ii Contents Input/Output Ports.............................................................................49 I/O Register List....................................................................................................49 Pull-high Resistors................................................................................................50 Port A Wake-up ....................................................................................................51 I/O Port Control Register ......................................................................................51 Pin Re-mapping Functions ...................................................................................52 I/O Pin Structures .................................................................................................56 Programming Considerations ...............................................................................56 Timer Modules - TM..........................................................................57 Introduction ..........................................................................................................57 TM Operation .......................................................................................................57 TM Clock Source..................................................................................................58 TM Interrupts ........................................................................................................58 TM External Pins ..................................................................................................58 TM Input/Output Pin Control Registers .................................................................60 Programming Considerations ...............................................................................62 Compact Type TM - CTM..................................................................63 Compact TM Operation ........................................................................................63 Compact Type TM Register Description ...............................................................64 Compact Type TM Operating Modes ....................................................................67 Compare Match Output Mode ..............................................................................67 Timer/Counter Mode.............................................................................................69 PWM Output Mode...............................................................................................70 Standard Type TM - STM..................................................................72 Standard TM Operation ........................................................................................72 Standard Type TM Register Description ...............................................................73 Standard Type TM Operating Modes....................................................................77 Enhanced Type TM - ETM ................................................................84 Enhanced TM Operation ......................................................................................84 Enhanced Type TM Register Description..............................................................85 Enhanced Type TM Operating Modes ..................................................................90 Compare Output Mode .........................................................................................91 Timer/Counter Mode.............................................................................................95 PWM Output Mode...............................................................................................95 Single Pulse Output Mode ..................................................................................101 Capture Input Mode............................................................................................103 Touch Key Function ........................................................................105 Touch Key Structure ...........................................................................................105 Touch Key Register Definition.............................................................................105 Touch Key Operation ..........................................................................................110 Touch Key Interrupt.............................................................................................110 Programming Considerations .............................................................................110 iii Contents Serial Interface Module - SIM .........................................................111 SPI Interface .......................................................................................................111 I2C Interface........................................................................................................117 Peripheral Clock Output .................................................................126 Peripheral Clock Operation.................................................................................126 Interrupts..........................................................................................127 Interrupt Registers ..............................................................................................127 Interrupt Register Contents.................................................................................128 Interrupt Operation .............................................................................................134 External Interrupt ................................................................................................136 Multi-function Interrupt ........................................................................................136 Time Base Interrupts ..........................................................................................136 External Peripheral Interrupt ...............................................................................138 LVD Interrupt ......................................................................................................138 TM Interrupts ......................................................................................................138 EEPROM Interrupt .............................................................................................139 Touch Key Interrupts...........................................................................................139 SIM Interrupt.......................................................................................................139 Interrupt Wake-up Function ................................................................................139 Programming Considerations .............................................................................140 Low Voltage Detector - LVD ...........................................................140 LVD Register ......................................................................................................140 LVD Operation....................................................................................................141 LCD Driver - SCOM and SSEG Function ......................................142 LCD Operation ...................................................................................................142 LCD Bias Control................................................................................................144 LCD Driver Registers..........................................................................................144 LED Driver........................................................................................146 LED Driver Operation .........................................................................................146 LED Driver Registers..........................................................................................146 Application Circuits ........................................................................148 Instruction Set .................................................................................149 Introduction.........................................................................................................149 Instruction Timing ...............................................................................................149 Moving and Transferring Data ............................................................................149 Arithmetic Operations .........................................................................................149 Logical and Rotate Operations ...........................................................................149 Branches and Control Transfer...........................................................................149 Bit Operations.....................................................................................................149 iv Contents Table Read Operations.......................................................................................149 Other Operations................................................................................................150 Instruction Set Summary ....................................................................................151 Instruction Definition ......................................................................153 Package Information .......................................................................163 24-pin SKDIP (300mil) Outline Dimensions ........................................................163 24-pin SOP (300mil) Outline Dimensions............................................................166 24-pin SSOP (150mil) Outline Dimensions .........................................................167 28-pin SKDIP (300mil) Outline Dimensions ........................................................168 28-pin SOP (300mil) Outline Dimensions............................................................169 28-pin SSOP (150mil) Outline Dimensions .........................................................170 44-pin QFP (10mm´10mm) Outline Dimensions ................................................171 Reel Dimensions ................................................................................................172 Carrier Tape Dimensions ....................................................................................173 v BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Technical Document · Application Note HA0075E MCU Reset and Oscillator Circuits Application Note Features CPU Features · Operating Voltage: fSYS= 8MHz: VLVR~5.5V fSYS= 12MHz: 2.7V~5.5V fSYS= 16MHz: 4.5V~5.5V Power down and wake-up functions to reduce power consumption Fully integrated low and high speed internal oscillators Low speed -- 32kHz High speed -- 8MHz, 12MHz, 16MHz Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP All instructions executed in one or two instruction cycles Table read instructions 63 powerful instructions Up to 4 subroutine nesting levels Bit manipulation instruction · · · · · · · · Peripheral Features · · · · · · · · · · · · Fully integrated 12 or 20 touch key functions -- require no external components Flash Program Memory: 2K´15 or 4K´15 RAM Data Memory: 256´8 or 384´8 EEPROM Memory: 64´8 or 128´8 Watchdog Timer function Up to 38 bidirectional I/O lines Two or three Timer Modules Dual Time-Base functions for generation of fixed time interrupt signals I2C and SPI interfaces Low voltage reset function Software controlled 4´14 or 4´22 LCD driver with 1/3 bias Software controlled 6´8 or 8´14 LED driver Rev. 1.00 1 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver General Description These devices are a series of Flash Memory type 8-bit high performance RISC architecture microcontrollers with fully integrated touch key functions and LCD/LED drivers. With all touch key functions provided internally and with the convenience of Flash Memory multi-programming features, this device range has all the features to offer designers a reliable and easy means of implementing Touch Keys within their products applications. The touch key functions are fully integrated completely eliminating the need for external components. The inclusion of both LCD and LED driver functions allows for easy and cost effective solutions in applications that require to interface to these display types. In addition to the flash program memory, other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector functions coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. All devices include fully integrated low and high speed oscillators which require no external components for their implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided 2 using the internal I C and SPI interfaces, while the inclusion of flexible I/O programming features, Timer Modules and many other features further enhance device functionality and flexibility. These touch key devices will find excellent use in a huge range of modern Touch Key product applications such as instrumentation, household appliances, electronically controlled tools to name but a few. Selection Table Part No. Internal VDD Clock 8MHz VLVR~ 12MHz 5.5V 16MHz 8MHz VLVR~ 12MHz 5.5V 16MHz System Clock 8MHz~ 16MHz Program Memory Data Memory Data EEPROM I/O Timer Touch LCD Module Key Driver LED Driver SPI/ Stack 2 IC Package BS85B12-3 2K´15 256´8 64´8 22 2 12 4´14 6´8 1 4 24/28SKDIP/SOP 24/28SSOP BS85C20-3 8MHz~ 16MHz 4K´15 384´8 128´8 38 3 20 4´22 8´14 1 8 28SKDIP/SOP 28SSOP, 44QFP Block Diagram F la s h /E E P R O M P r o g r a m m in g C ir c u itr y Low V o lta g e R eset W a tc h d o g T im e r Low V o lta g e D e te c t F la s h P ro g ra m M e m o ry EEPROM D a ta M e m o ry RAM D a ta M e m o ry S ta c k 8 - b it R IS C MCU C o re In te rru p t C o n tr o lle r In te rn a l Low Speed O s c illa to r Touch K eys I/O T im e r M o d u le T B 0 /T B 1 In te rn a l H ig h S p e e d O s c illa to r Rev. 1.00 2 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Pin Assignment P C 0 /[T P 0 _ 0 ]/[S D O ]/S S E G 0 /K E Y 1 P C 1 /[T P 0 _ 1 ]/[S C K /S C L ]/S S E G 1 /K E Y 2 P C 2 /[T P 1 B _ 0 ]/[S D I/S D A ]/S S E G 2 /K E Y 3 P C 3 /[T P 1 B _ 1 ]/[S C S ]/S S E G 3 /K E Y 4 P C 4 /[T C K 0 ]/[IN T 0 ]/[T P 1 B _ 2 ]/S S E G 4 /K E Y 5 P C 5 /[T C K 1 ]/[IN T 1 ]/[T P 1 A ]/S S E G 5 /K E Y 6 P C 6 /[P C K ]/S S E G 6 /K E Y 7 P C 7 /P IN T /S S E G 7 /K E Y 8 KEY11 KEY12 VSS VDD 9 10 11 12 8 7 6 5 4 3 2 1 24 23 22 21 20 19 18 17 16 15 14 13 P B 0 /T P 0 _ 0 /S C O M 0 P B 1 /T P 0 _ 1 /S C O M 1 P B 2 /T P 1 B _ 0 /S C O M 2 P B 3 /T P 1 B _ 1 /S C O M 3 P A 1 /T C K 1 /IN T 1 /S S E G 1 0 P A 4 /T C K 0 /IN T 0 /S S E G 1 1 P A 5 /S S E G 1 2 P A 6 /S S E G 1 3 P A 3 /S C S P A 0 /S D I/S D A P A 2 /S C K /S C L P A 7 /S D O P C 0 /[T P 0 _ 0 ]/[S D O ]/S S E G 0 /K E Y 1 P C 1 /[T P 0 _ 1 ]/[S C K ]/[S C L ]/S S E G 1 /K E Y 2 P C 2 /[T P 1 B _ 0 ]/[S D I]/[S D A ]/S S E G 2 /K E Y 3 P C 3 /[T P 1 B _ 1 ]/[S C S ]/S S E G 3 /K E Y 4 P C 4 /[T C K 0 ]/[IN T 0 ]/[T P 1 B _ 2 ]/S S E G 4 /K E Y 5 P C 5 /[T C K 1 ]/[IN T 1 ]/[T P 1 A ]/S S E G 5 /K E Y 6 P C 6 /[P C K ]/S S E G 6 /K E Y 7 P C 7 /[P IN T ]/S S E G 7 /K E Y 8 KEY9 KEY10 KEY11 P C 0 /[T P 0 _ 0 ]/[S D O ]/S S E G 0 /K E Y 1 P C 1 /[T P 0 _ 1 ]/[S C K ]/[S C L ]/S S E G 1 /K E Y 2 P C 2 /[T P 1 B _ 0 ]/[S D I]/[S D A ]/S S E G 2 /K E Y 3 P C 3 /[T P 1 B _ 1 ]/[S C S ]/S S E G 3 /K E Y 4 P C 4 /[T C K 0 ]/[IN T 0 ]/[T P 1 B _ 2 ]/S S E G 4 /K E Y 5 P C 5 /[T C K 1 ]/[IN T 1 ]/[T P 1 A ]/S S E G 5 /K E Y 6 P C 6 /T C K 2 /[P C K ]/S S E G 6 /K E Y 7 P C 7 /[P IN T ]/S S E G 7 /K E Y 8 KEY9 KEY10 KEY11 KEY12 VSS VDD 9 10 11 12 13 14 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P B 0 /T P 0 _ 0 /S C O M 0 P B 1 /T P 0 _ 1 /T P 2 _ 0 /S C O M 1 P B 2 /T P 1 B _ 0 /T P 2 _ 1 /S C O M 2 P B 3 /T P 1 B _ 1 /S C O M 3 P B 4 /T P 1 B _ 2 /P C K /S S E G 8 P B 5 /P IN T /T P 1 A /S S E G 9 P A 1 /T C K 1 /IN T 1 /S S E G 1 0 P A 4 /T C K 0 /IN T 0 /S S E G 1 1 P A 5 /S S E G 1 2 P A 6 /S S E G 1 3 P A 3 /S C S P A 0 /S D I/S D A P A 2 /S C K /S C L P A 7 /S D O P P C 1 /[T P C 2 /[T P PC KEY12 VSS VDD 9 10 11 12 13 14 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P B 0 /T P 0 _ 0 /S C O M 0 P B 1 /T P 0 _ 1 /S C O M 1 P B 2 /T P 1 B _ 0 /S C O M 2 P B 3 /T P 1 B _ 1 /S C O M 3 P B 4 /T P 1 B _ 2 /P C K /S S E G 8 P B 5 /P IN T /T P 1 A /S S E G 9 P A 1 /T C K 1 /IN T 1 /S S E G 1 0 P A 4 /T C K 0 /IN T 0 /S S E G 1 1 P A 5 /S S E G 1 2 P A 6 /S S E G 1 3 P A 3 /S C S P A 0 /S D I/S D A P A 2 /S C K /S C L P A 7 /S D O B S 8 5 B 1 2 -3 2 4 S K D IP -A /S O P -A /S S O P -A B S 8 5 B 1 2 -3 2 8 S K D IP -A /S O P -A /S S O P -A C 0 /[T P 0 P 0 _ 1 ]/[S 1 B _ 0 ]/[S 3 /[T P 1 B PB2 P PE2 PE1 PB /T P 1 B _ 0 /T P 2 1 /T P 0 _ 1 /T P 2 P B 0 /T P 0 E 3 /[S C K ]/[S C /[T P 2 _ 1 ]/[S C /[T P 2 _ 0 ]/[P C P E 0 /[P IN _ 0 ]/[S D O ]/S S C K ]/[S C L ]/S S D I]/[S D A ]/S S _ 1 ]/[S C S ]/S S B S 8 5 C 2 0 -3 2 8 S K D IP -A /S O P -A /S S O P -A _ 1 /S _ 0 /S _ 0 /S L ]/S S S ]/S S K ]/S S T ]/S S EG0 EG1 EG2 EG3 C C C /K /K /K /K E E E OM OM OM G1 G1 G1 G1 EY EY EY EY 44 43 42 41403938 37 363534 1 2 3 E 3 2 1 4 7 4 5 6 1 2 0 P C 4 /[T C K 0 ]/[IN T 0 ]/[T P 1 B _ P C 5 /[T C K 1 ]/[IN T 1 ]/[T P 1 P C 6 /T C K 2 /[P C P C 7 /[P IN PD 2 ]/S A ]/S K ]/S T ]/S 0 /[T SE SE SE SE CK PD PD PD PD PD PD G 4 /K G 5 /K G 6 /K G 7 /K 2 ]/K E 1 /K E 2 /K E 3 /K E 4 /K E 5 /K E 6 /K E EY EY EY EY Y1 Y1 Y1 Y1 Y1 Y1 Y1 5 6 33 32 31 8 4 5 6 7 8 9 7 3 6 7 8 4 5 30 B S 8 5 C 2 0 -3 4 4 Q F P -A 29 28 27 26 25 24 23 9 10 11 12 131415 1617 1819 20 2122 PB3 PB4 PB5 PB6 PB7 PE4 PE5 PA1 PA4 PA5 PA6 /T P /T P /P IN /S S /S S /[S D /[S D /T C /T C /S S /S S 1 B _ 1 /S C O 1 B _ 2 /P C K T /T P 1 A /S EG 20 EG 21 I]/[S D A ]/S O ]/S S E G K 1 /IN T 1 /S K 0 /IN T 0 /S EG 12 EG 13 M3 /S S E G 8 SEG9 SEG 18 19 SEG 10 SEG 11 PA3 PA0 PA2 PA7 VDD VSS KEY KEY KEY KEY PD7 /S C /S D /S C /S D 1 1 1 9 /K 0 EY20 1 2 O I/S D A K /S C L S Note: 1. Bracketed pin names indicate non-default pinout remapping locations. 2. If the pin-shared pin functions have multiple outputs simultaneously, its pin names at the right side of the ² / ² sign can be used for higher priority. Rev. 1.00 3 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Pin Description The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. BS85B12-3 Pin Name Function PA0 PA0/SDI/SDA SDI SDA PA1 PA1/TCK1/ TCK1 INT1/SSEG10 INT1 SSEG10 PA2 PA2/SCK/SCL SCK SCL PA3 PA3/SCS SCS PA4 PA4/TCK0/ TCK0 INT0/SSEG11 INT0 SSEG11 PA5 PA5/SSEG12 SSEG12 PA6 PA6/SSEG13 SSEG13 PA7 PA7/SDO SDO PB0 PB0/TP0_0/ SCOM0 TP0_0 SCOM0 PB1 PB1/TP0_1/ SCOM1 TP0_1 SCOM1 Register Select PAWU PAPU SIMC0 SIMC0 PAWU PAPU TM1C0 INTC0 SLCDCn PAWU PAPU SIMC0 SIMC0 PAWU PAPU SIMC0 PAWU PAPU TM0C0 INTC0 SLCDCn PAWU PAPU SLCDCn PAWU PAPU SLCDCn PAWU PAPU SIMC0 PBPU TMPCn SLCDCn PBPU I/T ST ST ST ST ST ST ¾ ST ST ST ST ST ST ST ST ¾ ST ¾ ST ¾ ST ¾ ST ST ¾ ST ST ¾ O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up. ¾ SPI data input 2 NMOS I C data I/O CMOS General purpose I/O. Register enabled pull-up and wake-up. ¾ ¾ LCD Timer Module 1 input External interrupt 1 input Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI serial clock NMOS I C clock CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI slave select CMOS General purpose I/O. Register enabled pull-up and wake-up. ¾ ¾ LCD Timer Module 0 input External interrupt 0 input 2 Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up and wake-up. LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up and wake-up. LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI data output CMOS General purpose I/O. Register enabled pull-up. CMOS TM0 I/O LCD Software controlled LCD COM CMOS General purpose I/O. Register enabled pull-up. CMOS TM0 I/O LCD Software controlled LCD COM TMPCn SLCDCn Rev. 1.00 4 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Pin Name Function PB2 PB2/TP1B_0/ SCOM2 TP1B_0 SCOM2 PB3 PB3/TP1B_1/ SCOM3 TP1B_1 SCOM3 PB4 PB4/TP1B_2/ PCK/SSEG8 TP1B_2 PCK SSEG8 PB5 PB5/PINT/ TP1A/SSEG9 PINT TP1A SSEG9 PC0 PC0/TP0_0/ SDO/SSEG0/ KEY1 TP0_0 SDO SSEG0 KEY1 PC1 TP0_1 PC1/TP0_1/ SCK/SCL/ SSEG1/KEY2 SCK SCL SSEG1 KEY2 PC2 TP1B_0 PC2/TP1B_0/ SDI/SDA/ SSEG2/KEY3 SDI SDA SSEG2 KEY3 PC3 PC3/TP1B_1/ SCS/SSEG3/ KEY4 TP1B_1 SCS SSEG3 KEY4 Register Select PBPU I/T ST ST ¾ ST ST ¾ ST ST ¾ ¾ ST ST ST ¾ ST ST ¾ ¾ NS ST ST ST ST ¾ NS ST ST ST ST ¾ NS ST ST ST ¾ NS O/T Description CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O LCD Software controlled LCD COM TMPCn SLCDCn PBPU TMPCn SLCDCn PBPU TMPCn SIMC0 SLCDCn PBPU MFI3 TMPCn SLCDCn PCPU TMPCn SIMC0 SLCDCn TKMnC1 PCPU TMPCn SIMC0 SIMC0 SLCDCn TKMnC1 PCPU TMPCn SIMC0 SIMC0 SLCDCn TKMnC1 PCPU TMPCn SIMC0 SLCDCn TKMnC1 CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O LCD Software controlled LCD COM CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O CMOS Peripheral clock output LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up. ¾ Peripheral interrupt input CMOS TM1 I/O LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up. CMOS TM0 I/O CMOS SPI data output LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. CMOS TM0 I/O CMOS SPI clock NMOS I C clock LCD ¾ Software controlled LCD SEG Touch key input 2 CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O ¾ SPI data input 2 NMOS I C data I/O LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O CMOS SPI slave select LCD ¾ Software controlled LCD SEG Touch key input Rev. 1.00 5 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Pin Name Function PC4 TCK0 PC4/TCK0/ INT0 INT0/TP1B_2/ SSEG4/KEY5 TP1B_2 SSEG4 KEY5 PC5 TCK1 PC5/TCK1/ INT1/TP1A/ SSEG5/KEY6 INT1 TP1A SSEG5 KEY6 PC6 PC6/PCK/ SSEG6/KEY7 PCK SSEG6 KEY7 PC7 PC7/PINT/ SSEG7/KEY8 PINT SSEG7 KEY8 KEY9 KEY10 KEY11 KEY12 VDD VSS KEY9 KEY10 KEY11 KEY12 Register Select PCPU TM0C0 INTC0 TMPCn SLCDCn TKMnC1 PCPU TM1C0 INTC0 TMPCn SLCDCn TKMnC1 PCPU SIMC0 SLCDCn TKMnC1 PCPU MFI3 SLCDCn TKMnC1 ¾ ¾ ¾ ¾ ¾ ¾ I/T ST ST ST ST ¾ NS ST ST ST ST ¾ NS ST ¾ ¾ NS ST ST ¾ NS NS NS NS NS PWR PWR O/T Description CMOS General purpose I/O. Register enabled pull-up. ¾ ¾ Timer Module 0 input External interrupt 0 input CMOS TM1 I/O LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ ¾ Timer Module 1 input External interrupt 1 input CMOS TM1 I/O LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. CMOS Peripheral clock output LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ LCD ¾ ¾ ¾ ¾ ¾ ¾ ¾ Peripheral interrupt input Software controlled LCD SEG Touch key input Touch key input Touch key input Touch key input Touch key input Power supply Ground VDD VSS Note: I/T: Input type O/T: Output type Register Select: Indicates register which selects alternative function PWR: Power ST: Schmitt Trigger input CMOS: CMOS output NMOS: NMOS output LCD: LCD COM or SEG Vbias output NS: Non-standard input or output The pins in the table reflect that of the package with the largest number of pins. For this reason not all pins may exist on all package types. Rev. 1.00 6 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver BS85C20-3 Pin Name Function PA0 PA0/SDI/SDA SDI SDA PA1 PA1/TCK1/ INT1/SSEG10 TCK1 INT1 SSEG10 PA2 PA2/SCK/SCL SCK SCL PA3 PA3/SCS SCS PA4 PA4/TCK0/ INT0/SSEG11 TCK0 INT0 SSEG11 PA5 PA5/SSEG12 SSEG12 PA6 PA6/SSEG13 SSEG13 PA7 PA7/SDO SDO PB0 PB0/TP0_0/ SCOM0 TP0_0 SCOM0 PB1 TP0_1 PB1/TP0_1/ TP2_0/SCOM1 TP2_0 SCOM1 PB2 Register Select PAWU PAPU SIMC0 SIMC0 PAWU PAPU TM1C0 INTC0 SLCDCn PAWU PAPU SIMC0 SIMC0 PAWU PAPU SIMC0 PAWU PAPU TM0C0 INTC0 SLCDCn PAWU PAPU SLCDCn PAWU PAPU SLCDCn PAWU PAPU SIMC0 PBPU TMPCn SLCDCn PBPU I/T ST ST ST ST ST ST ¾ ST ST ST ST ST ST ST ST ¾ ST ¾ ST ¾ ST ¾ ST ST ¾ ST ST ST ¾ ST ST ST ¾ O/T Description CMOS General purpose I/O. Register enabled pull-up and wake-up. ¾ SPI data input 2 NMOS I C data I/O CMOS General purpose I/O. Register enabled pull-up and wake-up. ¾ ¾ LCD Timer Module 1 input External interrupt 1 input Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI serial clock NMOS I C clock CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI slave select CMOS General purpose I/O. Register enabled pull-up and wake-up. ¾ ¾ LCD Timer Module 0 input External interrupt 0 input 2 Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up and wake-up. LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up and wake-up. LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up and wake-up. CMOS SPI data output CMOS General purpose I/O. Register enabled pull-up. CMOS TM0 I/O LCD Software controlled LCD COM CMOS General purpose I/O. Register enabled pull-up. CMOS TM0 I/O CMOS TM2 I/O LCD Software controlled LCD COM TMPCn TMPCn SLCDCn PBPU CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O CMOS TM2 I/O LCD Software controlled LCD COM PB2/TP1B_0/ TP1B_0 TP2_1/ TP2_1 SCOM2 SCOM2 TMPCn TMPCn SLCDCn Rev. 1.00 7 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Pin Name Function PB3 PB3/TP1B_1/ SCOM3 TP1B_1 SCOM3 PB4 PB4/TP1B_2/ PCK/SSEG8 TP1B_2 PCK SSEG8 PB5 PB5/PINT/ TP1A/SSEG9 PINT TP1A SSEG9 Register Select PBPU TMPCn SLCDCn PBPU TMPCn SIMC0 SLCDCn PBPU MFI3 TMPCn SLCDCn I/T ST ST ¾ ST ST ¾ ¾ ST ST ST ¾ O/T Description CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O LCD Software controlled LCD COM CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O CMOS Peripheral clock output LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up. ¾ Peripheral interrupt input CMOS TM1 I/O LCD Software controlled LCD SEG PB6 PB6/SSEG20 SSEG20 PB7 PB7/SSEG21 SSEG21 PC0 PC0/TP0_0/ SDO/SSEG0/ KEY1 TP0_0 SDO SSEG0 KEY1 PC1 TP0_1 PC1/TP0_1/ SCK/SCL/ SSEG1/KEY2 SCK SCL SSEG1 KEY2 PC2 TP1B_0 PC2/TP1B_0/ SDI/SDA/ SSEG2/KEY3 SDI SDA SSEG2 KEY3 PC3 PC3/TP1B_1/ SCS/SSEG3/ KEY4 TP1B_1 SCS SSEG3 KEY4 PBPU SLCDCn PBPU SLCDCn PCPU TMPCn SIMC0 SLCDCn TKMnC1 PCPU TMPCn SIMC0 SIMC0 SLCDCn TKMnC1 PCPU TMPCn SIMC0 SIMC0 SLCDCn TKMnC1 PCPU TMPCn SIMC0 SLCDCn TKMnC1 ST ¾ CMOS General purpose I/O. Register enabled pull-up. LCD Software controlled LCD SEG ST ¾ ST ST ¾ ¾ NS ST ST ST ST ¾ NS ST ST ST ST ¾ NS ST ST ST ¾ NS CMOS General purpose I/O. Register enabled pull-up. LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up. CMOS TM0 I/O CMOS SPI data output LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. CMOS TM0 I/O CMOS SPI clock NMOS I C clock LCD ¾ Software controlled LCD SEG Touch key input 2 CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O ¾ SPI data input 2 NMOS I C data I/O LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. CMOS TM1 I/O CMOS SPI slave select LCD ¾ Software controlled LCD SEG Touch key input Rev. 1.00 8 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Pin Name Function PC4 TCK0 PC4/TCK0/ INT0/TP1B_2/ SSEG4/KEY5 INT0 TP1B_2 SSEG4 KEY5 PC5 TCK1 PC5/TCK1/ INT1/TP1A/ SSEG5/KEY6 INT1 TP1A SSEG5 KEY6 PC6 PC6/TCK2/ PCK/SSEG6/ KEY7 Register Select PCPU TM0C0 INTC0 TMPCn SLCDCn TKMnC1 PCPU TM1C0 INTC0 TMPCn SLCDCn TKMnC1 PCPU TM2C0 SIMC0 SLCDCn TKMnC1 PCPU MFI3 SLCDCn TKMnC1 PDPU TM2C0 TKMnC1 PDPU TKMnC1 PDPU TKMnC1 PDPU TKMnC1 PDPU TKMnC1 PDPU TKMnC1 PDPU TKMnC1 PDPU TKMnC1 I/T ST ST ST ST ¾ NS ST ST ST ST ¾ NS ST O/T Description CMOS General purpose I/O. Register enabled pull-up. ¾ ¾ Timer Module 0 input External interrupt 0 input CMOS TM1 I/O LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ ¾ Timer Module 1 input External interrupt 1 input CMOS TM1 I/O LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ Timer Module 2 input TCK2 PCK SSEG6 KEY7 PC7 ST ¾ ¾ NS ST ST ¾ NS ST CMOS Peripheral clock output LCD ¾ Software controlled LCD SEG Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ LCD ¾ Peripheral interrupt input Software controlled LCD SEG Touch key input PC7/PINT/ SSEG7/KEY8 PINT SSEG7 KEY8 PD0 CMOS General purpose I/O. Register enabled pull-up. ¾ ¾ Timer Module 2 input Touch key input PD0/TCK2/ KEY13 TCK2 KEY13 PD1 ST NS ST NS ST NS ST NS ST NS ST NS ST NS ST NS CMOS General purpose I/O. Register enabled pull-up. ¾ Touch key input PD1/KEY14 KEY14 PD2 PD2/KEY15 KEY15 PD3 PD3/KEY16 KEY16 PD4 PD4/KEY17 KEY17 PD5 PD5/KEY18 KEY18 PD6 PD6/KEY19 KEY19 PD7 PD7/KEY20 KEY20 CMOS General purpose I/O. Register enabled pull-up. ¾ Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ Touch key input CMOS General purpose I/O. Register enabled pull-up. ¾ Touch key input Rev. 1.00 9 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Pin Name Function PE0 PE0/PINT/ SSEG14 PINT SSEG14 PE1 Register Select PEPU MFI3 SLCDCn PEPU I/T ST ST ¾ ST ST ¾ ¾ ST ST ST ¾ ST ST O/T Description CMOS General purpose I/O. Register enabled pull-up. ¾ LCD Peripheral interrupt input Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up. CMOS TM2 I/O CMOS Peripheral Clock Output LCD Software controlled LCD SEG PE1/TP2_0/ PCK/SSEG15 PCK TP2_0 TMPCn SIMC0 SLCDCn PEPU SSEG15 PE2 CMOS General purpose I/O. Register enabled pull-up. CMOS TM2 I/O CMOS SPI select LCD Software controlled LCD SEG PE2/TP2_1/ SCS/SSEG16 SCS TP2_1 TMPCn SIMC0 SLCDCn PEPU SSEG16 PE3 CMOS General purpose I/O. Register enabled pull-up. CMOS SPI serial clock NMOS I C clock LCD Software controlled LCD SEG 2 PE3/SCK/ SCL/SSEG17 SCL SCK SIMC0 SIMC0 SLCDCn PEPU ST ¾ ST ST SSEG17 PE4 CMOS General purpose I/O. Register enabled pull-up. ¾ SDI PE4/SDI/ SDA/SSEG18 SDA SSEG18 PE5 SIMC0 SIMC0 SLCDCn PEPU SPI data input 2 ST ¾ ST ST ¾ NS NS NS NS PWR PWR NMOS I C data I/O LCD Software controlled LCD SEG CMOS General purpose I/O. Register enabled pull-up. CMOS SPI data output LCD ¾ ¾ ¾ ¾ ¾ ¾ Software controlled LCD SEG PE5/SDO/ SSEG19 KEY9 KEY10 KEY11 KEY12 VDD VSS SDO SSEG19 KEY9 KEY10 KEY11 KEY12 SIMC0 SLCDCn ¾ ¾ ¾ ¾ ¾ ¾ Touch key input Touch key input Touch key input Touch key input Power supply Ground VDD VSS Note: I/T: Input type O/T: Output type Register Select: Indicates register which selects alternative function PWR: Power ST: Schmitt Trigger input CMOS: CMOS output NMOS: NMOS output LCD: LCD COM or SEG Vbias output NS: Non-standard input or output The pins in the table reflect that of the package with the largest number of pins. For this reason not all pins may exist on all package types. Rev. 1.00 10 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Absolute Maximum Ratings Supply Voltage ...............................................................................................VSS-0.3V to VSS+6.0V Storage Temperature .................................................................................................-50°C to 125°C Input Voltage .................................................................................................VSS-0.3V to VDD+0.3V Operating Temperature ..................................................................................................-40°C to 85° CIOL Total ..................................................................................................................................80mA IOH Total ..................................................................................................................................-80mA Total Power Dissipation .........................................................................................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Test Conditions VDD Conditions fSYS=8MHz VDD Operating Voltage (HIRC) ¾ fSYS=12MHz fSYS=16MHz 3V 5V IDD1 Operating Current (HIRC), (fSYS=fH) 3V 5V 5V Operating Current (LIRC), (fSYS=fL) IDLE0 Mode Standby Current 5V IIDLE1 3V IDLE1 Mode Standby Current 5V 3V ISLEEP SLEEP1 Mode Standby Current 5V VIL Input Low Voltage for I/O Ports or Input Pins Input High Voltage for I/O Ports or Input Pins LVR Voltage Level Output Low Voltage I/O Port 5V IOL=20mA 5V ¾ 5V ¾ ¾ 3V VOL1 ¾ No load, LVR disable No load, LVR disable, fSYS=12MHz on 3V 5V 3V No load, LVR disable No load, fH=8MHz, WDT enable No load, fH=12MHz, WDT enable No load, fH=16MHz, WDT enable No load, fL=32kHz, WDT enable Min. VLVR 2.7 4.5 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 0 0 3.5 0.8VDD -5% ¾ ¾ Typ. ¾ ¾ ¾ 1.2 2.7 1.9 4.2 5.6 15 30 1.5 3.0 0.9 1.6 1.5 2.5 ¾ ¾ ¾ ¾ 2.55 ¾ ¾ Max. 5.5 5.5 5.5 1.8 4.1 2.9 6.3 8.4 30 50 3.0 6.0 1.4 2.4 3.0 5.0 1.5 0.2VDD 5.0 VDD +5% 0.3 0.5 Ta=25°C Unit V V V mA mA mA mA mA mA mA mA mA mA mA mA mA V V V V V V V IDD2 IIDLE0 VIH VLVR ¾ LVR Enable IOL=9mA Rev. 1.00 11 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Ta=25°C Symbol Parameter Output Low Voltage I/O Port (PB) (High Current Enable) Output High Voltage I/O Port 5V VOH2 VLVR Output High Voltage I/O Port (PA, PE) (High Current Enable) LVR Voltage Level 3V 5V ¾ Test Conditions VDD 3V 5V 3V VOH1 Conditions IOL=18mA IOL=40mA IOH=-3.2mA IOH=-7.4mA IOH=-6.4mA IOH=-15.0mA LVR Enable, 2.55V option LVDEN=1, VLVD=2.0V LVDEN=1, VLVD=2.2V LVDEN=1, VLVD=2.4V VLVD LVD Voltage Level ¾ LVDEN=1, VLVD=2.7V LVDEN=1, VLVD=3.0V LVDEN=1, VLVD=3.3V LVDEN=1, VLVD=3.6V LVDEN=1, VLVD=4.2V ILV Additional Power Consumption if LVD is Used ¾ NORMAL or SLOW Mode IDLE or SLEEP Mode ISEL[1:0]=00 ISEL[1:0]=01 ISCOM SCOM Operating Current 5V ISEL[1:0]=10 ISEL[1:0]=11 ISEL[1:0]=00 ISEL[1:0]=01 ISSEG SSEG Operating Current 5V ISEL[1:0]=10 ISEL[1:0]=11 1/3 VDD VSSOM Voltage for LCD SCOM 5V 2/3 VDD 1/3 VDD VSSEG Voltage for LCD SSEG 5V 2/3 VDD 3V RPH Pull-high Resistance for I/O Ports 5V ¾ 70 140 -3% -3% -3% -3% 20 10 100 200 0.33 0.67 0.33 0.67 60 30 130 260 +3% +3% +3% +3% 100 50 70 140 17.5 35 100 200 25.0 50 130 260 32.5 65 Min. ¾ ¾ 2.7 4.5 2.7 4.5 -5% -5% -5% -5% -5% -5% -5% -5% -5% ¾ ¾ 17.5 35 Typ. ¾ ¾ ¾ ¾ ¾ ¾ 2.55 2.00 2.20 2.40 2.70 3.00 3.30 3.60 4.20 2 15 25.0 50 Max. 0.3 0.5 ¾ ¾ ¾ ¾ +5% +5% +5% +5% +5% +5% +5% +5% +5% 5 30 32.5 65 Unit V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA VDD VDD VDD VDD kW kW VOL2 Rev. 1.00 12 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver A.C. Characteristics Symbol Parameter Test Conditions VDD ¾ Conditions VLVR~5.5V fCPU Operating Clock 2.7V~5.5V 4.5V~5.5V 3V/5V Ta=25°C 3V/5V Ta=25°C 5V Ta=25°C 3V/5V Ta=0~70°C 3V/5V Ta=0~70°C 5V Ta=0~70°C 2.5V~ Ta=0~70°C 4.0V 3.0V~ Ta=0~70°C 5.5V 2.7V~ Ta=0~70°C 4.0V 3.0V~ Ta=0~70°C 5.5V 4.5V~ Ta=0~70°C 5.5V 2.5V~ Ta= -40°C~85°C 4.0V 3.0V~ Ta= -40°C~85°C 5.5V 2.7V~ Ta= -40°C~85°C 4.0V 3.0V~ Ta= -40°C~85°C 5.5V 4.5V~ Ta= -40°C~85°C 5.5V 5V fLIRC fTIMER tINT tLVR tLVD tLVDS tEERD tEEWR tSST Note: System Clock (LIRC) Timer Input Pin Frequency Interrupt Pulse Width Low Voltage Width to Reset Low Voltage Width to Interrupt LVDO Stable Time EEPROM Read Time EEPROM Write Time System Start-up Timer Period (Wake-up from HALT) ¾ Min. DC DC DC -2% -2% -2% -4% -4% -4% -9% -5% -9% -5% -5% -12% -8% -13% -8% -7% -10% -50% ¾ 1 60 180 15 ¾ ¾ ¾ ¾ Typ. ¾ ¾ ¾ 8 12 16 8 12 16 8 8 12 12 16 8 8 12 12 16 32 32 ¾ ¾ 120 240 ¾ 2 2 15~16 1~2 Max. 8 12 16 +2% +2% +2% +3% +3% +3% +6% +12% +5% +11% +5% +6% +12% +5% +11% +5% +10% +60% 1 ¾ 240 360 ¾ 4 4 ¾ ¾ Ta=25°C Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz kHz fSYS ms ms ms ms tSYS ms tSYS fHIRC System Clock (HIRC) 2.2V~ Ta=-40°C~+85°C 5.5V ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ fSYS=HIRC fSYS=LIRC ¾ ¾ ¾ ¾ ¾ ¾ ¾ 1. tSYS=1/fSYS 2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1mF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. Rev. 1.00 13 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Power-on Reset Characteristics Symbol VPOR RPOR AC tPOR Parameter VDD Start Voltage to Ensure Power-on Reset VDD Raising Rate to Ensure Power-on Reset Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset Test Conditions VDD ¾ ¾ ¾ Conditions ¾ ¾ ¾ Min. ¾ 0.035 1 Typ. ¾ ¾ ¾ Max. Ta=25°C Unit 100 ¾ ¾ mV V/ms ms V DD tP OR RR VDD V POR T im e Oscillator Temperature/Frequency Characteristics The following characteristic graphics depicts typical oscillator behavior. The data presented here is a statistical summary of data gathered on units from different lots over a period of time. This is for information only and the figures were not tested during manufacturing. In some of the graphs, the data exceeding the specified operating range are shown for information purposes only. The device will operate properly only within the specified range. Internal RC -- 8MHz (3V) 8.300 8.200 8.100 8.000 7.900 7.800 7.700 7.600 7.500 7.400 7.300 -60 -40 -20 0 20 40 60 80 100 120 140 2.5V 2.7V 3.0V 4.0V fSYS (MHz) T Ta(°C)) a (°C Rev. 1.00 14 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Internal RC -- 8MHz (5V) 8.800 8.600 8.400 3.0V 4.0V 4.5V 4.75V 5.0V 5.25V 5.5V fSYS (MHz) 8.200 8.000 7.800 7.600 7.400 -60 -40 -20 0 20 40 Ta(°C)C ) T a (° 60 80 100 120 140 Internal RC -- 12MHz (3V) 12.400 12.200 12.000 11.800 fSYS (MHz) 11.600 2.7V 3.0V 4.0V 11.400 11.200 11.000 10.800 -60 -40 -20 0 20 40 60 80 100 120 140 T Ta(°C) a (°C ) Rev. 1.00 15 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Internal RC -- 12MHz (5V) 13.000 12.800 12.600 3.0V 4.0V 4.5V 4.75V 5.0V 5.25V 5.5V 12.400 fSYS (MHz) 12.200 12.000 11.800 11.600 11.400 -60 -40 -20 0 20 40 Ta(°C) ) T a (°C 60 80 100 120 140 Internal RC -- 16MHz (5V) 16.400 16.300 16.200 16.100 16.000 fSYS (MHz) 15.900 15.800 15.700 15.600 15.500 15.400 15.300 -60 -40 -20 0 20 40 Ta(°C)) T a (°C 60 80 100 120 140 4.5V 4.75V 5.0V 5.25V 5.5V Rev. 1.00 16 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver System Architecture A key factor in the high-performance features of the Holtek range of microcontroller is attributed to their internal system architecture. The range of devices take advantage of the usual features found within RISC microcontroller providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a high or low speed oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. fS Y S C lo c k ) (S y s te m P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2 P ip e lin in g F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 ) F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C ) F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 ) System Clocking and Pipelining 1 2 3 4 5 6 D ELAY: : : M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ] F e tc h In s t. 1 E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7 NOP Instruction Fetching Rev. 1.00 17 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. Device BS85B12-3 BS85C20-3 Stack Levels 4 8 T o p o f S ta c k S ta c k P o in te r S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry P ro g ra m C o u n te r B o tto m o f S ta c k S ta c k L e v e l N Rev. 1.00 18 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: · · · · · Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC Increment and Decrement INCA, INC, DECA, DEC Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device series the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 2K´15 bits or 4K´15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. B S 8 5 B 1 2 -3 B S 8 5 C 2 0 -3 R eset In te rru p t V e c to r Device BS85B12-3 BS85C20-3 Capacity 2Kx15 4Kx15 0000H 0004H R eset In te rru p t V e c to r 07FFH 1 5 b its 0FFFH 1 5 b its Flash Program Memory Structure Rev. 1.00 19 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the ²TABRD[m]² or ²TABRDL[m]² instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as ²0². The accompanying diagram illustrates the addressing data flow of the look-up table. Lastpage or T B H P R e g is te r T B L P R e g is te r P ro g ra m A d d re s s R e g is te r T B L H H ig h B y te M e m o ry D a ta 1 5 b its U s e r S e le c te d R e g is te r Low B y te Table Program Example The following example using the BS85B12-3 shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is ²700H² which refers to the start address of the last page within the 2K words Program Memory of the device. The table pointer is setup here to have an initial value of ²06H². This will ensure that the first data read from the data table will be at the Program Memory address ²706H² or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the ²TABRD [m]² instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the ²TABRD [m]² instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.00 20 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Tempreg1 db ? tempreg2 db ? : : mov a,06h mov tblp,a mov a,07h mov tbhp,a : : tabrd tempreg1 dec tblp tabrd tempreg2 ; temporary register #1 ; temporary register #2 ; initialise low table pointer - note that this address ; is referenced ; initialise high table pointer ; transfers value in table referenced by table pointer data at ; program memory address ²706H² transferred to tempreg1 and TBLH ; reduce value of table pointer by one ; transfers value in table referenced by table pointer data at ; program memory address ²705H² transferred to tempreg2 and TBLH in ; this example the data ²1AH² is transferred to tempreg1 and data ; ²0FH² to register tempreg2 ; sets initial address of program memory : : org 700h dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 5-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Writer Pin Name SDATA SCLK VPP VDD VSS Device Pin Name PA0 PA2 PA7 VDD VSS Pin Description Serial Address and data -- read/write Address and data serial clock input Reset input Power Supply (5.0V) Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 5-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and one line for the reset. The technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. Rev. 1.00 21 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver During the programming process the PA7 pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the PA0 and PA2 I/O pins for data and clock programming purposes. The user must there take care to ensure that no other outputs are connected to these two pins. W r ite r C o n n e c to r S ig n a ls VDD MCU VDD P r o g r a m m in g P in s VPP SDATA PA7 PA0 SC LK PA2 VSS * * * VSS T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1kW or the capacitance of * must be less than 1nF. RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Function Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. Device BS85B12-3 BS85C20-3 Capacity 256´8 384´8 Bank 0 80H~FFH 80H~FFH Bank 1 80H~FFH 80H~FFH Bank 2 ¾ 80H~FFH General Purpose Data Memory The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two or three banks. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for all devices is the address 00H. Rev. 1.00 22 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section, however several registers require a separate description in this section. Indirect Addressing Registers - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation. Memory Pointers - MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used with Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. Note that for this series of devices, the Memory Pointers, MP0 and MP1, are both 8-bit registers and used to access the Data Memory together with their corresponding indirect addressing registers IAR0 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ¢code¢ org 00h start: mov mov mov mov loop: clr inc sdz jmp a,04h block,a a,offset adres1 mp0,a IAR0 mp0 block loop ; setup size of block ; Accumulator loaded with first RAM address ; setup memory pointer with first RAM address ; clear the data at address defined by MP0 ; increment memory pointer ; check if last memory location has been cleared continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Rev. 1.00 23 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver B S 8 5 B 1 2 -3 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Bank 0 IA M IA M ,Bank 1 R0 P0 R1 P1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVD C IN T E G W DTC TBC IN T C 0 IN T C 1 IN T C 2 U nused M F I0 M F I1 M F I2 M F13 PAW U PAPU PA PAC PBPU PB PBC PCPU PC PCC U nused U nused U nused U nused U nused U nused SLC DC0 SLC DC1 SLC DC2 U nused SLEDC0 SLEDC1 U nused U nused U nused U nused U nused U nused U nused I2 C T O C S IM C 0 S IM C 1 S IM D S IM A /S IM C 2 TM 0C0 TM 0C1 TM 0DL TM 0DH TM 0AL TM 0AH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Bank 0 U nused Bank 1 EEC 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH k 0~2 R0 P0 R1 P1 BP ACC PCL TBLP TBLH TBHP STATUS SMOD LVD C IN T E G W DTC TBC IN T C 0 IN T C 1 IN T C 2 IN T C 3 M F I0 M F I1 M F I2 M F I3 PAW U PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC SLC DC0 SLC DC1 SLC DC2 SLC DC3 SLEDC0 SLEDC1 SLEDC2 U nused M F I4 M F I5 U nused U nused U nused I2 C T O C S IM C 0 S IM C 1 S IM D S IM A /S IM C 2 TM 0C0 TM 0C1 TM 0DL TM 0DH TM 0AL TM 0AH Ban IA M IA M B S 8 5 C 2 0 -3 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH Bank 0,2 Bank 1 U nused EEC EEA EED TM PC0 TM PC1 PRM0 PRM1 PRM2 TM 1C0 TM 1C1 TM 1C2 TM 1DL TM 1DH TM 1AL TM 1AH TM 1BL TM 1BH TM 2C0 TM 2C1 TM 2DL TM 2DH TM 2AL TM 2AH CTRL TKM 016D H TKM 016D L R e s e rv e d R e s e rv e d TKM 0C 0 TKM 0C 1 TKM 0C 2 TKM 0C 3 TKM 116D H TKM 116D L R e s e rv e d R e s e rv e d TKM 1C 0 TKM 1C 1 TKM 1C 2 TKM 1C 3 TKM 216D H TKM 216D L R e s e rv e d R e s e rv e d TKM 2C 0 TKM 2C 1 TKM 2C 2 TKM 2C 3 TKM 316D H TKM 316D L R e s e rv e d R e s e rv e d TKM 3C 0 TKM 3C 1 TKM 3C 2 TKM 3C 3 TKM 4D H TKM 4D L R e s e rv e d R e s e rv e d TKM 4C 0 TKM 4C 1 TKM 4C 2 TKM 4C 3 T T T T T T EEA EED TM PC0 U nused PRM0 PRM1 PRM2 TM 1C0 TM 1C1 TM 1C2 TM 1DL TM 1DH TM 1AL TM 1AH TM 1BL TM 1BH U nused U nused U nused U nused U nused U nused CTRL KM 016D KM 016D R e s e rv e d R e s e rv e d TKM 0C 0 TKM 0C 1 TKM 0C 2 TKM 0C 3 KM 116D KM 116D R e s e rv e d R e s e rv e d TKM 1C 0 TKM 1C 1 TKM 1C 2 TKM 1C 3 KM 216D KM 216D R e s e rv e d R e s e rv e d TKM 2C 0 TKM 2C 1 TKM 2C 2 TKM 2C 3 U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused U nused H L H L H L Special Purpose Data Memory Note: The ²Reserved² bytes shown in the table must not be modified by the user. Rev. 1.00 24 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver B S 8 5 B 1 2 -3 80H 80H B S 8 5 C 2 0 -3 Bank 0 Bank 1 Bank 0 Bank 1 Bank 2 FFH FFH General Purpose Data Memory Bank Pointer - BP For this series of devices, the Data Memory is divided into two or three banks. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 and 1 is used to select Data Memory Banks 0~2. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from banks other than Bank 0 must be implemented using indirect addressing. BP Register -- BS85B12-3 Bit Name R/W POR Bit 7~1 Bit 0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 ¾ ¾ ¾ 0 DMBP0 R/W 0 unimplemented, read as ²0² DMBP0: select data memory banks 0: bank 0 1: bank 1 BP Register -- BS85C20-3 Bit Name R/W POR Bit 7~2 Bit 1~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 DMBP0 R/W 0 0 DMBP0 R/W 0 unimplemented, read as ²0² DMBP1, DMBP0: select data memory banks 00: bank 0 01: bank 1 10: bank 2 11: undefined Rev. 1.00 25 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointer and indicates the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the ²INC² or ²DEC² instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. · C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. · · · Rev. 1.00 26 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver · PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. · In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit Name R/W POR Bit 7, 6 Bit 5 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 TO R 0 4 PDF R 0 3 OV R/W x 2 Z R/W x 1 AC R/W x 0 C R/W x ²x² unknown Bit 4 Bit 3 Bit 2 unimplemented, read as ²0² TO: watchdog time-out flag 0: After power up or executing the ²CLR WDT² or ²HALT² instruction 1: A watchdog time-out occurred. PDF: power down flag 0: After power up or executing the ²CLR WDT² instruction 1: By executing the ²HALT² instruction OV: Overflow flag 0: no overflow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero AC: Auxiliary flag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction C: Carry flag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Bit 1 Bit 0 Rev. 1.00 27 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver EEPROM Data Memory The devices contain an area of internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of re-programmable memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64´8 or 128´8 bits for this series of devices. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. Device BS85B12-3 BS85C20-3 Capacity 64´8 128´8 Address 00H ~ 3FH 00H ~ 7FH EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Bank1, cannot be addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. EEPROM Register List · BS85B12-3 Bit 7 ¾ D7 ¾ 6 ¾ D6 ¾ 5 D5 D5 ¾ 4 D4 D4 ¾ 3 D3 D3 WREN 2 D2 D2 WR 1 D1 D1 RDEN 0 D0 D0 RD Name EEA EED EEC · BS85C20-3 Bit 7 ¾ D7 ¾ 6 D6 D6 ¾ 5 D5 D5 ¾ 4 D4 D4 ¾ 3 D3 D3 WREN 2 D2 D2 WR 1 D1 D1 RDEN 0 D0 D0 RD Name EEA EED EEC Rev. 1.00 28 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver EEA Register · BS85B12-3 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Bit Name R/W POR Bit 7, 6 Bit 5~0 · unimplemented, read as ²0² Data EEPROM address Data EEPROM address bit 5~bit 0 BS85C20-3 7 ¾ ¾ ¾ 6 D6 R/W x 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Bit Name R/W POR Bit 7 Bit 6~0 unimplemented, read as ²0² Data EEPROM address Data EEPROM address bit 6~bit 0 EEC Register Bit Name R/W POR Bit 7~4 Bit 3 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 WREN R/W 0 2 WR R/W 0 1 RDEN R/W 0 0 RD R/W 0 Bit 2 unimplemented, read as ²0² WREN: data EEPROM write enable 0: disable 1: enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. WR: EEPROM write control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. RDEN: Data EEPROM read enable 0: disable 1: enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 1 Bit 0 RD: EEPROM read control 0: read cycle has finished 1: activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. The WREN, WR, RDEN and RD can not be set to ²1² at the same time in one instruction. The WR and RD can not be set to ²1² at the same time. Note: Rev. 1.00 29 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver EED Register Bit Name R/W POR Bit 7~0 7 D7 R/W x 6 D6 R/W x 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Data EEPROM data Data EEPROM data bit 7~bit 0 Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multi-function interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Rev. 1.00 30 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Programming Examples Reading Data from the EEPROM - Polling Method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EEDATA MOV READ_DATA, A ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register Writing Data to the EEPROM - Polling Method CLR MOV MOV MOV MOV MOV MOV MOV MOV SET SET EMI A, EEPROM_ADRES EEA, A A, EEPROM_DATA EED, A A, 040H MP1, A A, 01H BP, A IAR1.3 IAR1.2 ; user defined address ; user defined data ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set WREN bit, enable write operations ; Start Write Cycle - set WR bit - executed immediately ; after set WREN bit ; check for write cycle end ; disable EEPROM read/write SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 1.00 31 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview The devices include two internal oscillators, a low speed oscillator and high speed oscillator. Both can be chosen as the clock source for the main system clock however the slow speed oscillator is also used as a clock source for other functions such as the Watchdog Timer, Time Base and Timer Modules. Both oscillators require no external components for their implementation. All oscillator options are selected using registers. The high speed oscillator provides higher performance but carries with it the disadvantage of higher power requirements, while the opposite is of course true for the low speed oscillator. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimise the performance/power ratio, a feature especially important in power sensitive portable applications. Type Internal High Speed Internal Low Speed Name HIRC LIRC Oscillator Types Freq. 8, 12 or 16MHz 32kHz System Clock Configurations There are two methods of generating the system clock, a high speed internal clock source and low speed internal clock source. The high speed oscillator is an internal 8MHz, 12MHz or 16MHz RC oscillator while the low speed oscillator is an internal 32kHz RC oscillator. Both oscillators are fully integrated and do not require external components. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register allowing the system clock to be dynamically selected. Internal High Speed RC Oscillator - HIRC The internal High Speed RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a power on default frequency of 8 MHz but can be selected to be either 8MHz, 12MHz or 16MHz using the HIRCS1 and HIRCS0 bits in the CTRL register. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Rev. 1.00 32 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver CTRL Register Bit Name R/W POR Bit 7, 6 Bit 5, 4 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 HIRCS1 R/W 0 4 HIRCS0 R/W 0 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D1 R/W 0 0 D0 R/W 0 ²x² unknown unimplemented, read as ²0² HIRCS1, HIRCS0: High frequency clock select 00: 8MHz 01: 16MHz 10: 12MHz 11: 8MHz unimplemented, read as ²0² D1, D0: These bits must be set to the binary value ²00² Bit 3, 2 Bit 1, 0 Internal Low Speed RC Oscillator - LIRC The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. After power on this LIRC oscillator will be permanently enabled; there is no provision to disable the oscillator using register bits. Rev. 1.00 33 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The main system clock, can come from either a high frequency, fH, or low frequency, fL, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. Both the high and low speed system clocks are sourced from internal RC oscillators. H ig h S p e e d O s c illa to r H IR C 8 M H z /1 2 M H z /1 6 M H z fH IR C H ig h S p e e d C lo c k S e le c t H IR C S 0 , H IR C S 1 b its 6 - s ta g e P r e s c a le r f H IR C / n n = (2 , 4 , 8 , 1 6 , 3 2 o r 6 4 ) M U X fL F a s t/S lo w C lo c k S e le c t M U fH IR C /n o r fL X IR C fS YS L IR C 32kH z L o w S p e e d O s c illa to r P e r m a n e n tly E n a b le d IR C 32kH z H C L K b it C lo c k S e le c t C K S 0 ~ C K S 2 b its fL fL IR C W a tc h d o g T im e r fS YS /4 M U X T im e B a s e 0 T im e B a s e 1 IR C T B C K b it System Clock Configurations Rev. 1.00 34 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. SMOD Register Bit Name R/W POR Bit 7~5 7 CKS2 R/W 0 6 CKS1 R/W 0 5 CKS0 R/W 0 4 D4 R/W 0 3 LTO R 0 2 HTO R 0 1 IDLEN R/W 1 0 HLCLK R/W 1 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CKS2~CKS0: The system clock selection when HLCLK is ²0² 000: fL (fLIRC) 001: fL (fLIRC) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which is LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Undefined bit These bits can be read or written by user software program. LTO: Low speed system oscillator ready flag 0: not ready 1: ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset. HTO: High speed system oscillator ready flag 0: not ready 1: ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to ²0² by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as ²1² by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles. IDLEN: IDLE Mode control 0: disable 1: enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. HLCLK: system clock selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. Rev. 1.00 35 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver System Operation Modes There are five different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining three modes, the SLEEP, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode NORMAL Mode SLOW Mode IDLE0 Mode IDLE1 Mode SLEEP Mode · Description CPU On On Off Off Off fSYS fH~ fH/64 fL Off On Off fLIRC On On On On On fTBC On On On On Off NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~LCKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with the slow speed clock source. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the high speed clock is off. SLEEP Mode The SLEEP Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP mode the CPU will be stopped however as the fLIRC oscillator continues to run the Watchdog Timer will continue to operate. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is low. In the IDLE0 Mode the system oscillator the system oscillator will be stopped and will therefore be inhibited from driving the CPU. IDLE1 Mode The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the WDTC register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be the high speed or low speed system oscillator. · · · · Rev. 1.00 36 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver fS NORMAL Y S = fH ~ fH /6 4 fH o n C P U ru n fS Y S o n f L IR C o n W D T on SLOW fS Y S = fL fL o n C P U ru n fS Y S o n f L IR C o n fH o ff W D T on SLEEP H A L T in s tr u c tio n is e x e c u te d fS Y S o ff C P U s to p ID L E N = 0 f L IR C o n W D T on ID L E 1 H A L T in s tr u c tio n is e x e c u te d C P U s to p ID L E N = 1 FSYSO N=1 fS Y S o n f L IR C o n W D T on ID L E 0 H A L T in s tr u c tio n is e x e c u te d C P U s to p ID L E N = 1 FSYSO N=0 fS Y S o ff f L IR C o n W D T on Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the WDTC register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fHIRC, to the clock source, fHIRC/2~fHIRC/64 or fLIRC. If the clock is from fHIRC, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fHIRC/16 and fHIRC/64 internal clock sources will also stop running. The accompanying flowchart shows what happens when the device moves between the various operating modes. Rev. 1.00 37 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver N O RM AL M ode SLO W M ode C K S 2 ~ C K S 0 = 00xB & HLC LK = 0 SLO W M ode C KS2~C KS0¹000B,001B as H LCLK=0 orHLC LK=1 NO RM AL M ode ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP M ode ID L E N = 1 , F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d ID L E N = 0 H A L T in s tr u c tio n is e x e c u te d SLEEP M ode ID L E N = 1 , F S Y S O N = 0 H A L T in s tr u c tio n is e x e c u te d ID E L 0 M o d e ID L E N = 1 , F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e ID L E 0 M o d e ID L E N = 1 , F S Y S O N = 1 H A L T in s tr u c tio n is e x e c u te d ID L E 1 M o d e NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by set the HLCLK bit to ²0² and set the CKS2~CKS0 bits to ²000² or ²001² in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode clock is sourced from the LIRC oscillator. SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses the LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to ²1² or HLCLK bit is ²0², but CKS2~CKS0 is set to ²010², ²011², ²100², ²101², ²110² or ²111². As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in SMOD register equal to ²0². When this instruction is executed under the conditions described above, the following will occur: · · · · · The system clock will be stopped and the application program will stop at the ²HALT² instruction, but the fLIRC clock will be on. The Data Memory contents and registers will maintain their present condition. The WDT will be cleared and resume counting. The I/O ports will maintain their present conditions. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 38 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in SMOD register equal to ²1² and the FSYSON bit in WDTC register equal to ²0². When this instruction is executed under the conditions described above, the following will occur: · · · · · The system clock will be stopped and the application program will stop at the ²HALT² instruction, but the Time Base clock and fLIRC clock will be on. The Data Memory contents and registers will maintain their present condition. The WDT will be cleared and resume counting. The I/O ports will maintain their present conditions. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the ²HALT² instruction in the application program with the IDLEN bit in SMOD register equal to ²1² and the FSYSON bit in WDTC register equal to ²1². When this instruction is executed under the with conditions described above, the following will occur: · · · · · The system clock and fLIRC clock will be on and the application program will stop at the ²HALT² instruction. The Data Memory contents and registers will maintain their present condition. The WDT will be cleared and resume counting. The I/O ports will maintain their present conditions. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Rev. 1.00 39 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: · · · · An external reset An external falling edge on Port A A system interrupt A WDT overflow If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the ²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. System Oscillator HIRC LIRC Wake-up Time (SLEEP Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) 1~2 HIRC cycles 1~2 LIRC cycles 15~16 HIRC cycles 1~2 LIRC cycles Wake-Up Times Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP Mode the HIRC oscillator needs to start-up from an off state. · If the device is woken up from the SLEEP Mode to the NORMAL Mode, the high speed system oscillator needs an SST period. The device will execute the first instruction after HTO is high. Rev. 1.00 40 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal low speed oscillator, fLIRC. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 215 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period. WDTC Register Bit Name R/W POR Bit 7 7 FSYSON R/W 0 6 WS2 R/W 1 5 WS1 R/W 1 4 WS0 R/W 1 3 D3 R/W 1 2 D2 R/W 0 1 D1 R/W 1 0 D0 R/W 0 Bit 6~4 FSYSON: fSYS control in IDLE Mode 0: disable 1: enable WS2, WS1, WS0 : WDT time-out period selection 000: 256/fLIRC 001: 512/fLIRC 010: 1024/fLIRC 011: 2048/fLIRC 100: 4096/fLIRC 101: 8192/fLIRC 110: 16384/fLIRC 111: 32768/fLIRC These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. Undefined bit These bits can be read or written by user software program. Bit 3~0 Rev. 1.00 41 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Watchdog Timer Operation In these devices the Watchdog Timer supplied by the fLIRC oscillator and is therefore always on. The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is an external hardware reset, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. The Watchdog Timer is cleared using a single CLR WDT instruction. The maximum time out period is when the 215 division ratio is selected. As an example, with the LIRC oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 215 8 division ratio, and a minimum timeout of 7.8ms for the 2 division ration. C le a r W D T In s tr u c tio n L IR C O s c illa to r 8 - s ta g e D iv id e r fL IR C /2 8 CLR W D T P r e s c a le r 8 -to -1 M U X W S2~W S0 W D T T im e - o u t ( 2 8 / f L IR C ~ 2 1 5 / f L IR C ) Watchdog Timer Rev. 1.00 42 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD RES In te rn a l R e s e t 0 .9 V DD t RR SS TT DD ++ t SS SS TT Note: tRSTD is power-on delay, typical time=100ms Power-On Reset Timing Chart Low Voltage Reset - LVR If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed tLVR, the LVR will ignore it and will not perform a reset function. One of a range of specified voltage values for VLVR can be selected using configuration options. The LVR function is permanently on in these devices. LVR tR In te rn a l R e s e t STD + tS ST Note: tRSTD is power-on delay, typical time=100ms Low Voltage Reset Timing Chart Rev. 1.00 43 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a hardware power-on reset except that the Watchdog time-out flag TO will be set to ²1². W D T T im e - o u t tR In te rn a l R e s e t STD + tS ST Note: tRSTD is power-on delay, typical time=100ms WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to ²0² and the TO flag will be set to ²1². Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by HIRC. The tSST is 1~2 clock for LIRC. W D T T im e - o u t tS In te rn a l R e s e t ST WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO 0 u 1 1 PDF 0 u u 1 Power-on reset LVR reset during NORMAL or SLOW Mode operation WDT time-out reset during NORMAL or SLOW Mode operation WDT time-out reset during IDLE or SLEEP Mode operation RESET Conditions Note: ²u² stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Timer Modules Input/Output Ports Stack Pointer Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off I/O ports will be setup as inputs Stack Pointer will point to the top of the stack Condition After RESET Rev. 1.00 44 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. BS85C20-3 BS85B12-3 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · Register Power-on Reset LVR Reset WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP) MP0 MP1 BP BP ACC PCL TBLP TBLH TBHP TBHP STATUS SMOD LVDC INTEG WDTC TBC INTC0 INTC1 INTC2 INTC3 MFI0 MFI1 MFI2 MFI3 PAWU PAPU PA PAC PBPU PBPU · · xxxx xxxx xxxx xxxx ---- ---0 ---- --00 xxxx xxxx 0000 0000 xxxx xxxx -xxx xxxx ---- -xxx ---- xxxx --00 xxxx 0000 0011 --00 -000 ---- 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 0000 0000 uuuu uuuu uuuu uuuu ---- ---0 ---- --00 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu ---- uuuu --uu uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 0000 0000 uuuu uuuu uuuu uuuu ---- ---0 ---- --00 uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu ---- uuuu --1u uuuu 0000 0011 --00 -000 ---- 0000 0111 1010 0011 0111 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -000 -000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 --00 0000 0000 0000 uuuu uuuu uuuu uuuu ---- ---u ---- --uu uuuu uuuu 0000 0000 uuuu uuuu -uuu uuuu ---- -uuu ---- uuuu --11 uuuu uuuu uuuu --uu -uuu ---- uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu Rev. 1.00 45 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver BS85B12-3 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · BS85C20-3 WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP) Register Power-on Reset LVR Reset PB PB PBC PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC SLCDC0 SLCDC1 SLCDC2 SLCDC2 SLCDC3 SLEDC0 SLEDC0 SLEDC1 SLEDC2 MFI4 MFI5 I2CTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 TM0C0 TM0C1 TM0DL TM0DH TM0AL --11 1111 1111 1111 --11 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 0000 0000 0000 0000 --00 0000 0000 0000 0-00 0000 --00 0000 0000 0000 0000 0000 --00 0000 0000 0000 --00 --00 0000 0000 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 --11 1111 1111 1111 --11 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 0000 0000 0000 0000 --00 0000 0000 0000 0-00 0000 --00 0000 0000 0000 0000 0000 --00 0000 0000 0000 --00 --00 0000 0000 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 --11 1111 1111 1111 --11 1111 1111 1111 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 --00 0000 --11 1111 --11 1111 0000 0000 0000 0000 --00 0000 0000 0000 0-00 0000 --00 0000 0000 0000 0000 0000 --00 0000 0000 0000 --00 --00 0000 0000 1110 0001000 0001 xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 --uu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu --uu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu u-uu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu --uu --uu uuuu uuuu uuuu uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu Rev. 1.00 46 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver BS85B12-3 · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · · BS85C20-3 WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP) Register Power-on Reset LVR Reset TM0AH EEA EEA EED TMPC0 TMPC1 PRM0 PRM0 PRM1 PRM1 PRM2 PRM2 TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL TM1AH TM1BL TM1BH TM2C0 TM2C1 TM2DL TM2DH TM2AL TM2AH CTRL TKM016DH TKM016DL TKM0C0 TKM0C1 TKM0C2 TKM0C3 · ---- --00 --00 0000 -000 0000 0000 0000 1001 --01 ---- --01 -0-0 -0-0 0000 0000 0000 -0-0 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 --00 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 --00 0000 -000 0000 0000 0000 1001 --01 ---- --01 -0-0 -0-0 0000 0000 0000 -0-0 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 --00 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 --00 0000 -000 0000 0000 0000 1001 --01 ---- --01 -0-0 -0-0 0000 0000 0000 -0-0 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 ---- --00 0000 0000 0000 0000 0000 0000 ---- --00 0000 0000 ---- --00 --00 --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- --uu --uu uuuu -uuu uuuu uuuu uuuu uuuu --uu ---- --uu -u-u -u-u uuuu uuuu uuuu -u-u uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu ---- --uu uuuu uuuu uuuu uuuu uuuu uuuu ---- --uu uuuu uuuu ---- --uu --uu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu Rev. 1.00 47 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver BS85B12-3 · · · · · · · · BS85C20-3 WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP) Register Power-on Reset LVR Reset TKM116DH TKM116DL TKM1C0 TKM1C1 TKM1C2 TKM1C3 TKM216DH TKM216DL TKM2C0 TKM2C1 TKM2C2 TKM2C3 TKM316DH TKM316DL TKM3C0 TKM3C1 TKM3C2 TKM3C3 TKM416DH TKM416DL TKM4C0 TKM4C1 TKM4C2 TKM4C3 EEC Note: · · · · · · · · · 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu · · · · · · · · · · · · · · · · · · · · ²u² stands for unchanged ²x² stands for unknown ²-² stands for unimplemented Rev. 1.00 48 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PE. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. I/O Register List BS85B12-3 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC Bit 7 D7 D7 D7 D7 ¾ ¾ ¾ D7 D7 D7 6 D6 D6 D6 D6 ¾ ¾ ¾ D6 D6 D6 5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 Rev. 1.00 49 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver BS85C20-3 Register Name PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC PEPU PE PEC Bit 7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 D7 ¾ ¾ ¾ 6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 D6 ¾ ¾ ¾ 5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 D5 4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 D4 3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 D1 0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 D0 Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using the register PAPU~PEPU, and are implemented using weak PMOS transistors. BS85B12-3: PAPU, PCPU Registers BS85C20-3: PAPU, PBPU, PCPU, PDPU Registers Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 PxPU Port bit 7~bit 0 Pull-High control 0: disable 1: enable BS85B12-3: PBPU Registers BS85C20-3: PEPU Registers Bit Name R/W POR Bit 7~4 Bit 3~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 unimplemented, read as ²0² PxPU: Port bit 5~bit 0 Pull-High control 0: disable 1: enable Rev. 1.00 50 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit Name R/W POR Bit 7~5 Bit 4~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 unimplemented, read as ²0² PAWU: Port A bit 7~bit 0 wake-up control 0: disable 1: enable I/O Port Control Register The I/O port has its own control register known as PAC~PEC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O port is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. BS85B12-3: PAC, PCC Registers BS85C20-3: PAC, PBC, PCC, PDC Registers Bit Name R/W POR Bit 7~0 7 D7 R/W 1 6 D6 R/W 1 5 D5 R/W 1 4 D4 R/W 1 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1 I/O Port bit 7 ~ bit 0 input/output control 0: output 1: input BS85B12-3: PBC Registers BS85C20-3: PEC Registers Bit Name R/W POR Bit 7~4 Bit 3~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 1 2 D2 R/W 1 1 D1 R/W 1 0 D0 R/W 1 unimplemented, read as ²0² PxC: Port bit 5~bit 0 input/output control 0: output 1: input Rev. 1.00 51 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Pin Re-mapping Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. The way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. Additionally there are a series of PRM0, PRM1 and PRM2 registers to establish certain pin functions. Pin-remapping Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. The device includes PRM0, PRM1, PRM2 registers which can select the functions of certain pins. Pin-remapping Register List · BS85B12-3 Bit 7 ¾ 6 SCSPS0 INT0PS TP1B1PS 5 ¾ TCK1PS TP1B0PS 4 SDIPS0 TCK0PS TP1APS 3 ¾ ¾ ¾ 2 SCKPS0 PINTS0 ¾ 1 ¾ ¾ TP01PS 0 SDOPS0 PCKPS0 TP00PS Register Name PRM0 PRM1 PRM2 INT1PS TP1B2PS · BS85C20-3 Bit 7 6 SCSPS0 INT0PS TP1B1PS ¾ 5 SDIPS1 TCK1PS TP1B0PS SEG21EN 4 SDIPS0 TCK0PS TP1APS SEG20EN 3 SCKPS1 PINTS1 TP21PS SEG19EN 2 SCKPS0 PINTS0 TP20PS SEG18EN 1 SDOPS1 PCKPS1 TP01PS SEG17EN 0 SDOPS0 PCKPS0 TP00PS SEG16EN Register Name PRM0 PRM1 PRM2 SLCDC3 SCSPS1 INT1PS TP1B2PS TCK2PS Rev. 1.00 52 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver PRM0 Register -- BS85B12-3 Bit Name R/W POR Bit 7 Bit 6 7 ¾ ¾ ¾ 6 SCSPS0 R/W 0 5 ¾ ¾ ¾ 4 SDIPS0 R/W 0 3 ¾ ¾ ¾ 2 SCKPS0 R/W 0 1 ¾ ¾ ¾ 0 SDOPS0 R/W 0 unimplemented, read as ²0² SCSPS0: SCS pin remapping control 0: SCS on PA3 1: SCS on PC3 unimplemented, read as ²0² SDIPS0: SDI/SDA pin remapping control 0: SDI/SDA on PA0 1: SDI/SDA on PC2 unimplemented, read as ²0² SCKPS0: SCK/SCL pin remapping control 0: SCK/SCL on PA2 1: SCK/SCL on PC1 unimplemented, read as ²0² SDOPS0: SDO pin remapping control 0: SDO on PA7 1: SDO on PC0 PRM0 Register -- BS85C20-3 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name R/W POR Bit 7~6 7 SCSPS1 R/W 0 6 SCSPS0 R/W 0 5 SDIPS1 R/W 0 4 SDIPS0 R/W 0 3 SCKPS1 R/W 0 2 SCKPS0 R/W 0 1 SDOPS1 R/W 0 0 SDOPS0 R/W 0 Bit 5~4 Bit 3~2 Bit 1~0 SCSPS1~SCSPS0: SCS pin remapping control 00: SCS on PA3 01: SCS on PC3 10: SCS on PE2 11: undefined SDIPS1~SDIPS0: SDI/SDA pin remapping control 00: SDI/SDA on PA0 01: SDI/SDA on PC2 10: SDI/SDA on PE4 11: undefined SCKPS1~SCKPS0: SCK/SCL pin remapping control 00: SCK/SCL on PA2 01: SCK/SCL on PC1 10: SCK/SCL on PE3 11: undefined SDOPS1~SDOPS0: SDO pin remapping control 00: SDO on PA7 01: SDO on PC0 10: SDO on PE5 11: undefined Rev. 1.00 53 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver PRM1 Register -- BS85B12-3 Bit Name R/W POR Bit 7 7 INT1PS R/W 0 6 INT0PS R/W 0 5 TCK1PS R/W 0 4 TCK0PS R/W 0 3 ¾ ¾ ¾ 2 PINTS0 R/W 0 1 ¾ ¾ ¾ 0 PCKPS0 R/W 0 Bit 6 INT1PS: INT1 pin remapping control 0: INT1 on PA1 1: INT1 on PC5 INT0PS: INT0 pin remapping control 0: INT0 on PA4 1: INT0 on PC4 TCK1PS: TCK1 pin remapping control 0: TCK1 on PA1 1: TCK1 on PC5 TCK0PS: TCK0 pin remapping control 0: TCK0 on PA4 1: TCK0 on PC4 unimplemented, read as ²0² PINTS0: PINT pin remapping control 0: PINT on PB5 1: PINT on PC7 unimplemented, read as ²0² PCKPS0: PCK pin remapping control 0: PCK on PB4 1: PCK on PC6 PRM1 Register -- BS85C20-3 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name R/W POR Bit 7 7 INT1PS R/W 0 6 INT0PS R/W 0 5 TCK1PS R/W 0 4 TCK0PS R/W 0 3 PINTS1 R/W 0 2 PINTS0 R/W 0 1 PCKPS1 R/W 0 0 PCKPS0 R/W 0 Bit 6 INT1PS: INT1 pin remapping control 0: INT1 on PA1 1: INT1 on PC5 INT0PS: INT0 pin remapping control 0: INT0 on PA4 1: INT0 on PC4 TCK1PS: TCK1 pin remapping control 0: TCK1 on PA1 1: TCK1 on PC5 TCK0PS: TCK0 pin remapping control 0: TCK0 on PA4 1: TCK0 on PC4 PINTS1~PINTS0: PINT pin remapping control 00: PINT on PB5 01: PINT on PC7 10: PINT on PE0 11: undefined PCKPS1~PCKPS0: PCK pin remapping control 00: PCK on PB4 01: PCK on PC6 10: PCK on PE1 11: undefined Bit 5 Bit 4 Bit 3~2 Bit 1~0 Rev. 1.00 54 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver PRM2 Register -- BS85B12-3 Bit Name R/W POR Bit 7 7 TP1B2PS R/W 0 6 TP1B1PS R/W 0 5 TP1B0PS R/W 0 4 TP1APS R/W 0 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 TP01PS R/W 0 0 TP00PS R/W 0 Bit 6 TP1B2PS: TP1B_2 pin remapping cControl 0: TP1B_2 on PB4 1: TP1B_2 on PC4 TP1B1PS: TP1B_1 pin remapping control 0: TP1B_1 on PB3 1: TP1B_1 on PC3 TP1B0PS: TP1B_0 pin remapping control 0: TP1B_0 on PB2 1: TP1B_0 on PC2 TP1APS: TP1A pin remapping control 0: TP1A on PB5 1: TP1A on PC5 unimplemented, read as ²0² TP01PS: TP0_1 Pin Remapping Control 0: TP0_1 on PB1 1: TP0_1 on PC1 TP00PS: TP0_0 Pin Remapping Control 0: TP0_0 on PB0 1: TP0_0 on PC0 PRM2 Register -- BS85C20-3 Bit 5 Bit 4 Bit 3~2 Bit 1 Bit 0 Bit Name R/W POR Bit 7 7 TP1B2PS R/W 0 6 TP1B1PS R/W 0 5 TP1B0PS R/W 0 4 TP1APS R/W 0 3 TP21PS R/W 0 2 TP20PS R/W 0 1 TP01PS R/W 0 0 TP00PS R/W 0 Bit 6 TP1B2PS: TP1B_2 pin remapping control 0: TP1B_2 on PB4 1: TP1B_2 on PC4 TP1B1PS: TP1B_1 pin remapping control 0: TP1B_1 on PB3 1: TP1B_1 on PC3 TP1B0PS: TP1B_0 pin remapping control 0: TP1B_0 on PB2 1: TP1B_0 on PC2 TP1APS: TP1A pin remapping coontrol 0: TP1A on PB5 1: TP1A on PC5 TP21PS: TP2_1 pin remapping coontrol 0: TP2_1 on PB2 1: TP2_1 on PE2 TP20PS: TP2_0 pin remapping coontrol 0: TP2_0 on PB1 1: TP2_0 on PE1 TP01PS: TP0_1 pin remapping coontrol 0: TP0_1 on PB1 1: TP0_1 on PC1 TP00PS: TP0_0 pin remapping coontrol 0: TP0_0 on PB0 1: TP0_0 on PC0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.00 55 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SLCDC3 Register -- BS85C20-3 Bit Name R/W POR Bit 7 7 TCK2PS R/W 0 6 ¾ ¾ ¾ 5 SEG21EN R/W 0 4 SEG20EN R/W 0 3 SEG19EN R/W 0 2 SEG18EN R/W 0 1 SEG17EN R/W 0 0 SEG16EN R/W 0 TCK2PS: TCK2 pin remapping control 0: TCK2 on PC6 1: TCK2 on PD0 unimplemented, read as ²0² described elsewhere Bit 6 Bit 5~0 I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. P u ll- H ig h R e g is te r S e le c t V DD C o n tr o l B it D a ta B u s D Q CK S Q W eak P u ll- u p W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r I/O D a ta B it Q D CK Q S M U X p in W r ite D a ta R e g is te r R e a d D a ta R e g is te r S y s te m W a k e -u p W a k e - u p S e le c t P A o n ly Generic Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control register, PAC~PEC, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data register, PA~PE, is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.00 56 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Timer Modules - TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions each device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has either two or three individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Enhanced TM sections. Introduction The devices contain from two to three TMs depending upon which device is selected with each TM having a reference name of TM0, TM1 and TM2. Each individual TM can be categorised as a certain type, namely Compact Type TM, Standard Type TM or Enhanced Type TM. Although similar in nature, the different TM types vary in their feature complexity. The common features to all of the Compact, Standard and Enhanced TMs will be described in this section, the detailed operation regarding each of the TM types will be described in separate sections. The main features and differences between the three types of TMs are summarised in the accompanying table. Function Timer/Counter I/P Capture Compare Match Output PWM Channels Single Pulse Output PWM Alignment PWM Adjustment Period & Duty CTM Ö ¾ Ö 1 ¾ Edge Duty or Period STM Ö Ö Ö 1 1 Edge Duty or Period ETM Ö Ö Ö 2 2 Edge & Centre Duty or Period TM Function Summary Each device in the series contains a specific number of either Compact Type, Standard Type and Enhanced Type TM units which are shown in the table together with their individual reference name, TM0~TM2. Device BS85B12-3 BS85C20-3 TM0 10-bit CTM 10-bit CTM TM1 10-bit ETM 10-bit ETM TM2 ¾ 10-bit STM TM Name/Type Reference TM Operation The three different types of TM offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. Rev. 1.00 57 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the TnCK2~TnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external TCKn pin. Note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the TM clock source. The TCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact and Standard type TMs each have two internal interrupts, one for each of the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. As the Enhanced type TM has three internal comparators and comparator A or comparator B or comparator P compare match functions, it consequently has three internal interrupts. When a TM interrupt is generated it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label TCKn. The TM input pin, is essentially a clock source for the TM and is selected using the TnCK2~TnCK0 bits in the TMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the TnCK2~TnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one or more output pins with the label TPn. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external TPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type and device is different, the details are provided in the accompanying table. All TM output pin names have an ²_n² suffix. Pin names that include a ²_1² or ²_2² suffix indicate that they are from a TM with multiple output pins. This allows the TM to generate a complimentary output pair, selected using the I/O register data bits. Device BS85B12-3 BS85C20-3 CTM TP0_0, TP0_1 TP0_0, TP0_1 STM ¾ TP2_0, TP2_1 TM Output Pins ETM TP1A, TP1B_0, TP1B_1, TP1B_2 TP1A, TP1B_0, TP1B_1, TP1B_2 Registers TMPC0 TMPC0, TMPC1 Rev. 1.00 58 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver TM Input/Output Pin Control Registers Selecting to have a TM input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. Bit Registers TMPC0 TMPC0 All BS85C20-3 Device 7 T1ACP0 ¾ 6 T1BCP2 ¾ 5 T1BCP1 ¾ 4 T1BCP0 ¾ 3 ¾ ¾ 2 ¾ ¾ 1 T0CP1 T2CP1 0 T0CP0 T2CP0 TM Input/Output Pin Control Registers List TMPC0 Register -- All devices Bit Name R/W POR Bit 7 7 T1ACP0 R/W 1 6 T1BCP2 R/W 0 5 T1BCP1 R/W 0 4 T1BCP0 R/W 1 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T0CP1 R/W 0 0 T0CP0 R/W 1 Bit 6 Bit 5 Bit 4 T1ACP0: TP1A pin Control 0: disable 1: enable T1BCP2: TP1B_2 pin Control 0: disable 1: enable T1BCP1: TP1B_1 pin Control 0: disable 1: enable T1BCP0: TP1B_0 pin Control 0: disable 1: enable Unimplemented, read as ²0² T0CP1: TP0_1 pin Control 0: disable 1: enable T0CP0: TP0_0 pin Control 0: disable 1: enable TMPC1 Register -- BS85C20-3 Bit 3~2 Bit 1 Bit 0 Bit Name R/W POR Bit 7~2 Bit 1 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 4 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 T2CP1 R/W 0 0 T2CP0 R/W 1 Bit 0 Unimplemented, read as ²0² T2CP1: TP2_1 pin control 0: disable 1: enable T2CP0: TP2_0 pin control 0: disable 1: enable Rev. 1.00 59 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver P B 0 o r P C 0 O u tp u t F u n c tio n 0 1 PB0 orPC 0 P B 1 o r P C 1 O u tp u t F u n c tio n O u tp u t 0 1 PB1 orPC 1 TM 0 (C T M ) T C K In p u t 1 T0C P1 TCK0 0 TP0_1 PB1 orPC 1 1 T0C P0 0 TP0_0 PB0 orPC 0 PA4 orPC4 TM0 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. P B 1 o r P E 1 O u tp u t F u n c tio n 0 1 0 1 PB1 orPE1 P B 2 o r P E 2 O u tp u t F u n c tio n 0 1 0 1 PB2 orPE2 1 0 T2C P1 1 0 T2C P0 T C K In p u t C a p tu re In p u t TM 2 (S T M ) O u tp u t TP2_0 PB1 orPE1 T2C P0 TP2_1 PB2 orPE2 T2C P1 PC 6 orPD 0 TM2 Function Pin Control Block Diagram -- BS85C20-3 only Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 1.00 60 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver P B 5 o r P C 5 O u tp u t F u n c tio n C C R A O u tp u t 1 T1AC P0 C C R A C a p tu re In p u t 0 T1AC P0 1 0 TP1A PB5 orPC5 P B 2 o r P C 2 O u tp u t F u n c tio n 0 1 TP1B_0 PB2 orPC2 0 1 PB2 orPC2 PB3 orPC3 T1BC P0 O u tp u t F u n c tio n 0 1 0 1 TP1B_1 PB3 orPC3 T1BC P1 TM 1 (E T M ) PB3 orPC3 P B 4 o r P C 4 O u tp u t F u n c tio n 0 1 C C R B O u tp u t 0 1 PB4 orPC4 T1BC P2 1 0 T1BC P2 1 0 T1BC P1 1 0 T1BC P0 P A 4 /T C K 1 PB4 orPC4 C C R B C a p tu re In p u t T C K In p u t TM1 Function Pin Control Block Diagram Note: 1. The I/O register data bits shown are used for TM output inversion control. 2. In the Capture Input Mode, the TM pin control register must never enable more than one TM input. Rev. 1.00 61 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRB registers, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. TM Counter Register (Read only) TMxDL 8-bit Buffer TMxDH TMxAL TMxAH TM CCRA Register (Read/Write) TMxBL TMxBH Data Bus TM CCRB Register (Read/Write) As the CCRA and CCRB registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to use the ²MOV² instruction to access the CCRA and CCRB low byte registers, named TMxAL and TMxBL, using the following access procedures. Accessing the CCRA or CCRB low byte registers without following these access procedures will result in unpredictable values. The following steps show the read and write procedures: · Writing Data to CCRB or CCRA ¨ Step ¨ Step 1. Write data to Low Byte TMxAL or TMxBL - note that here data is only written to the 8-bit buffer. 2. Write data to High Byte TMxAH or TMxBH - here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. · Reading Data from the Counter Registers and CCRB or CCRA ¨ Step 1. Read data from the High Byte TMxDH, TMxAH or TMxBH - here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. 2. Read data from the Low Byte TMxDL, TMxAL or TMxBL - this step reads data from the 8-bit buffer. ¨ Step Rev. 1.00 62 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Compact Type TM - CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one or two external output pins. These two external output pins can be the same signal or the inverse signal. CTM BS85B12-3 BS85C20-3 Name 10-bit CTM 10-bit CTM TM No. 0 0 TM Input Pin TCK0 TCK0 TM Output Pin TP0_0, TP0_1 TP0_0, TP0_1 Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. CCRP 3 - b it C o m p a r a to r P C o m p a ra to r P M a tc h T n P F In te rru p t Y S /4 fS Y S fH /1 6 fH /6 4 fT B C R e s e rv e d fS 000 001 010 011 100 101 110 111 TnO N TnPAU b7~b9 TnO C TPn_0 TPn_1 1 0 - b it C o u n t- u p C o u n te r C o u n te r C le a r 0 1 O u tp u t C o n tro l P o la r ity C o n tro l T P n P in O u tp u t TCKn b0~b9 TnC CLR TnM 1,TnM 0 T n IO 1 , T n IO 0 TnPO L 1 0 - b it C o m p a r a to r A TnC K2~TnC K0 CCRA C o m p a ra to r A M a tc h T n A F In te rru p t Compact Type TM Block Diagram Rev. 1.00 63 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Compact Type TM Register Description Overall operation of the Compact TM is controlled using six registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name TMnC0 TMnC1 TMnDL TMnDH TMnAL TMnAH Bit7 TnPAU TnM1 D7 ¾ D7 ¾ Bit6 TnCK2 TnM0 D6 ¾ D6 ¾ Bit5 TnCK1 TnIO1 D5 ¾ D5 ¾ Bit4 TnCK0 TnIO0 D4 ¾ D4 ¾ Bit3 TnON TnOC D3 ¾ D3 ¾ Bit2 TnRP2 TnPOL D2 ¾ D2 ¾ Bit1 TnRP1 TnDPX D1 D9 D1 D9 Bit0 TnRP0 TnCCLR D0 D8 D0 D8 Compact TM Register List (n=0) TMnDL Register Bit Name R/W POR Bit 7~0 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0 TMnDL: TMn Counter Low Byte Register bit 7 ~ bit 0 TMn 10-bit Counter bit 7 ~ bit 0 TMnDH Register Bit Name R/W POR Bit 7~2 Bit 1~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R 0 0 D8 R 0 Unimplemented, read as ²0² TMnDH: TMn Counter High Byte Register bit 1 ~ bit 0 TMn 10-bit Counter bit 9 ~ bit 8 TMnAL Register Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 TMnAL: TMn CCRA Low Byte Register bit 7 ~ bit 0 TMn 10-bit CCRA bit 7 ~ bit 0 Rev. 1.00 64 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver TMnAH Register Bit Name R/W POR Bit 7~2 Bit 1~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R/W 0 0 D8 R/W 0 unimplemented, read as ²0² TMn 10-bit CCRA bit 9 ~ bit 8 TMnC0 Register Bit Name R/W POR Bit 7 7 TnPAU R/W 0 6 TnCK2 R/W 0 5 TnCK1 R/W 0 4 TnCK0 R/W 0 3 TnON R/W 0 2 TnRP2 R/W 0 1 TnRP1 R/W 0 0 TnRP0 R/W 0 Bit 6~4 Bit 3 TnPAU: TMn Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. TnCK2~TnCK0: Select TMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: undefined 110: TCKn rising edge clock 111: TCKn falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. TnON: TMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the TnOC bit, when the TnON bit changes from low to high. Rev. 1.00 65 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Bit 2~0 TnRP2~TnRP0: TMn CCRP 3-bit register, compared with the TMn Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TMn clocks 001: 128 TMn clocks 010: 256 TMn clocks 011: 384 TMn clocks 100: 512 TMn clocks 101: 640 TMn clocks 110: 768 TMn clocks 111: 896 TMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the TnCCLR bit is set to zero. Setting the TnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TMnC1 Register Bit Name R/W POR Bit 7~6 7 TnM1 R/W 0 6 TnM0 R/W 0 5 TnIO1 R/W 0 4 TnIO0 R/W 0 3 TnOC R/W 0 2 TnPOL R/W 0 1 TnDPX R/W 0 0 TnCCLR R/W 0 Bit 5~4 TnM1~TnM0: Select TMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the TnM1 and TnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. TnIO1~TnIO0: Select TPn_0, TPn_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/counter Mode unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the TnOC bit in the TMnC1 register. Note that the output level requested by the TnIO1 and TnIO0 bits must be different from the initial value setup using the TnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the TnON bit from low to high. Rev. 1.00 66 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver In the PWM Mode, the TnIO1 and TnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the TnIO1 and TnIO0 bits only after the TMn has been switched off. Unpredictable PWM outputs will occur if the TnIO1 and TnIO0 bits are changed when the TM is running TnOC: TPn_0, TPn_1 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 TnPOL: TPn_0, TPn_1 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TPn_0 or TPn_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. TnDPX: TMn PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. TnCCLR: Select TMn Counter clear condition 0: TMn Comparatror P match 1: TMn Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the TnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The TnCCLR bit is not used in the PWM Mode. Bit 3 Bit 1 Bit 0 Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to ²00² respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. Rev. 1.00 67 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the TnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin will change state. The TM output pin condition however only changes state when an TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Counter Value 0x3FF CCRP Pause Stop Counter overflow CCRP=0 TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value Resume Counter Restart CCRP > 0 CCRA Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0, a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.00 68 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value 0x3FF Resume TnCCLR = 1; TnM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0 Stop Counter Restart CCRA = 0 Counter overflow CCRA CCRP Pause Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated Output does not change Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode -- TnCCLR = 1 Note: 1. With TnCCLR=1, a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. Rev. 1.00 69 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. Counter Value Counter cleared by CCRP Pause Resume TnDPX = 0; TnM [1:0] = 10 Counter Reset when TnON returns high Counter Stop if TnON bit low CCRP CCRA Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode -- TnDPX = 0 Note: 1. Here TnDPX=0 -- Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.00 70 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver CTM, PWM Mode, Edge-aligned Mode, T0DPX=0 CCRP Period Duty 001b 128 010b 256 011b 384 100b 512 CCRA 101b 640 110b 768 111b 896 000b 1024 If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128, The CTM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. CTM, PWM Mode, Edge-aligned Mode, T0DPX=1 CCRP Period Duty 128 256 384 512 001b 010b 011b 100b CCRA 640 768 896 1024 101b 110b 111b 000b The output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Counter Value Counter cleared by CCRA Pause Resume TnDPX = 1; TnM [1:0] = 10 Counter Reset when TnON returns high Counter Stop if TnON bit low CCRA CCRP Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Mode -- TnDPX = 1 Note: 1. Here TnDPX = 1 -- Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.00 71 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Standard Type TM - STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with an external input pin and can drive one or two external output pins. CTM BS85B12-3 BS85C20-3 Name ¾ 10-bit STM TM No. ¾ 2 TM Input Pin ¾ TCK2 TM Output Pin ¾ TP2_0, TP2_1 Standard TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. CCRP 3 - b it C o m p a r a to r P C o m p a ra to r P M a tc h T n P F In te rru p t fS YS /4 YS fS fH /1 6 fH /6 4 fT B C R e s e rv e d TCKn 000 001 010 011 100 101 110 111 TnO N TnPAU b7~b9 TnO C TPn_ TPn_ 1 0 - b it C o u n t- u p C o u n te r C o u n te r C le a r 1 TnC CLR 0 O u tp u t C o n tro l P o la r ity C o n tro l T P n P in In p u t/O u tp u t b0~b9 TnM 1,TnM 0 T n IO 1 , T n IO 0 TnPO L 1 0 - b it C o m p a r a to r A C o m p a ra to r A M a tc h T n IO 1 , T n IO 0 T n A F In te rru p t TnC K2~TnC K0 CCRA Edge D e te c to r Standard Type TM Block Diagram Rev. 1.00 72 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. STM Register List Name TM2C0 TM2C1 TM2DL TM2DH TM2AL TM2AH Bit7 T2PAU T2M1 D7 ¾ D7 ¾ Bit6 T2CK2 T2M0 D6 ¾ D6 ¾ Bit5 T2CK1 T2IO1 D5 ¾ D5 ¾ Bit4 T2CK0 T2IO0 D4 ¾ D4 ¾ Bit3 T2ON T2OC D3 ¾ D3 ¾ Bit2 T2RP2 T2POL D2 ¾ D2 ¾ Bit1 T2RP1 T2DPX D1 D9 D1 D9 Bit0 T2RP0 T2CCLR D0 D8 D0 D8 10-bit Standard TM Register List TM2C0 Register Bit Name R/W POR Bit 7 7 T2PAU R/W 0 6 T2CK2 R/W 0 5 T2CK1 R/W 0 4 T2CK0 R/W 0 3 T2ON R/W 0 2 T2RP2 R/W 0 1 T2RP1 R/W 0 0 T2RP0 R/W 0 Bit 6~4 Bit 3 T2PAU: TM2 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T2CK2~T2CK0: Select TM2 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: undefined 110: TCK2 rising edge clock 111: TCK2 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. T2ON: TM2 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T2OC bit, when the T2ON bit changes from low to high. Rev. 1.00 73 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Bit 2~0 T2RP2~T2RP0: TM2 CCRP 3-bit register, compared with the TM2 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM2 clocks 001: 128 TM2 clocks 010: 256 TM2 clocks 011: 384 TM2 clocks 100: 512 TM2 clocks 101: 640 TM2 clocks 110: 768 TM2 clocks 111: 896 TM2 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the T2CCLR bit is set to zero. Setting the T2CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. TM2C1 Register Bit Name R/W POR Bit 7~6 7 T2M1 R/W 0 6 T2M0 R/W 0 5 T2IO1 R/W 0 4 T2IO0 R/W 0 3 T2OC R/W 0 2 T2POL R/W 0 1 T2DPX R/W 0 0 T2CCLR R/W 0 Bit 5~4 T2M1~T2M0: Select TM2 Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T2M1 and T2M0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T2IO1~T2IO0: Select TP2_0, TP2_1 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP2_0, TP2_1 01: Input capture at falling edge of TP2_0, TP2_1 10: Input capture at falling/rising edge of TP2_0, TP2_1 11: Input capture disabled Timer/counter Mode: Unused Rev. 1.00 74 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T2OC bit in the TM2C1 register. Note that the output level requested by the T2IO1 and T2IO0 bits must be different from the initial value setup using the T2OC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T2ON bit from low to high. In the PWM Mode, the T2IO1 and T2IO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T2IO1 and T2IO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T2IO1 and T2IO0 bits are changed when the TM is running Bit 3 T2OC: TP2_0, TP2_1 Output control bit Compare Match Output Mode 0: initial low 1: initial high PWM Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. T2POL: TP2_0, TP2_1 Output polarity Control 0: non-invert 1: invert This bit controls the polarity of the TP2_0 or TP2_1 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T2DPX: TM1 PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. T2CCLR: Select TM1 Counter clear condition 0: TM2 Comparatror P match 1: TM2 Comparatror A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the T2CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T2CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Bit 2 Bit 1 Bit 0 Rev. 1.00 75 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver TM2DL Register Bit Name R/W POR Bit 7~0 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0 TM2DL: TM2 Counter Low Byte Register bit 7~bit 0 TM2 10-bit Counter bit 7~bit 0 TM2DH Register Bit Name R/W POR Bit 7~2 Bit 1~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R 0 0 D8 R 0 Unimplemented, read as ²0² TM2DH: TM2 Counter High Byte Register bit 1~bit 0 TM2 10-bit Counter bit 9~bit 8 TM2AL Register Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 TM2AL: TM2 CCRA Low Byte Register bit 7~bit 0 TM2 10-bit CCRA bit 7~bit 0 TM2AH Registe Bit Name R/W POR Bit 7~2 Bit 1~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R/W 0 0 D8 R/W 0 Unimplemented, read as ²0² TM2AH: TM2 CCRA High Byte Register bit 1~bit 0 TM2 10-bit CCRA bit 9~bit 8 Rev. 1.00 76 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnM1 and TnM0 bits in the TMnC1 register. Compare Match Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to 0. Counter Value 0x3FF CCRP Pause Stop Counter overflow CCRP=0 TnCCLR = 0; TnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value Resume Counter Restart CCRP > 0 CCRA Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to itsinitial state by a TnON bit rising edge Rev. 1.00 77 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a TnAF interrupt request flag is generated after a compare match occurs from Comparator A. The TnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the TnIO1 and TnIO0 bits in the TMnC1 register. The TM output pin can be selected using the TnIO1 and TnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero then no pin change will take place. Timer/Counter Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. Counter Value 0x3FF Resume TnCCLR = 1; TnM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0 Stop Counter Restart CCRA = 0 Counter overflow CCRA CCRP Pause Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated Output does not change Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow TM O/P Pin Output pin set to initial Level Low if TnOC=0 Output Toggle with TnAF flag Here TnIO [1:0] = 11 Toggle Output select Output Inverts when TnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode -- TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TM output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge 4. A TnPF flag is not generated when TnCCLR=1 Rev. 1.00 78 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver PWM Output Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the TnDPX bit in the TMnC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The TnOC bit in the TMnC1 register is used to select the required polarity of the PWM waveform while the two TnIO1 and TnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnPOL bit is used to reverse the polarity of the PWM output waveform. · STM, PWM Mode, Edge-aligned Mode, T0DPX=0 001b 128 010b 256 011b 384 100b 512 CCRA 101b 640 110b 768 111b 896 000b 1024 CCRP Period Duty If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b and CCRA =128, The STM PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. · STM, PWM Mode, Edge-aligned Mode, T0DPX=1 001b 010b 011b 100b CCRA 128 256 384 512 640 768 896 1024 101b 110b 111b 000b CCRP Period Duty The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.00 79 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value Counter cleared by CCRP Pause Resume TnDPX = 0; TnM [1:0] = 10 Counter Reset when TnON returns high Counter Stop if TnON bit low CCRP CCRA Time TnON TnPAU TnPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM Duty Cycle set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Period set by CCRP PWM Mode -- TnDPX = 0 Note: 1. Here TnDPX=0 ¡V Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Rev. 1.00 80 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value Counter cleared by CCRA Pause Resume TnDPX = 1; TnM [1:0] = 10 Counter Reset when TnON returns high Counter Stop if TnON bit low CCRA CCRP Time TnON TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) PWM resumes operation Output controlled by Output Inverts other pin-shared function when TnPOL = 1 PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM Mode -- TnDPX = 1 Note: 1. Here TnDPX=1 -- Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when TnIO [1:0] = 00 or 01 4. The TnCCLR bit has no influence on PWM operation Single Pulse Mode To select this mode, bits TnM1 and TnM0 in the TMnC1 register should be set to 10 respectively and also the TnIO1 and TnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. Rev. 1.00 81 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Com m and S E T "T n O N " or T C K n P in T r a n s itio n S /W L e a d in g E d g e T n O N b it 0® 1 T r a ilin g E d g e T n O N b it 1® 0 S /W C o m m a n d C L R "T n O N " or C C R A M a tc h C o m p a re T M n O u tp u t P in P u ls e W id th = C C R A V a lu e Single Pulse Generation However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR and TnDPX bits are not used in this Mode. Counter Value Counter stopped by CCRA Resume TnM [1:0] = 10 ; TnIO [1:0] = 11 Counter Reset when TnON returns high Pause Counter Stops by software CCRA CCRP Time TnON Software Trigger Cleared by CCRA match Auto. set by TCKn pin Software Trigger Software Trigger Software Clear Software Trigger TCKn pin TnPAU TnPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF No CCRP Interrupts generated TCKn pin Trigger TM O/P Pin (TnOC=1) TM O/P Pin (TnOC=0) Pulse Width set by CCRA Output Inverts when TnPOL = 1 Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high 5. In the Single Pulse Mode, TnIO [1:0] must be set to ²11² and can not be changed. Rev. 1.00 82 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Capture Input Mode To select this mode bits TnM1 and TnM0 in the TMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPn_0 or TPn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnIO1 and TnIO0 bits in the TMnC1 register. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPn_0 or TPn_1 pin, the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the TPn_0 or TPn_1 pin the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs, the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnIO1 and TnIO0 bits can select the active trigger edge on the TPn_0 or TPn_1 pin to be a rising edge, falling edge or both edge types. If the TnIO1 and TnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPn_0 or TPn_1 pin, however it must be noted that the counter will continue to run. As the TPn_0 or TPn_1 pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR and TnDPX bits are not used in this Mode. Counter Value Counter cleared by CCRP TnM [1:0] = 01 Counter Counter Stop Reset CCRP YY XX Time TnON TnPAU Active edge Resume Pause TM capture pin TPn_x CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnIO [1:0] Value 00 Rising edge Active edge Active edge XX YY XX YY 01 Falling edge 10 Both edges 11 Disable Capture Capture Input Mode Note: 1.. TnM [1:0] = 01 and active edge set by the TnIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. TnCCLR bit not used 4. No output function -- TnOC and TnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 83 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Enhanced Type TM - ETM The Enhanced Type TM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Enhanced TM can also be controlled with an external input pin and can drive three or four external output pins. CTM BS85B12-3 BS85C20-3 Name 10-bit ETM 10-bit ETM TM No. 1 1 TM Input Pin TCK1 TCK1 TM Output Pin TP1A, TP1B_0, TP1B_1, TP1B_2 TP1A, TP1B_0, TP1B_1, TP1B_2 Enhanced TM Operation At its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. There are three internal comparators with the names, Comparator A, Comparator B and Comparator P. These comparators will compare the value in the counter with the CCRA, CCRB and CCRP registers. The CCRP comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while CCRA and CCRB are 10-bits wide and therefore compared with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the TnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Enhanced Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. All operating setup conditions are selected using relevant internal registers. CCRP C o m p a ra to r P M a tc h 3 - b it C o m p a r a to r P T n P F In te rru p t fS YS /4 YS fS fH /1 6 fH /6 4 fT B C R e s e rv e d TCKn 000 001 010 011 100 101 110 111 b7~b9 TnAO C 1 0 - b it U p /D o w n C o u n te r C o u n te r C le a r 0 1 TnC CLR O u tp u t C o n tro l P o la r ity C o n tro l T P n A P in In p u t/O u tp u t TPnA TnO N TnPAU b0~b9 TnAM 1,TnAM 0 T n A IO 1 , T n A IO 0 TnAPO L TnC K2~TnC K0 1 0 - b it C o m p a ra to r A C o m p a ra to r A M a tc h TnAF In te rru p t T n A IO 1 , T n A IO 0 CCRA Edge D e te c to r TnBO C T P n B -0 T P n B -1 T P n B -2 1 0 - b it C o m p a ra to r B C o m p a ra to r B M a tc h TnBF In te rru p t Edge D e te c to r O u tp u t C o n tro l P o la r ity C o n tro l T P n B P in In p u t/O u tp u t CCRB TnBM 1,TnBM 0 T n B IO 1 , T n B IO 0 TnBPO L T n IO 1 , T n IO 0 Enhanced Type TM Block Diagram Rev. 1.00 84 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Enhanced Type TM Register Description Overall operation of the Enhanced TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRB value. The remaining three registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Name TM1C0 TM1C1 TM1C2 TM1DL TM1DH TM1AL TM1AH TM1BL TM1BH Bit7 T1PAU T1AM1 T1BM1 D7 ¾ D7 ¾ D7 ¾ Bit6 T1CK2 T1AM0 T1BM0 D6 ¾ D6 ¾ D6 ¾ Bit5 T1CK1 T1AIO1 T1BIO1 D5 ¾ D5 ¾ D5 ¾ Bit4 T1CK0 T1AIO0 T1BIO0 D4 ¾ D4 ¾ D4 ¾ Bit3 T1ON T1AOC T1BOC D3 ¾ D3 ¾ D3 ¾ Bit2 T1RP2 T1APOL T1BPOL D2 ¾ D2 ¾ D2 ¾ Bit1 T1RP1 T1CDN T1PWM1 D1 D9 D1 D9 D1 D9 Bit0 T1RP0 T1CCLR T1PWM0 D0 D8 D0 D8 D0 D8 10-bit Enhanced TM Register List (if ETM is TM1) 10-bit Enhanced TM Register List · TM1C0 Register -- 10-bit ETM 7 6 T1CK2 R/W 0 5 T1CK1 R/W 0 4 T1CK0 R/W 0 3 T1ON R/W 0 2 T1RP2 R/W 0 1 T1RP1 R/W 0 0 T1RP0 R/W 0 Bit Name R/W POR Bit 7 T1PAU R/W 0 Bit 6~4 T1PAU: TM1 Counter Pause Control 0: run 1: pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. T1CK2~T1CK0: Select TM1 Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: Undefined 110: TCK1 rising edge clock 111: TCK1 falling edge clock These three bits are used to select the clock source for the TM. Selecting the Reserved clock input will effectively disable the internal counter. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Rev. 1.00 85 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Bit 3 T1ON: TM1 Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the T1OC bit, when the T1ON bit changes from low to high. T1RP2~T1RP0: TM1 3-bit register, compared with the TM1 Counter bit 9~bit 7 Comparator P Match Period 000: 1024 TM1 clocks 001: 128 TM1 clocks 010: 256 TM1 clocks 011: 384 TM1 clocks 100: 512 TM1 clocks 101: 640 TM1 clocks 110: 768 TM1 clocks 111: 896 TM1 clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter¢s highest three bits. The result of this comparison can be selected to clear the internal counter if the T1CCLR bit is set to zero. Setting the T1CCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. · Bit 2~0 TM1C1 Register -- 10-bit ETM 7 6 T1AM0 R/W 0 5 T1AIO1 R/W 0 4 T1AIO0 R/W 0 3 T1AOC R/W 0 2 T1APOL R/W 0 1 T1CDN R 0 0 T1CCLR R/W 0 Bit Name R/W POR Bit 7~6 T1AM1 R/W 0 Bit 5~4 T1AM1~T1AM0: Select TM1 CCRA Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1AM1 and T1AM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T1AIO1~T1AIO0: Select TP1A output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output Mode/ Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1A 01: Input capture at falling edge of TP1A 10: Input capture at falling/rising edge of TP1A 11: Input capture disabled Rev. 1.00 86 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1AOC bit in the TM1C1 register. Note that the output level requested by the T1AIO1 and T1AIO0 bits must be different from the initial value setup using the T1AOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1AIO1 and T1AIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1AIO1 and T1AIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1AIO1 and T1AIO0 bits are changed when the TM is running T1AOC: TP1A Output control bit Compare Match Output Mode 0: Initial low 1: Initial high Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. T1APOL: TP1A Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1A output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T1CDN: TM1 Counter count up or down flag 0: Count up 1: Count down T1CCLR: Select TM1 Counter clear condition 0: TM1 Comparator P match 1: TM1 Comparator A match This bit is used to select the method which clears the counter. Remember that the Enhanced TM contains three comparators, Comparator A, Comparator B and Comparator P, but only Comparator A or Comparator Pan be selected to clear the internal counter. With the T1CCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.00 87 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver · TM1C2 Register -- 10-bit ETM 7 6 T1BM0 R/W 0 5 T1BIO1 R/W 0 4 T1BIO0 R/W 0 3 T1BOC R/W 0 2 T1BPOL R/W 0 1 T1PWM1 R 0 0 T1PWM0 R/W 0 Bit Name R/W POR Bit 7~6 T1BM1 R/W 0 Bit 5~4 T1BM1~T1BM0: Select TM1 CCRB Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the T1BM1 and T1BM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. T1BIO1~T1BIO0: Select TP1B_0, TP1B_1, TP1B_2 output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of TP1B_0, TP1B_1, TP1B_2 01: Input capture at falling edge of TP1B_0, TP1B_1, TP1B_2 10: Input capture at falling/rising edge of TP1B_0, TP1B_1, TP1B_2 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the T1BOC bit in the TM1C2 register. Note that the output level requested by the T1BIO1 and T1BIO0 bits must be different from the initial value setup using the T1BOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the T1ON bit from low to high. In the PWM Mode, the T1BIO1 and T1BIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the T1BIO1 and T1BIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the T1BIO1 and T1BIO0 bits are changed when the TM is running Rev. 1.00 88 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Bit 3 T1BOC: TP1B_0, TP1B_1, TP1B_2 Output control bit Compare Match Output Mode 0: Initial low 1: Initial high Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. T1BPOL: TP1B_0, TP1B_1, TB1B_2 Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TP1B_0, TP1B_1, TP1B_2 output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. T1PWM1~T1PWM0: Select PWM Mode 00: Edge aligned 01: Centre aligned, compare match on count up 10: Centre aligned, compare match on count down 11: Centre aligned, compare match on count up or down · Bit 2 Bit 1~0 TM1DL Register -- 10-bit ETM 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0 Bit Name R/W POR Bit 7~0 · TM1DL: TM1 Counter Low Byte Register bit 7~bit 0 TM1 10-bit Counter bit 7~bit 0 TM1DH Register -- 10-bit ETM 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R 0 0 D8 R 0 Bit Name R/W POR Bit 7~2 Unimplemented, read as ²0² Bit 1~0 · TM1DH: TM1 Counter High Byte Register bit 1~bit 0 TM1 10-bit Counter bit 9~bit 8 TM1AL Register -- 10-bit ETM 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit Name R/W POR Bit 7~0 TM1AL: TM1 Low Byte Register bit 7~bit 0 TM1 10-bit CCRA bit 7~bit 0 Rev. 1.00 89 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver · TM1AH Register -- 10-bit ETM 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R/W 0 0 D8 R/W 0 Bit Name R/W POR Bit 7~2 Bit 1~0 · Unimplemented, read as ²0² TM1AH: TM1 High Byte Register bit 1~bit 0 TM1 10-bit CCRA bit 9~bit 8 TM1BL Register -- 10-bit ETM 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 Bit Name R/W POR Bit 7 ~ 0 · TM1BL: TM1 Low Byte Register bit 7~bit 0 TM1 10-bit CCRB bit 7~bit 0 TM1BH Register -- 10-bit ETM 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 ¾ ¾ ¾ 2 ¾ ¾ ¾ 1 D9 R/W 0 0 D8 R/W 0 Bit Name R/W POR Bit 7~2 Bit 1~0 Unimplemented, read as ²0² TM1BH: TM1 High Byte Register bit 1~bit 0 TM1 10-bit CCRB bit 9 ~ bit 8 Enhanced Type TM Operating Modes The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and TnBM0 bits in the TMnC2 register. CCRA CCRA CCRA Single CCRA Input Compare CCRA PWM Timer/Count Pulse Output Capture Match Output Mode er Mode Mode Mode Output Mode Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ¾ ¾ ¾ ¾ ¾ Ö ETM Operating Mode CCRB Compare Match Output Mode CCRB Timer/Counter Mode CCRB PWM Output Mode CCRB Single Pulse Output Mode CCRB Input Capture Mode ²Ö²: permitted; ²¾² : not permitted Rev. 1.00 90 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Compare Output Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match occurs from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the TnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when TnCCLR is high no TnPF interrupt request flag will be generated. Counter Value 0x3FF CCRP Counter overflow CCRP=0 TnCCLR = 0; TnAM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value Resume Pause Stop Counter Restart CCRP > 0 CCRA Time TnON TnPAU TnAPOL CCRP Int. Flag TnPF CCRA Int. Flag TnAF TPnA O/P Pin Output pin set to initial Level Low if TnAOC=0 Output Toggle with TnAF flag Here TnAIO [1:0] = 11 Toggle Output select Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnAIO [1:0] = 10 Active High Output select Output Inverts when TnAPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function ETM CCRA Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TPnA output pin is controlled only by the TnAF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.00 91 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when an TnAF or TnBF interrupt request flag is generated after a compare match occurs from Comparator A or Comparator B. The TnPF interrupt request flag, generated from a compare match from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state is determined by the condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1 and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using the TnAIO1, TnAIO0 bits (for the TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0, TPnB_1 or TPnB_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A or a compare match occurs from Comparator B. The initial condition of the TM output pin, which is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are zero then no pin change will take place. Counter Value 0x3FF CCRP Pause Stop Counter overflow CCRP=0 TnCCLR = 0; TnBM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value Resume Counter Restart CCRP > 0 CCRB Time TnON TnPAU TnBPOL CCRP Int. Flag TnPF CCRB Int. Flag TnBF TPnB O/P Pin Output pin set to initial Level Low if TnBOC=0 Output Toggle with TnBF flag Here TnBIO [1:0] = 11 Toggle Output select Output not affected by TnBF flag. Remains High until reset by TnON bit Note TnBIO [1:0] = 10 Active High Output select Output Inverts when TnBPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function ETM CCRB Compare Match Output Mode -- TnCCLR = 0 Note: 1. With TnCCLR=0 a Comparator P match will clear the counter 2. The TPnB output pin is controlled only by the TnBF flag 3. The output pin is reset to its initial state by a TnON bit rising edge Rev. 1.00 92 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value 0x3FF Resume TnCCLR = 1; TnAM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0 Stop Counter Restart CCRA = 0 Counter overflow CCRA CCRP Pause Time TnON TnPAU TnAPOL CCRA Int. Flag TnAF CCRP Int. Flag TnPF TnPF not generated Output does not change Output not affected by TnAF flag. Remains High until reset by TnON bit Note TnAIO [1:0] = 10 Active High Output select No TnAF flag generated on CCRA overflow TPnA O/P Pin Output pin set to initial Level Low if TnAOC=0 Output Toggle with TnAF flag Here TnAIO [1:0] = 11 Toggle Output select Output Inverts when TnAPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function ETM CCRA Compare Match Output Mode -- TnCCLR = 1 Note: 1. With TnCCLR=1 a Comparator A match will clear the counter 2. The TPnA output pin is controlled only by the TnAF flag 3. The TPnA output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 1.00 93 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value 0x3FF Resume TnCCLR = 1; TnBM [1:0] = 00 CCRA > 0 Counter cleared by CCRA value CCRA=0 Stop Counter Restart CCRA = 0 Counter overflow CCRA CCRB Pause Time TnON TnPAU TnBPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF No TnAF flag generated on CCRA overflow TPnB O/P Pin Output pin set to initial Level Low if TnBOC=0 Output Toggle with TnBF flag Output not affected by TnBF flag. Remains High until reset by TnON bit Note TnBIO [1:0] = 10 Active High Output select Output Inverts when TnBPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Here TnBIO [1:0] = 11 Toggle Output select ETM CCRB Compare Match Output Mode -- TnCCLR = 1 1. With TnCCLR=1 a Comparator A match will clear the counter Note: 2. The TPnB output pin is controlled only by the TnBF flag 3. The TPnB output pin is reset to its initial state by a TnON bit rising edge 4. The TnPF flag is not generated when TnCCLR=1 Rev. 1.00 94 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Timer/Counter Mode To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 register should all be set high. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the TnCCLR bit is used to determine in which way the PWM period is controlled. With the TnCCLR bit set high, the PWM period can be finely controlled using the CCRA registers. In this case the CCRB registers are used to set the PWM duty value (for TPnB output pins). The CCRP bits are not used and TPnA output pin is not used. The PWM output can only be generated on the TPnB output pins. With the TnCCLR bit cleared to zero, the PWM period is set using one of the eight values of the three CCRP bits, in multiples of 128. Now both CCRA and CCRB registers can be used to setup different duty cycle values to provide dual PWM outputs on their relative TPnA and TPnB pins. The TnPWM1 and TnPWM0 bits determine the PWM alignment type, which can be either edge or centre type. In edge alignment, the leading edge of the PWM signals will all be generated concurrently when the counter is reset to zero. With all power currents switching on at the same time, this may give rise to problems in higher power applications. In centre alignment the centre of the PWM active signals will occur sequentially, thus reducing the level of simultaneous power switching currents. Interrupt flags, one for each of the CCRA, CCRB and CCRP, will be generated when a compare match occurs from either the Comparator A, Comparator B or Comparator P. The TnAOC and TnBOC bits in the TMnC1 and TMnC2 register are used to select the required polarity of the PWM waveform while the two TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits pairs are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The TnAPOL and TnBPOL bit are used to reverse the polarity of the PWM output waveform. Rev. 1.00 95 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver ETM, PWM Mode, Edge-aligned Mode, TnCCLR=0 CCRP Period A Duty B Duty 001b 128 010b 256 011b 384 100b 512 CCRA CCRB 101b 640 110b 768 111b 896 000b 1024 If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 100b, CCRA = 128 and CCRB = 256, The TP1A PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. The TP1B_n PWM output frequency = (fSYS/4) / 512 = fSYS/2048 = 7.8125kHz, duty = 256/512 = 50%. If the Duty value defined by CCRA or CCRB register is equal to or greater than the Period value, then the PWM output duty is 100%. ETM, PWM Mode, Edge-aligned Mode, TnCCLR=1 CCRA Period B Duty 1 1 2 2 3 3 511 511 CCRB 512 512 1021 1021 1022 1022 1023 1023 ETM, PWM Mode, Center-aligned Mode, TnCCLR=0 CCRP Period A Duty B Duty 001b 256 010b 512 011b 768 100b 1024 101b 1280 110b 1536 111b 1792 000b 2046 (CCRA´2)-1 (CCRB´2)-1 ETM, PWM Mode, Center-aligned Mode, TnCCLR=1 CCRA Period B Duty 1 2 2 4 3 6 511 1022 512 1024 1021 2042 1022 2044 1023 2046 (CCRB´2)-1 Rev. 1.00 96 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value Counter Cleared by CCRP CCRP CCRA Pause Resume Counter Restart TnCCLR = 0; TnAM [1:0] = 10, TnBM [1:0] = 10; TnPWM [1:0] = 00 Stop CCRB Time TnON TnPAU TnAPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnA Pin (TnAOC=1) Duty Cycle set by CCRA Duty Cycle set by CCRA Duty Cycle set by CCRA Output Inverts when TnAPOL is high TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) Duty Cycle set by CCRB Output controlled by other pin-shared function Output Pin Reset to Initial value PWM Period set by CCRP ETM PWM Mode -- Edge Aligned Note: 1. Here TnCCLR=0 therefore CCRP clears counter and determines the PWM period 2. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01 3. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty Rev. 1.00 97 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value Counter Cleared by CCRA CCRA Resume Counter Restart TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 00 Pause Stop CCRB Time TnON TnPAU TnBPOL CCRP Int. Flag TnPF CCRB Int. Flag TnBF TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) Duty Cycle set by CCRB Output controlled by other pin-shared function Output Pin Reset to Initial value Output Inverts when TnBPOL is high PWM Period set by CCRA ETM PWM Mode -- Edge Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 3. The CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 4. Here the TM pin control register should not enable the TPnA pin as a TM output pin. Rev. 1.00 98 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value TnCCLR = 0; TnAM [1:0] = 10, TnBM [1:0] = 10; TnPWM [1:0] = 11 Stop Counter Restart CCRP CCRA CCRB Resume Pause Time TnON TnPAU TnAPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnA Pin (TnAOC=1) Duty Cycle set by CCRA TPnB Pin (TnBOC=1) Output Inverts when TnAPOL is high TPnB Pin (TnBOC=0) Duty Cycle set by CCRB PWM Period set by CCRP Output controlled by Other pin-shared function Output Pin Reset to Initial value ETM PWM Mode -- Centre Aligned Note: 1. Here TnCCLR=0 therefore CCRP clears the counter and determines the PWM period 2. TnPWM [1:0] =11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnAIO [1:0] (or TnBIO [1:0]) = 00 or 01 4. CCRA controls the TPnA PWM duty and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value Rev. 1.00 99 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value TnCCLR = 0; TnAM [1:0] = 10, TnBM [1:0] = 10; TnPWM [1:0] = 11 Stop Counter Restart CCRP CCRA CCRB Resume Pause Time TnON TnPAU TnAPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF CCRP Int. Flag TnPF TPnA Pin (TnAOC=1) Duty Cycle set by CCRA TPnB Pin (TnBOC=1) Output Inverts when TnAPOL is high TPnB Pin (TnBOC=0) Duty Cycle set by CCRB PWM Period set by CCRP Output controlled by Other pin-shared function Output Pin Reset to Initial value ETM PWM Mode -- Centre Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. TnPWM [1:0] =11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value Rev. 1.00 100 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Single Pulse Output Mode To select this mode, the required bit pairs, TnAM1, TnAM0 and TnBM1, TnBM0 should be set to 10 respectively and also the corresponding TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse TPnA output leading edge is a low to high transition of the TnON bit, which can be implemented using the application program. The trigger for the pulse TPnB output leading edge is a compare match from Comparator B, which can be implemented using the application program. However in the Single Pulse Mode, the TnON bit can also be made to automatically change from low to high using the external TCKn pin, which will in turn initiate the Single Pulse output of TPnA. When the TnON bit transitions to a high level, the counter will start running and the pulse leading edge of TPnA will be generated. The TnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge of TPnA and TPnB will be generated when the TnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the TnON bit and thus generate the Single Pulse output trailing edge of TPnA and TPnB. In this way the CCRA value can be used to control the pulse width of TPnA. The CCRA-CCRB value can be used to control the pulse width of TPnB. A compare match from Comparator A and Comparator B will also generate TM interrupts. The counter can only be reset back to zero when the TnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The TnCCLR bit is also not used. Single Pulse Generation Rev. 1.00 101 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Counter Value Counter stopped by CCRA TnAM [1:0] = 10, TnBM [1:0] = 10; TnAIO [1:0] = 11, TnBIO [1:0] = 11 Counter Reset when TnON returns high CCRA Pause Resume Counter Stops by software CCRB Time TnON Software Trigger Cleared by CCRA match Auto. set by TCKn pin Software Trigger Software Trigger Software Clear Software Trigger TCKn pin TnPAU TnAPOL TnBPOL CCRB Int. Flag TnBF CCRA Int. Flag TnAF TPnA Pin (TnAOC=1) TCKn pin Trigger TPnA Pin (TnAOC=0) Pulse Width set by CCRA Output Inverts when TnAPOL=1 TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) Pulse Width set by (CCRA-CCRB) Output Inverts when TnBPOL=1 ETM -- Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the TCKn pin or by setting the TnON bit high 4. A TCKn pin active edge will automatically set the TnON bit high 5. In the Single Pulse Mode, TnAIO [1:0] and TnBIO [1:0] must be set to ²11² and can not be changed. Rev. 1.00 102 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Capture Input Mode To select this mode bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1 and TMnC2 registers should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits in the TMnC1 and TMnC2 registers. The counter is started when the TnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the present value in the counter will be latched into the CCRA and CCRB registers and a TM interrupt generated. Irrespective of what events occur on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins the counter will continue to free run until the TnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits can select the active trigger edge on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins to be a rising edge, falling edge or both edge types. If the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the TPnA and TPnB_0, TPnB_1, TPnB_2 pins, however it must be noted that the counter will continue to run. Counter Value Counter cleared by CCRP TnAM [1:0] = 01 Counter Counter Stop Reset CCRP YY XX Time TnON TnPAU Active edge Resume Pause TM capture pin TPnA CCRA Int. Flag TnAF CCRP Int. Flag TnPF CCRA Value TnAIO [1:0] Value XX Active edge Active edge YY XX YY 00 Rising edge 01 Falling edge 10 Both edges 11 Disable Capture ETM CCRA Capture Input Mode Note: 1. TnAM [1:0] = 01 and active edge set by the TnAIO [1:0] bits 2. The TM Capture input pin active edge transfers he counter value to CCRA 3. TnCCLR bit not used 4. No output function -- TnAOC and TnAPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 103 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver As the TPnA and TPnB_0, TPnB_1, TPnB_2 pins are pin shared with other functions, care must be taken if the TM is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The TnCCLR, TnAOC, TnBOC, TnAPOL and TnBPOL bits are not used in this mode. TnBM1, TnBM0 = 01 Counter Value CCRP YY XX Pause Resume Counter overflow Stop Counter Reset Time TnON bit TnPAU bit Active edge Active edge Active edges TM Capture Pin CCRB Int. Flag TnBF CCRP Int. Flag TnPF CCRB Value TnBIO1, TnBIO0 Value XX YY XX YY 00 - Rising edge 01 - Falling edge 10 - Both edges 11 - Disable Capture ETM CCRB Capture Input Mode Note: 1. TnBM [1:0] = 01 and active edge set by the TnBIO [1:0] bits 2. The TM Capture input pin active edge transfers the counter value to CCRB 3. TnCCLR bit not used 4. No output function -- TnBOC and TnBPOL bits not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 104 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Touch Key Function Each device provides multiple touch key functions. The touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The touch keys are pin shared with the PC and PD logic I/O pins, as well as having dedicated pins. For the pin shared touch keys, the touch key function is chosen using register bits. Keys are organised into groups of four, with each group known as a module and having a module number, M0 to M4. Each module contains its own control logic circuits and register set. Examination of the register names will reveal the module number it is referring to. Device Keys - n Touch Key Module M0 BS85B12-3 12 M1 M2 M0 M1 BS85C20-3 20 M2 M3 M4 Touch Key K1~K4 K5~K8 K9~K12 K1~K4 K5~K8 K9~K12 K13~K16 K17~K20 Shared I/O Pin PC0~PC3 PC4~PC7 Dedicated Pins PC0~PC3 PC4~PC7 Dedicated Pins PD0~PD3 PD4~PD7 Touch Key Module/Pin Reference Table Touch Key Register Definition Each touch key module, which contains four touch key functions, has its own suite of registers. The following table shows the register set for each touch key module. The Mn within the register name refers to the Touch Key module number and has a range of M0 to M4. Name TKMn16DH TKMn16DL TKMnC0 16-bit C/F counter high byte 16-bit C/F counter low byte Control Register 0 Key Select Control Register 1 Internal reference. Touch pad reference. Control Register 2 Counter on-off and clear control/reference clock control/TKST start bit Control Register 3 Counter overflow bits Register Listing Usage TKMnC1 TKMnC2 TKMnC3 Rev. 1.00 105 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Register Name TKMn16DH TKMn16DL TKMnC0 TKMnC1 TKMnC2 TKMnC3 Bit 7 D7 D7 MnMXS1 MnK4OEN Mn16CTON D9 6 D6 D6 MnMXS0 MnK3OEN D6 D8 5 D5 D5 D5 MnK2OEN MnST MnRCOV 4 D4 D4 D4 MnK1OEN MnROEN Mn16CTOV 3 D3 D3 D3 MnK4IO MnRCCLR D3 2 D2 D2 D2 MnK3IO Mn16CTCLR MnROVS2 1 D1 D1 D1 MnK2IO D1 MnROVS1 0 D0 D0 D0 MnK1IO MnROS MnROVS0 Register Content Summary TKMn16DH Register Bit Name R/W POR Bit 7~0 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0 Module n 16-bit counter high byte contents TKMn16DL Register Bit Name R/W POR Bit 7~0 7 D7 R 0 6 D6 R 0 5 D5 R 0 4 D4 R 0 3 D3 R 0 2 D2 R 0 1 D1 R 0 0 D0 R 0 Module n 16-bit counter low byte contents TKMnC0 Register Bit Name R/W POR Bits 7~6 7 MnMXS1 R/W 0 6 MnMXS0 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 MnMXS1, MnMXS0: Multiplexer Key Select Bit MnMXS1 0 0 1 1 MnMXS0 0 1 0 1 M0 Key 1 Key 2 Key 3 Key 4 M1 Key 5 Key 6 Key 7 Key 8 Module Number M2 Key 9 Key 10 Key 11 Key 12 M3 Key 13 Key 14 Key 15 Key 16 M4 Key 17 Key 18 Key 19 Key 20 Bit 5~0 D5~D0: These bits must be set to the binary value ²011000² Rev. 1.00 106 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver TKMnC1 Register Bit Name R/W POR Bits 7~4 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 MnK4IO R/W 0 2 MnK3IO R/W 0 1 MnK2IO R/W 0 0 MnK1IO R/W 0 MnK4OEN MnK3OEN MnK2OEN MnK1OEN For the BS85B12-3 n=0~2 while for the BS85C20-3 n=0~4. MnK4OEN~ MnK1OEN: key selector control M0 Key 4 M1 Key 8 M2 Key 12 Disable Enable M0 Key 3 M1 Key 7 M2 Key 11 Disable Enable M0 Key 2 M1 Key 6 M2 Key 10 Disable Enable M0 Key 1 M1 Key 5 M2 Key 9 Disable Enable M3 Key 13 M4 Key 17 M3 Key 14 M4 Key 18 M3 Key 15 M4 Key 19 M3 Key 16 M4 Key 20 MnK4OEN 0 1 MnK3OEN 0 1 MnK2OEN 0 1 MnK1OEN 0 1 Bits 3~0 I/O Pin or Touch Key Function Select MnK4IO 0 1 M0 PC2/Key 3 M1 PC6/Key 7 I/O pin Touch Key M0 PC1/Key 2 M1 PC5/Key 6 I/O pin Touch Key M0 PC0/Key 1 M1 PC4/Key 5 I/O pin Touch Key M3 PD0/Key 13 M4 PD4/Key 17 M3 PD1/Key 14 M4 PD5/Key 18 M0 PC3/Key 4 M1 PC7/Key 8 I/O pin Touch Key M3 PD2/Key 15 M4 PD6/Key 19 M3 PD3/Key 16 M4 PD7/Key 20 MnK3IO 0 1 MnK2IO 0 1 MnK1IO 0 1 Rev. 1.00 107 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver TKMnC2 Register Bit Name R/W POR Bit 7 7 Mn16CTON R/W 0 6 D6 R/W 0 5 MnST R/W 0 4 MnROEN R/W 0 3 MnRCCLR R/W 0 2 Mn16CTCLR R/W 0 1 D1 R/W 0 0 MnROS R/W 0 Bit 6 Bit 5 Mn16CTON: 16-bit C/F counter control 0: disable 1: enable D6: This bit must be cleared to zero. MnST: Time slot counter start control 0: time slot counter stopped 0 ® 1: enable time slot counter. When this bit changes from low to high the time slot counter will be enabled and the touch sense procedure started. When the time slot counter has completed its counting an interrupt will be generated. MnROEN: Reference clock control 0: disable 1: enable MnRCCLR: Time slot counter clear control 0: no change 1: clear counter This bit must be first set to 1 and then to 0. Mn16CTCLR: 16-bit C/F counter clear control 0: no change 1: clear counter This bit must be first set to 1 and then to 0. D1: This bit must be cleared to zero. MnROS: Time slot counter clock source 0: reference clock 1: sense key oscillator M0:K4, M1:K8, M2:K12, M3:K16, M4:K20 TKMnC3 Register Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name R/W POR Bit 7~6 Bit 5 7 D7 R 0 6 D6 R 0 5 MnRCOV R 0 4 Mn16CTOV R/W 0 3 D3 R/W 0 2 MnROVS2 R/W 0 1 MnROVS1 R/W 0 0 0 MnROVS0 R/W Bit 4 D7, D6: Read only bits -- unknown values MnRCOV: Time slot counter overflow flag 0: no overflow 1: overflow Mn16CTOV: 16-bit C/F counter overflow flag 0: no overflow 1: overflow D3: This bit must be cleared to zero. MnROVS2~MnROVS0: Time slot counter overflow time setup 000: 64 count 001: 128 count 010: 256 count 011: 512 count 100: 1024 count 101: 2048 count 110: 4096 count 111: 8192 count Bit 3 Bit 2~0 Rev. 1.00 108 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Touch Key Operation When a finger touches or is in proximity to a touch pad, the capacitance of the pad will increase. By using this capacitance variation to change slightly the frequency of the internal sense oscillator, touch actions can be sensed by measuring these frequency changes. Using an internal programmable divider the reference clock is used to generated a fixed time period. By counting the number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. Each touch key module contains four touch key inputs which are either dedicated touch key pins or are shared logical I/O pins. If shared, the desired function is selected using register bits. Each touch key has its own independent sense oscillator. There are therefore four sense oscillators within each touch key module. Each Touch Key module also has its own interrupt vector and set of interrupts flags. During this reference clock fixed interval, the number of clock cycles generated by the sense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval, a Touch Key interrupt signal will be generated. Touch Key (1 Set = Touch Key*5) Key0 Key1 Key2 Key3 C/F & Mux. Enable 16-bit C/F Counter 16-bit C/F Counter INT Flag 16-bit C/F Counter Overflow Flag Reference Clock Mux. Time Slot Counter Time Slot Counter INT flag Time Slot Counter Overflow flag Time Slot Counter Clock Select Touch Switch Module Block Diagram M n K 4 IO E x te r n a l P in orTouch K ey M n K 3 IO E x te r n a l P in orTouch K ey M n K 2 IO E x te r n a l P in orTouch K ey M n K 1 IO E x te r n a l P in orTouch K ey b it T o u c h C ir c u its L o g ic I/O c ir c u its b it T o u c h C ir c u its L o g ic I/O c ir c u its b it T o u c h C ir c u its L o g ic I/O c ir c u its b it T o u c h C ir c u its L o g ic I/O c ir c u its I/O I/O I/O I/O Touch Key or I/O Function Select Rev. 1.00 109 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Touch Key Interrupt Each touch key module, which consists of four touch keys, has two independent interrupts, one for each of the, 16-bit C/F counter and time slot counter. The time slot counter interrupt has its own interrupt vector while the 16-bit C/F counter interrupts are contained within the Multi-function interrupts and therefore do not have their own vector. Care must be taken during programming as the 16-bit C/F counter interrupt flags contained within the Multi-function interrupts will not be automatically reset upon entry into the interrupt service routine but rather must be reset manually by the application program. More details regarding the touch key interrupts are located in the interrupt section of the datasheet. Programming Considerations After the relevant registers are setup, the touch key detection process is initiated the changing the MnST bit from low to high. This will enable and synchronise all relevant oscillators. The MnRCOV flag, which is the time slot counter flag will go high and remain high until the counter overflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency. Rev. 1.00 110 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Serial Interface Module - SIM These devices contain a Serial Interface Module, which includes both the four line SPI interface or the two line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM pins are pin shared with other I/O pins and must be selected using the SIMEN bit in the SIMC0 register. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but this device provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface must first be enabled by setting the correct bits in the SIMC0 and SIMC2 registers. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to ²1² to enable SCS pin function, set CSEN bit to ²0² the SCS pin will be as I/O function. S P I M a s te r SCK SDO SDI SCS S P I S la v e SCK SDI SDO SCS SPI Master/Slave Connection The SPI function in this device offers the following features: · · · · · Full duplex synchronous data transfer Both Master and Slave modes LSB first or MSB first data transmission modes Transmission complete flag Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. Rev. 1.00 111 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver D a ta B u s S IM D S D I P in SDO P in T x /R x S h ift R e g is te r C K E N b it C K P O L B b it S C K P in fS fL YS IR C C lo c k E d g e /P o la r ity C o n tro l B usy S ta tu s W C O L F la g T R F F la g C lo c k S o u r c e S e le c t S C S P in C S E N b it SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Register Name SIMC0 SIMD SIMC2 Bit 7 SIM2 D7 D7 6 SIM1 D6 D6 5 SIM0 D5 CKPOLB 4 PCKEN D4 CKEG 3 PCKP1 D3 MLS 2 PCKP0 D2 CSEN 1 SIMEN D1 WCOL 0 ¾ D0 TRF SPI Register List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. SIMD Register Bit Name R/W POR 7 D7 R/W x 6 D6 R/W x 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown Rev. 1.00 112 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. SIMC0 Register Bit Name R/W POR Bit 7~5 7 SIM2 R/W 1 6 SIM1 R/W 1 5 SIM0 R/W 1 4 PCKEN R/W 0 3 PCKP1 R/W 0 2 PCKP0 R/W 0 1 SIMEN R/W 0 0 ¾ ¾ ¾ Bit 4 Bit 3~2 Bit 1 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fLIRC 100: Unused 101: SPI slave mode 2 110: I C slave mode 111: Unused 2 These bits setup the overall operating mode of the SIM function. As well as selecting if the I C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. PCKEN: PCK Output Pin Control 0: Disable 1: Enable PCKP1, PCKP0: Select PCK output pin frequency 00: fSYS 01: fSYS/4 10: fSYS/8 11: TM0 CCRP match frequency/2 SIMEN: SIM Control 0: disable 1: enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be as I/O function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured 2 to operate as an I C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to 2 high, the contents of the I C control bits such as HTX and TXAK will remain at the previous 2 settings and should therefore be first initialised by the application program while the relevant I C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. unimplemented, read as ²0² Bit 0 Rev. 1.00 113 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SIMC2 Register Bit Name R/W POR Bit 7~6 Bit 5 7 D7 R/W 0 6 D6 R/W 0 5 CKPOLB R/W 0 4 CKEG R/W 0 3 MLS R/W 0 2 CSEN R/W 0 1 WCOL R/W 0 0 TRF R/W 0 Undefined bit This bit can be read or written by user software program. CKPOLB: Determines the base condition of the clock line 0: the SCK line will be high when the clock is inactive 1: the SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and as I/O function. If the bit is high the SCS pin will be enabled and used as a select pin. WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set ²1² automatically when an SPI data transmission is completed, but must set to ²0² by the application program. It can be used to generate an interrupt. Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.00 114 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output an SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. S IM E N = 1 , C S E N = 0 ( E x te r n a l P u ll- H ig h ) SCS S C K (C K P O L B = 1 , C K E G = 0 ) S C K (C K P O L B = 0 , C K E G = 0 ) S C K (C K P O L B = 1 , C K E G = 1 ) S C K (C K P O L B = 0 , C K E G = 1 ) SDO SDO (C K E G = 0 ) (C K E G = 1 ) D 7 /D 0 D 7 /D 0 D 6 /D 1 D 6 /D 1 D 5 /D 2 D 5 /D 2 D 4 /D 3 D 4 /D 3 D 3 /D 4 D 3 /D 4 D 2 /D 5 D 2 /D 5 D 1 /D 6 D 1 /D 6 D 0 /D 7 D 0 /D 7 S IM E N , C S E N = 1 S D I D a ta C a p tu re W r ite to S IM D SPI Master Mode Timing SCS S C K (C K P O L B = 1 ) S C K (C K P O L B = 0 ) SDO S D I D a ta C a p tu re W r ite to S IM D ( S D O d o e s n o t c h a n g e u n til fir s t S C K e d g e ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 SPI Slave Mode Timing - CKEG=0 Rev. 1.00 115 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SCS S C K (C K P O L B = 1 ) S C K (C K P O L B = 0 ) SDO S D I D a ta C a p tu re W r ite to S IM D ( S D O c h a n g e s a s s o o n a s w r itin g o c c u r s ; S D O is flo a tin g if S C S = 1 ) D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7 N o te : F o r S P I s la v e m o d e , if S IM E N = 1 a n d C S E N = 0 , S P I is a lw a y s e n a b le d a n d ig n o r e s th e S C S le v e l. SPI Slave Mode Timing - CKEG=1 A S P I tra n s fe r C le a r W C O L W r ite D a ta in to S IM D M a s te r m a s te r o r s la v e ? S la v e Y W CO L=1? S IM [2 :0 ]= 0 0 0 , 0 0 1 ,0 1 0 ,0 1 1 o r 1 0 0 S IM [2 :0 ]= 1 0 1 N N C o n fig u r e C K P O L B , C KEG ,C SEN and M LS T r a n s m is s io n c o m p le te d ? (T R F = 1 ? ) Y S IM E N = 1 R e a d D a ta fro m S IM D A C le a r T R F T ra n s fe r F in is h e d ? N Y END SPI Transfer Control Flowchart Rev. 1.00 116 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver I2C Interface The I C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. VDD 2 SDA SCL D e v ic e S la v e D e v ic e M a s te r D e v ic e S la v e I2C Master Slave Bus Connection I C Interface Operation 2 The I C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. 2 D a ta B u s I2C D a ta R e g is te r (S IM D ) S la v e A d d r e s s R e g is te r (S IM A ) A d d re s s C o m p a ra to r A d d re s s M a tc h H A A S B it H T X B it S C L P in S D A P in M U X D ir e c tio n C o n tr o l S h ift R e g is te r I2C In te rru p t D a ta in L S B D a ta O u t M S B R e a d /w r ite S la v e SRW B it E n a b le /D is a b le A c k n o w le d g e T r a n s m it/R e c e iv e C o n tr o l U n it 2 8 - b it D a ta C o m p le te D e te c t S ta rt o r S to p H C F B it H B B B it I C Block Diagram Rev. 1.00 117 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver The debounce time, if selected, can be chosen to be either 1 or 2 system clocks. S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r I C Registers 2 There are four control registers associated with the I C bus, SIMC0, SIMC1, SIMA and I2CTOC and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. The SIM pins are pin shared with other I/O pins and must be selected using the SIMEN bit in the SIMC0 register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Register Name SIMC0 SIMC1 SIMD SIMA I2CTOC Bit 7 SIM2 HCF D7 IICA6 I2CTOEN 6 SIM1 HAAS D6 IICA5 I2CTOF 5 SIM0 HBB D5 IICA4 I2CTOS5 2 2 4 PCKEN HTX D4 IICA3 I2CTOS4 3 PCKP1 TXAK D3 IICA2 I2CTOS3 2 PCKP0 SRW D2 IICA1 I2CTOS2 1 SIMEN IAMWU D1 IICA0 I2CTOS1 0 ¾ RXAK D0 D0 I2CTOS0 I C Register List Rev. 1.00 118 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SIMC0 Register Bit Name R/W POR Bit 7~5 7 SIM2 R/W 1 6 SIM1 R/W 1 5 SIM0 R/W 1 4 PCKEN R/W 0 3 PCKP1 R/W 0 2 PCKP0 R/W 0 1 SIMEN R/W 0 0 ¾ ¾ ¾ Bit 4 Bit 3~2 Bit 1 SIM2, SIM1, SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fLIRC 100: SPI master mode; SPI clock is TM0 CCRP match frequency/2 101: SPI slave mode 2 110: I C slave mode 111: Unused mode 2 These bits setup the overall operating mode of the SIM function. As well as selecting if the I C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. PCKEN: PCK Output Pin Control Described elsewhere PCKP1, PCKP0: Select PCK output pin frequency Described elsewhere SIMEN: SIM Control 0: disable 1: enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared, the SDI, SDO, SCK and SCS, or SDA and SCL lines will be as I/O function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured 2 to operate as an I C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to 2 high, the contents of the I C control bits such as HTX and TXAK will remain at the previous 2 settings and should therefore be first initialised by the application program while the relevant I C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. unimplemented, read as ²0² Bit 0 Rev. 1.00 119 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SIMC1 Register Bit Name R/W POR Bit 7 7 HCF R 1 2 6 HAAS R 0 5 HBB R 0 4 HTX R/W 0 3 TXAK R/W 0 2 SRW R 0 1 IAMWU R/W 0 0 RXAK R 1 Bit 6 HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. 2 HAAS: I C Bus address match flag 0: Not address match 1: Address match The HASS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. HBB: I C Bus busy flag 2 0: I C Bus is not busy 2 1: I C Bus is busy 2 2 The HBB flag is the I C busy flag. This flag will be ²1² when the I C bus is busy which will occur when a START signal is detected. The flag will be set to ²0² when the bus is free which will occur when a STOP signal is detected. 2 HTX: Select I C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter 2 TXAK: I C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to ²0² before further data is received. 2 SRW: I C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode 2 The SRW flag is the I C Slave Read/Write flag. This flag determines whether the master device 2 wishes to transmit or receive data from the I C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. 2 IAMWU: I C address match wake-up control 0: disable 1: enable 2 This bit should be set to ²1² to enable I C address match wake-up from SLEEP or IDLE Mode. 2 RXAK: I C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is ²0², it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is ²1². When this occurs, the slave transmitter will release the 2 SDA line to allow the master to send a STOP signal to release the I C Bus. 2 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.00 120 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver I2CTOC Register Bit Name R/W POR Bit 7 7 I2CTOEN R/W 0 2 6 I2CTOF R/W 0 5 I2CTOS5 R/W 0 4 I2CTOS4 R/W 0 3 I2CTOS3 R/W 0 2 I2CTOS2 R/W 0 1 I2CTOS1 R/W 0 0 I2CTOS0 R/W 0 Bit 6 Bit 5~0 I2CTOEN: I C Time-out Control 0: disable 1: enable I2CTOF: Time-out flag 0: no time-out 1: time-out occurred I2CTOS5~I2CTOS0: Time-Out Time Definition 2 I C time-out clock source is fLIRC/32. 2 I C Time-Out time is given by: [I2CTOS5 : I2CTOS0]+1) x (32/fLIRC) The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. SIMD Register Bit Name R/W POR 7 D7 R/W x 6 D6 R/W x 5 D5 R/W x 4 D4 R/W x 3 D3 R/W x 2 D2 R/W x 1 D1 R/W x 0 D0 R/W x ²x² unknown SIMA Register Bit Name R/W POR Bit 7~1 7 IICA6 R/W x 6 IICA5 R/W x 2 5 IICA4 R/W x 4 IICA3 R/W x 3 IICA2 R/W x 2 IICA1 R/W x 1 IICA0 R/W x 0 D0 R/W x ²x² unknown Bit 0 IICA6~ IICA0: I C slave address 2 IICA6~ IICA0 is the I C slave address bit 6~bit 0. The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. 2 When a master device, which is connected to the I C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Undefined bit This bit can be read or written by user software program. Rev. 1.00 121 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver I C Bus Communication 2 Communication on the I C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to ²1² to enable the I2C bus. Step 2 Write the slave address of the device to the I2C bus address register SIMA. Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt. S ta rt 2 S E T S IM [2 :0 ]= 1 1 0 S E T S IM E N W r ite S la v e A d d re s s to S IM A No C lr S IE P o ll S IF to d e c id e w h e n to g o to I2C B u s IS R I2C B u s In te rru p t= ? Yes S e t S IE W a it fo r In te r r u p t G o to M a in P r o g r a m G o to M a in P r o g r a m I2C Bus Initialisation Flow Chart I C Bus Start Signal 2 The START signal can only be generated by the master device connected to the I C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. 2 Rev. 1.00 122 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SCL S ta rt S la v e A d d r e s s SRW ACK SDA 1 0 1 1 0 1 0 1 0 SCL D a ta ACK S to p 1 SDA S=S SA= SR= M =S D=D A=A P=S S ta rt (1 S la v e SRW la v e d a ta (8 C K (R to p (1 SA 0 0 1 0 1 0 0 b it) A d d r e s s ( 7 b its ) b it ( 1 b it) e v ic e s e n d a c k n o w le d g e b it ( 1 b it) b its ) X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it) b it) SR M D A D A S SA SR M D A D A P Note: * When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Communication Timing Diagram Slave Address The transmission of a START signal by the master will be detected by all devices on the I C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I C Bus Read/Write Signal 2 2 The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is ²1² then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is ²0² then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. 2 Rev. 1.00 123 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver I C Bus Slave Address Acknowledge Signal 2 After the master has transmitted a calling address, any slave device on the I C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to ²1². If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to ²0². I C Bus Data and Acknowledge Signal 2 2 The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level ²0², before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. S ta rt No HAAS=1 ? Yes Yes Yes No No R e a d fro m S IM D to r e le a s e S C L lin e HTX=1 ? SRW =1 ? SET HTX C LR H TX C LR TXAK RETI Yes RXAK=1 ? No C LR H TX C LR TXAK W r ite d a ta to S IM D r e le a s e S C L L in e W r ite d a ta to S IM D to r e le a s e S C L L in e D u m m y re a d fro m S IM D to r e le a s e S C L L in e RETI RETI D u m m y re a d fro m S IM D to r e le a s e S C L L in e RETI RETI I2C Bus ISR Flow Chart Rev. 1.00 124 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver I C Time-out Control 2 In order to reduce the problem of I C lockup due to reception of erroneous clock sources, clock, a time-out function is provided. If the clock source to the I2C is not received then after a fixed time period, the I2C circuitry and registers will be reset. The time-out counter starts counting on an I2C bus ²START² & ²address match² condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out setup by the I2CTOC register, then a time-out condition will occur. The time-out function will stop when an I2C ²STOP² condition occurs. SCL S ta rt S la v e A d d r e s s SRW ACK 2 SDA 1 0 1 1 0 1 0 1 0 I2 C t i m e - o u t c o u n te r s ta rt SCL S to p 1 SDA 0 0 1 0 1 0 0 I2 C t im e - o u t c o u n t e r r e s e t o n S C L n e g a tiv e tr a n s itio n I2C Time-out When an I C time-out counter overflow occurs, the counter will stop and the I2CTOEN bit will be cleared to zero and the I2CTF bit will be set high to indicate that a time-out condition as occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When an I2C time-out occurs the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register SIMDR, SIMAR, SIMC0 SIMC1 After I C Time-out No change Reset to POR condition I2C Registers After Time-out 2 2 The I2CTOF flag can be cleared by the application program. There are 64 time-out periods which can be selected using bits in the I2CTOC register. The time-out time is given by the formula: ((1~64) ´ 32) / fLIRC. This gives a range of about 1ms to 64ms. Note also that the LIRC oscillator is continuously enabled. Rev. 1.00 125 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Peripheral Clock Output The Peripheral Clock Output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. Peripheral Clock Operation As the peripheral clock output pin, PCK, is shared with I/O line, the required pin function is chosen via PCKEN in the SIMC0 register. The Peripheral Clock function is controlled using the SIMC0 register. The clock source for the Peripheral Clock Output can originate from either the TM0 CCRP match frequency/2 or a divided ratio of the internal fSYS clock. The PCKEN bit in the SIMC0 register is the overall on/off control, setting PCKEN bit to ²1² enables the Peripheral Clock, setting PCKEN bit to ²0² disables it. The required division ratio of the system clock is selected using the PCKP1 and PCKP0 bits in the same register. If the device enters the SLEEP Mode this will disable the Peripheral Clock output. SIMC0 Register Bit Name R/W POR Bit 7~5 Bit 4 7 SIM2 R/W 1 6 SIM1 R/W 1 5 SIM0 R/W 1 4 PCKEN R/W 0 3 2 1 SIMEN R/W 0 0 ¾ ¾ ¾ PCKPSC1 PCKPSC0 R/W 0 R/W 0 Bit 3~2 Bit 1 Bit 0 SIM2~SIM0: SIM Operating Mode Control Described elsewhere PCKEN: PCK Output Pin Control 0: disable 1: enable PCKPSC1, PCKPSC0: Select PCK output pin frequency 0: fSYS 1: fSYS/4 2: fSYS/8 3: TM0 CCRP match frequency/2 SIMEN: SIM Control Described elsewhere Unimplemented, read as ²0² Rev. 1.00 126 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Touch Action or Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The devices contains several external interrupt and internal interrupts functions. The external interrupt is generated by the action of the external INT pin, while the internal interrupts are generated by various internal functions such as the Touch Keys, Timer Module, Time Base, SIM etc. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the MFI0~MFI5 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an E for enable/disable bit or F for request flag. Function Global INT Pin Touch Key Module SIM EEPROM Multi-function Time Base LVD External Peripheral Enable Bit EMI INTnE TKMnE SIM DEE MFnE TBnE LVF XPE TnPE TM TnAE TnBE Request Flag ¾ INTnF TKMnF SIF DEF MFnF TBnF LVE XPF TnPF TnAF TnBF Notes ¾ N=0 or 1 n=0~4 ¾ ¾ n=0~5 N=0 or 1 ¾ ¾ n=0~2 n=0~2 n=0~2 Interrupt Register Bit Naming Conventions Rev. 1.00 127 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Interrupt Register Contents BS85B12-3 Bit Name 7 INTEG INTC0 INTC1 INTC2 MFI0 MFI1 MFI2 MFI3 ¾ ¾ TB0F MF3F M116CTF T0AF ¾ DEF 6 ¾ SIMF TKM2F MF2F D6 T0PF T1BF LVF 5 ¾ INT1F TKM1F MF1F M016CTF M216CTF T1AF XPF 4 ¾ INT0F TKM0F MF0F D4 D4 T1PF TB1F 3 INT1S1 SIME TB0E MF3E M116CTE T0AE ¾ DEE 2 INT1S0 INT1E TKM2E MF2E D2 T0PE T1BE LVE 1 INT0S1 INT0E TKM1E MF1E M016CTE M216CTE T1AE XPE 0 INT0S0 EMI TKM0E MF0E D0 D0 T1PE TB1E BS85C20-3 Bit Name 7 INTEG INTC0 INTC1 INTC2 INTC3 MFI0 MFI1 MFI2 MFI3 MFI4 MFI5 ¾ ¾ TB0F MF3F MF5F M116CTF T0AF ¾ DEF M416CTF ¾ 6 ¾ SIMF TKM2F MF2F MF4F D6 T0PF T1BF LVF D6 ¾ 5 ¾ INT1F TKM1F MF1F TKM4F M016CTF M216CTF T1AF XPF M316CTF T2AF 4 ¾ INT0F TKM0F MF0F TKM3F D4 D4 T1PF TB1F D4 T2PF 3 INT1S1 SIME TB0E MF3E MF5E M116CTE T0AE ¾ DEE M416CTE ¾ 2 INT1S0 INT1E TKM2E MF2E MF4E D2 T0PE T1BE LVE D2 ¾ 1 INT0S1 INT0E TKM1E MF1E TKM4E M016CTE M216CTE T1AE XPE M316CTE T2AE 0 INT0S0 EMI TKM0E MF0E TKM3E D0 D0 T1PE TB1E D0 T2PE Rev. 1.00 128 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver INTEG Register - All devices Bit Name R/W POR Bit 7~2 Bit 1~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 ¾ ¾ ¾ 4 ¾ ¾ ¾ 3 INT1S1 R/W 0 2 INT1S0 R/W 0 1 INT0S1 R/W 0 0 INT0S0 R/W 0 Bit 1~0 unimplemented, read as ²0² INT1S1, INT1S0: interrupt edge control for INT1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges INT0S1, INT0S0: interrupt edge control for INT0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges INTC0 Register - All devices Bit Name R/W POR Bit 7 Bit 6 7 ¾ ¾ ¾ 6 SIMF R/W 0 5 INT1F R/W 0 4 INT0F R/W 0 3 SIME R/W 0 2 INT1E R/W 0 1 INT0E R/W 0 0 EMI R/W 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 unimplemented, read as ²0² SIMF: SIM interrupt request flag 0: no request 1: interrupt request INT1F: INT1 pin interrupt request flag 0: no request 1: interrupt request INT0F: INT0 pin interrupt request flag 0: No request 1: Interrupt request SIME: SIM interrupt control 0: disable 1: enable INT1E: INT1 pin interrupt control 0: disable 1: enable INT0E: INT0 pin interrupt control 0: disable 1: enable EMI: Global interrupt control 0: disable 1: enable Rev. 1.00 129 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver INTC1 Register - All devices Bit Name R/W POR Bit 7 7 TB0F R/W 0 6 TKM2F R/W 0 5 TKM1F R/W 0 4 TKM0F R/W 0 3 TB0E R/W 0 2 TKM2E R/W 0 1 TKM1E R/W 0 0 TKM0E R/W 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TB0F: Time Base 0 interrupt request flag 0: no request 1: interrupt request TKM2F: Touch Key Module 2 interrupt request flag 0: no request 1: interrupt request TKM1F: Touch Key Module 1 interrupt request flag 0: no request 1: interrupt request TKM0F: Touch Key Module 0 interrupt request flag 0: no request 1: interrupt request TB0E: Time Base 0 interrupt control 0: disable 1: enable TKM2E: Touch Key Module 2 interrupt control 0: disable 1: enable TKM1E: Touch Key Module 1 interrupt control 0: disable 1: enable TKM0E: Touch Key Module 0 interrupt control 0: disable 1: enable INTC2 Register - All devices Bit Name R/W POR Bit 7 7 MF3F R/W 0 6 MF2F R/W 0 5 MF1F R/W 0 4 MF0F R/W 0 3 MF3E R/W 0 2 MF2E R/W 0 1 MF1E R/W 0 0 MF0E R/W 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MF3F: Multi-function interrupt 3 request flag 0: no request 1: interrupt request MF2F: Multi-function interrupt 2 request flag 0: no request 1: interrupt request MF1F: Multi-function interrupt 1 request flag 0: no request 1: interrupt request MF0F: Multi-function interrupt 0 request flag 0: no request 1: interrupt request MF3E: Multi-function interrupt 3 control 0: disable 1: enable MF2E: Multi-function interrupt 2 control 0: disable 1: enable MF1E: Multi-function interrupt 1 control 0: disable 1: enable MF0E: Multi-function interrupt 0 control 0: disable 1: enable Rev. 1.00 130 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver INTC3 Register - BS85C20 only Bit Name R/W POR Bit 7 7 MF5F R/W 0 6 MF4F R/W 0 5 TKM4F R/W 0 4 TKM3F R/W 0 3 MF5E R/W 0 2 MF4E R/W 0 1 TKM4E R/W 0 0 TKM3E R/W 0 Bit 6 Bit 5 MF5F: Multi-function interrupt 5 request flag 0: no request 1: interrupt request MF4F: Multi-function interrupt 4 request flag 0: no request 1: interrupt request TKM4F: Touch Key Module 4 interrupt request flag 0: no request 1: interrupt request TKM3F: Touch Key Module 3 interrupt request flag 0: no request 1: interrupt request MF5E: Multi-function interrupt 5 control 0: disable 1: enable MF4E: Multi-function interrupt 4 control 0: disable 1: enable TKM4E: Touch Key Module 4 interrupt control 0: disable 1: enable TKM3E: Touch Key Module 3 interrupt control 0: disable 1: enable MFI0 Register - All devices Bit 4 Bit 3 Bit 2 Bit 1 bit 0 Bit Name R/W POR Bit 7 7 M116CTF R/W 0 6 D6 R/W 0 5 M016CTF R/W 0 4 D4 R/W 0 3 M116CTE R/W 0 2 D2 R/W 0 1 M016CTE R/W 0 0 D0 R/W 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 M116CTF: Touch Key Module 1 16-bit counter interrupt request flag 0: no request 1: interrupt request D6: This bit must be cleared to zero M016CTF: Touch Key Module 0 16-bit counter interrupt request flag 0: no request 1: interrupt request D4: This bit must be cleared to zero M116CTE: Touch Key Module 1 16-bit timer interrupt control 0: disable 1: enable D2: This bit must be cleared to zero M016CTE: Touch Key Module 0 16-bit timer interrupt control 0: disable 1: enable D0: This bit must be cleared to zero Bit 0 Rev. 1.00 131 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver MFI1 Register - All devices Bit Name R/W POR Bit 7 7 T0AF R/W 0 6 T0PF R/W 0 5 M216CTF R/W 0 4 D4 R/W 0 3 T0AE R/W 0 2 T0PE R/W 0 1 M216CTE R/W 0 0 D0 R/W 0 Bit 6 Bit 5 T0AF: TM0 Comparator A match interrupt request flag 0: no request 1: interrupt request T0PF: TM0 Comparator P match interrupt request flag 0: no request 1: interrupt request M216CTF: Touch Key Module 2 16-bit counter interrupt request flag 0: no request 1: interrupt request D4: This bit must be cleared to zero T0AE: TM0 Comparator A match interrupt control 0: disable 1: enable T0PE: TM0 Comparator P match interrupt control 0: disable 1: enable M216CTE: Touch Key Module 2 16-bit counter interrupt control 0: disable 1: enable D0: This bit must be cleared to zero MFI2 Register - All devices Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name R/W POR Bit 7 Bit 6 7 ¾ ¾ ¾ 6 T1BF R/W 0 5 T1AF R/W 0 4 T1PF R/W 0 3 ¾ ¾ ¾ 2 T1BE R/W 0 1 T1AE R/W 0 0 T1PE R/W 0 Bit 5 Bit 4 unimplemented, read as ²0² T1BF: TM1 Comparator B match interrupt request flag 0: no request 1: interrupt request T1AF: TM1 Comparator A match interrupt request flag 0: no request 1: interrupt request T1PF: TM1 Comparator P match interrupt request flag 0: no request 1: interrupt request unimplemented, read as ²0² T1BE: TM1 Comparator B match interrupt control 0: disable 1: enable T1AE: TM1 Comparator A match interrupt control 0: disable 1: enable T1PE: TM1 Comparator P match interrupt control 0: disable 1: enable Bit 3 Bit 2 Bit 1 Bit 0 Rev. 1.00 132 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver MFI3 Register - All devices Bit Name R/W POR Bit 7 7 DEF R/W 0 6 LVF R/W 0 5 XPF R/W 0 4 TB1F R/W 0 3 DEE R/W 0 2 LVE R/W 0 1 XPE R/W 0 0 TB1E R/W 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DEF: Data EEPROM interrupt request flag 0: no request 1: interrupt request LVF: LVD interrupt request flag 0: no request 1: interrupt request XPF: External peripheral interrupt request flag 0: no request 1: interrupt request TB1F: Time Base 1 interrupt request flag 0: no request 1: interrupt request DEE: Data EEPROM interrupt control 0: disable 1: enable LVE: LVD interrupt control 0: disable 1: enable XPE: External Peripheral interrupt control 0: disable 1: enable TB1E: Time Base 1 interrupt control 0: disable 1: enable MFI4 Register - BS85C20 only Bit Name R/W POR Bit 7 7 M416CTF R/W 0 6 D6 R/W 0 5 M316CTF R/W 0 4 D4 R/W 0 3 M416CTE R/W 0 2 D2 R/W 0 1 M316CTE R/W 0 0 D0 R/W 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M416CTF: Touch Key Module 4 16-bit counter interrupt request flag 0: no request 1: interrupt request D6: This bit must be cleared to zero M316CTF: Touch Key Module 3 16-bit counter interrupt request flag 0: no request 1: interrupt request D4: This bit must be cleared to zero M416CTE: Touch Key Module 4 16-bit counter interrupt control 0: disable 1: enable D2: This bit must be cleared to zero M316CTE: Touch Key Module 3 16-bit counter interrupt control 0: disable 1: enable D0: This bit must be cleared to zero MFI5 Register - BS85C20 only Bit Name R/W 7 ¾ ¾ 6 ¾ ¾ 5 T2AF R/W 4 T2PF R/W 3 ¾ ¾ 2 ¾ ¾ 1 T2AE R/W 0 T2PE R/W Rev. 1.00 133 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver POR Bit 7~6 Bit 5 ¾ ¾ 0 0 ¾ ¾ 0 0 unimplemented, read as ²0² T2AF: TM2 Comparator A match interrupt request flag 0: no request 1: interrupt request T2PF: TM2 Comparator P match interrupt request flag 0: no request 1: interrupt request unimplemented, read as ²0² T2AE: TM2 Comparator A match interrupt control 0: disable 1: enable T2PE: TM2 Comparator P match interrupt control 0: disable 1: enable Bit 4 Bit 3~2 Bit 1 Bit 0 Interrupt Operation When the conditions for an interrupt event occur, such as a Touch Key Counter overflow, Timer Module overflow, etc. the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP instruction which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI instruction, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. Rev. 1.00 134 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device enters the SLEEP or IDLE Mode. E M I a u to d is a b le d in IS R Legend xxF xxF xxE R e q u e s t F la g - - n o a u to r e s e t in IS R R e q u e s t F la g - - a u to r e s e t in IS R E n a b le B it In te rru p t Nam e E x te rn a l 0 E x te rn a l 1 S IM T o u c h K e y M o d u le 0 T o u c h K e y M o d u le 1 T o u c h K e y M o d u le 2 In te rru p t N a m e M0 M1 1 6 - b it C tr o v e r flo w 1 6 - b it C tr o v e r flo w R e q u e s t F la g s M 016C TF M 116C TF E n a b le B its M 016C TE M 116C TE T im e B a s e 0 M . F u n c tio n 0 R equest F la g s IN T 0 F IN T 1 F S IM F TKM 0F TKM 1F TKM 2F TB0F M F0F E n a b le B its IN T 0 E IN T 1 E S IM E TKM 0E TKM 1E TKM 2E TB0E M F0E M a s te r E n a b le EMI EMI EMI EMI EMI EMI EMI EMI V e c to r 04H 08H 0CH 10H 14H 18H 1CH 20H P r io r ity H ig h M2 1 6 - b it C tr o v e r flo w TM 0 P TM 0 A M 216C TF T0PF T0AF M 216C TE T0PE T0AE M . F u n c tio n 1 M F1F M F1E EMI 24H TM 1 P TM 1 A TM 1B T1PF T1AF T1BF T1PE T1AE T1BE M . F u n c tio n 2 M F2F M F2E EMI 28H T im e B a s e 1 P IN T P in LVD EEPROM TB1F XPF LVF DEF TB1E XPE M . F u n c tio n 3 LVE DEE M F3F M F3E EMI 2CH B S 8 5 C 2 0 -3 o n ly T o u c h K e y M o d u le 3 T o u c h K e y M o d u le 4 TKM 3F TKM 4F TKM 3E TKM 4E EMI EMI 30H 34H M3 M4 1 6 - b it C tr o v e r flo w 1 6 - b it C tr o v e r flo w M 316C TF M 416C TF M 316C TE M . F u n c tio n 4 M 416C TE M F4F M F4E EMI 38H TM 2 P TM 2 A T2PF T2AF T2PE M . F u n c tio n 5 T2AE M F5F M F5E EMI 3CH Low Interrupt Structure Rev. 1.00 135 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver External Interrupt The external interrupt is controlled by signal transitions on the INT0 and INT1 pins. An external interrupt request will take place when the external interrupt request flag, INT0F or INT1F, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E or INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pin, it can only be configured as external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Multi-function Interrupt Within these devices there are four or six Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from the Touch Key Module, Timer Module, Low Voltage Detector, EEPROM, External Peripheral and Time Base interrupt sources. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi-Function request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the Touch Key module timer interrupts, will not be automatically reset and must be manually reset by the application program. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. Rev. 1.00 136 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. TB02~TB00 fS YS /4 M BC L IR C fT U X fT B ¸ 2 8 ~2 15 T im e B a s e 0 In te r r u p t ¸ 2 12 ~2 15 T im e B a s e 1 In te r r u p t T B C K B it TB11~TB10 Time Base Structure TBC Register Bit Name R/W POR Bit 7 7 TBON R/W 0 6 TBCK R/W 0 5 TB11 R/W 1 4 TB10 R/W 1 3 D3 R/W 0 2 TB02 R/W 1 1 TB01 R/W 1 0 TB00 R/W 1 Bit 6 Bit 5~4 TBON: TB0 and TB1 Control 0: disable 1: enable TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 TB11~TB10: Select Time Base 1 Time-out Period 0: 4096/fTB 1: 8192/fTB 2: 16384/fTB 3: 32768/fTB Undefined bit This bit can be read or written by user software program. TB02~TB00: Select Time Base 0 Time-out Period 0: 256/fTB 1: 512/fTB 2: 1024/fTB 3: 2048/fTB 4: 4096/fTB 5: 8192/fTB 6: 16384/fTB 7: 32768/fTB Bit 3 Bit 2~0 Rev. 1.00 137 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver External Peripheral Interrupt The External Peripheral Interrupt operates in a similar way to the external interrupt and is contained within the Multi-function Interrupt. A Peripheral Interrupt request will take place when the External Peripheral Interrupt request flag, XPF, is set, which occurs when a negative edge transition appears on the PINT pin. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, external peripheral interrupt enable bit, XPE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a negative transition appears on the External Peripheral Interrupt pin, a subroutine call to the respective Multi-function Interrupt, will take place. When the External Peripheral Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the XPF flag will not be automatically cleared, it has to be cleared by the application program. The external peripheral interrupt pin is pin-shared with several other pins with different functions. It must therefore be properly configured to enable it to operate as an External Peripheral Interrupt pin. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupts The Compact and Standard Type TMs have two interrupts each, while the Enhanced Type TM has three interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact and Standard Type TMs there are two interrupt request flags TnPF and TnAF and two enable bits TnPE and TnAE. For the Enhanced Type TM there are three interrupt request flags TnPF, TnAF and TnBF and three enable bits TnPE, TnAE and TnBE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P, A or B match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Rev. 1.00 138 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver EEPROM Interrupt The EEPROM Interrupt, is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective Multi-function Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. Touch Key Interrupts For a Touch Key interrupt to occur, the global interrupt enable bit, EMI, and the corresponding Touch Key interrupt enable TKMnE must be first set. An actual Touch Key interrupt will take place when the Touch Key request flag. TKMnF, is set, a situation that will occur when the 13-bit time slot counter in the relevant Touch Key module overflows. When the interrupt is enabled, the stack is not full and the Touch Key time slot counter overflow occurs, a subroutine call to the relevant Touch Key interrupt vector, will take place. When the interrupt is serviced, the Touch Key interrupt request flag, TKMnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. SIM Interrupt A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective interrupt vector, will take place. When the Serial Interface Interrupt is serviced, the SIM interrupt request flag, SIF, will be automatically cleared and the EMI bit will be automatically cleared to disable other interrupts. Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Rev. 1.00 139 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the ²CALL² instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Low Voltage Detector - LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be detemined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. Rev. 1.00 140 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver LVDC Register Bit Name R/W POR Bit 7~6 Bit 5 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 LVDO R 0 4 LVDEN R/W 0 3 ¾ ¾ ¾ 2 VLVD2 R/W 0 1 VLVD1 R/W 0 0 VLVD0 R/W 0 unimplemented, read as ²0² LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect LVDEN: Low Voltage Detector Control 0: Disable 1: Enable unimplemented, read as ²0² VLVD2 ~ VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.2V Bit Bit 3 Bit 2~0 LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.2V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. VDD V LVD LVDEN LVDO tL VDS LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-function interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.00 141 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver LCD Driver - SCOM and SSEG Function The devices can drive LCD panels by simulating LCD signals on their I/O pins using the application program. Both Command and Segment signals can be emulated in this way. LCD Operation The LCD driving Common pins, SCOM0~SCOM3, and Segment pins, SSEG0~SSEGn, are pin shared with other I/O pins. These LCD driving pins are configured using a series of LCD control registers which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM and SEG driver to generate the necessary VSS, (1/3)VDD, (2/3)VDD voltage and VDD levels for full LCD 1/3 bias operation. The SLCDEN bit in the LCD control register is the overall master control for the LCD driver, and this bit is used in conjunction with the COMnEN and SEGnEN bits to select which I/O Port pins are used for LCD driving. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. V DD VDD VDD (2 /3 )V D D (1 /3 )V D D VSS VSS L C D V o lta g e S e le c t C ir c u it A n a lo g S w itc h SCOM0 SCOM1 SCOM2 SCOM3 SSEG0 SSEG1 SSEGn VSS LCD Driver Structure Rev. 1.00 142 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver The accompanying waveform diagram shows a typical 1/3 Bias LCD waveform generated using the application program. Note that the depiction of a ²1² in the diagram illustrates an illuminated LCD pixel. The COM signal polarity generated on pins SCOM0~SCOM3, whether 0 or 1, are generated using the corresponding I/O data registers, which are bits PB0~PB3 in the PB register. fra m e 0 fra m e 1 fra m e 0 VDD 0 0 1 2 /3 V D D 1 /3 V D D VSS COM0 1 0 0 0 1 0 VDD COM1 0 1 0 0 0 1 0 0 0 1 2 /3 V D D 1 /3 V D D VSS VDD COM2 0 0 1 0 0 0 1 0 0 0 2 /3 V D D 1 /3 V D D VSS VDD 0 COM3 SEG0 0 0 1 1 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 2 /3 V D D 1 /3 V D D VSS VDD 2 /3 V D D 1 /3 V D D VSS VDD 2 /3 V D D SEG1 1 1 1 0 1 1 1 0 1 0 1 /3 V D D VSS Note: The logical values shown in the diagram are the PB I/O register values, PB0~PB3. 1/3 Bias LCD Waveform A cyclic LCD waveform includes two frames, known as Frame 0 and Frame 1 for which the following offers a functional explanation. In Frame 0 To select Frame 0 clear the FRAME bit to 0. In frame 0, the COM signal output can have a value of VDD, or have a Vbias value of 1/3 VDD. The SEG signal can have a value of VSS, or have a Vbias value of 2/3 VDD. In Frame 1 In frame 1, the COM signal output can have a value of VSS, have a Vbias value of 2/3 VDD. The SEG signal can have a value of VDD have a Vbias value of 1/3 VDD. Rev. 1.00 143 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver The COM0~COMn waveform is controlled by the application program using the FRAME bit, and the corresponding I/O data register for the respective COM pin to determine whether the COM0~COMn output has a value of either VDD, VSS or Vbias. The SEG0~SEGm waveform is controlled in a similar way using the FRAME bit and the corresponding I/O data register for the respective SEG pin to determine whether the SEG0~SEGn output has a value of either VDD, VSS or Vbias. LCD Bias Control The LCD COM and SEG driver enable a range of selections to be provided to suit the requirement of the LCD panel which are being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the LCD control register. LCD Driver Registers SLCDC0 Register Bit Name R/W POR Bit 7 7 FRAME R/W 0 6 ISEL1 R/W 0 5 ISEL0 R/W 0 4 SLCDEN R/W 0 3 COM3EN R/W 0 2 COM2EN R/W 0 1 COM1EN R/W 0 0 COM0EN R/W 0 Bit 6~5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FRAME: Present Frame output select -- Frame 0 or Frame 1 0: Frame 0 1: Frame 1 ISEL1, ISEL0: SCOM and SSEG operating current selection -- VDD=5V 0: 25mA 1: 50mA 2: 100mA 3: 200mA SLCDEN: SCOM and SSEG module on/off control 0: disable 1: enable The SCOMn and SSEGm lines can be enabled using COMnEN and SEGmEN if SLCDEN=1. When SLCDEN=0, then the SCOMn and SSEGm outputs will be fixed at a VDD level. COM3EN: SCOM3 or other function selection 0: Other function 1: SCOM3 COM2EN: SCOM2 or other function selection 0: Other function 1: SCOM2 COM1EN: SCOM1 or other function selection 0: Other function 1: SCOM1 COM0EN: SCOM0 or other function selection 0: Other function 1: SCOM0 Rev. 1.00 144 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SLCDC1 Register Bit Name R/W POR Bit 7~0 7 SEG7EN R/W 0 6 SEG6EN R/W 0 5 SEG5EN R/W 0 4 SEG4EN R/W 0 3 SEG3EN R/W 0 2 SEG2EN R/W 0 1 SEG1EN R/W 0 0 SEG0EN R/W 0 SEG7EN~SEG0EN: SSEG7~SSEG0 or other function selection 0: Other function 1: SSEG7~SSEG0 SLCDC2 Register - BS85B12-3 Bit Name R/W POR Bit 7~6 Bit 5~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 SEG13EN R/W 0 4 SEG12EN R/W 0 3 SEG11EN R/W 0 2 SEG10EN R/W 0 1 SEG9EN R/W 0 0 SEG8EN R/W 0 unimplemented, read as ²0² SEG13EN~SEG8EN: SSEG13~SSEG8 or other function selection 0: Other function 1: SSEG13~SSEG8 SLCDC2 Register - BS85C20-3 Bit Name R/W POR Bit 7~6 Bit 5~0 7 SEG15EN R/W 0 6 SEG14EN R/W 0 5 SEG13EN R/W 0 4 SEG12EN R/W 0 3 SEG11EN R/W 0 2 SEG10EN R/W 0 1 SEG9EN R/W 0 0 SEG8EN R/W 0 unimplemented, read as ²0² SEG15EN~SEG8EN: SSEG15~SSEG8 or other function selection 0: Other function 1: SSEG15~SSEG8 SLCDC3 Register - BS85C20-3 Bit Name R/W POR Bit 7 Bit 6 Bit 5~0 7 TCK2PS R/W 0 6 ¾ ¾ ¾ 5 SEG21EN R/W 0 4 SEG20EN R/W 0 3 SEG19EN R/W 0 2 SEG18EN R/W 0 1 SEG17EN R/W 0 0 SEG16EN R/W 0 TCK2PS: TCK2 Pin Remapping Control Described elsewhere unimplemented, read as ²0² SEG21EN~SEG16EN: SSEG21~SSEG16 or other function selection 0: Other function 1: SSEG21~SSEG16 Rev. 1.00 145 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver LED Driver The devices contain an LED driver function offering high current output drive capability which can be used to drive external LEDs. LED Driver Operation Depending upon which device is chosen various I/O pins have a capability of providing LED high current drive outputs. Device BS85B12-3 LED Drive Pins PA0~PA7 (high source current) PB0~PB5 (high sink current) PA0~PA7 (high source current) PB0~PB7 (high sink current) PE0~PE5 (high source current) BS85C20-3 Whether a normal current sink capability or high current sink capability is used, the selection is made using the SLEDCn registers. LED Driver Registers SLEDC0 Register - BS85B12-3 Bit Name R/W POR Bit 7~6 Bit 5~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 unimplemented, read as ²0² D5~D0: PB5~PB0 I/O output sink current select 0: Normal output sink current 1: ´2 output sink current SLEDC0 Register - BS85C20-3 Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 D7~D0: PB7~PB0 I/O output sink current select 0: Normal output sink current 1: ´2 output sink current Rev. 1.00 146 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SLEDC1 Register - All Devices Bit Name R/W POR Bit 7~0 7 D7 R/W 0 6 D6 R/W 0 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 D7~D0: PA7~PA0 I/O output source current select 0: Normal output source current 1: ´2 output source current SLEDC2 Register - BS85C20-3 Bit Name R/W POR Bit 7~6 Bit 5~0 7 ¾ ¾ ¾ 6 ¾ ¾ ¾ 5 D5 R/W 0 4 D4 R/W 0 3 D3 R/W 0 2 D2 R/W 0 1 D1 R/W 0 0 D0 R/W 0 unimplemented, read as ²0² D5~D0: PE5~PE0 I/O output source current select 0: Normal output source current 1: ´2 output source current Rev. 1.00 147 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Application Circuits V DD VDD 0 .1 m F VSS SC O M n,SSEG n LCD Panel PA,PB orPE KEY1 KEY2 I/O S P I /I2 C KEY19 KEY20 LED C o n tr o l D e v ic e S P I/I2 C D evoce W r ite r C o n n e c to r S ig n a ls VDD MCU VDD P r o g r a m m in g P in s VPP SDATA PA7 PA0 SC LK PA2 VSS # # # VSS T o o th e r C ir c u it Note: ²#² may be resistor or capacitor. The resistance of ²#² must be greater than 1kW or the capacitance of ²#² must be less than 1nF. Rev. 1.00 148 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Rev. 1.00 149 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the ²SET [m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 150 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 Note 1 1 1 Note 1 1 1 Note 1 1 Note 1 Note 1 Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Description Cycles Flag Affected Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC 1 1 1 Note 1 Note 1 Note 1 1 1 1 Note 1 1 Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 Note 1 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 Note 1 1 Note 1 1 Note 1 1 Note 1 None None C C None None C C Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 Note 1 1 Note 1 Z Z Z Z Rev. 1.00 151 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Mnemonic Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 Note 1 Note 1 1 1 1 Note 1 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2 Note 2 Note Description Cycles Note Flag Affected Clear bit of Data Memory Set bit of Data Memory 1 Note 1 None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 Note 1 note 1 Note 1 Note 1 Note 1 Note 1 Note 1 Note 1 2 2 2 2 None None None None None None None None None None None None None None None 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and ²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 152 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ¬ ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ¬ ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ¬ ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ¬ ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ¬ ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ¬ ACC ²AND² [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ¬ ACC ²AND² x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ¬ ACC ²AND² [m] Z Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Rev. 1.00 153 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver CALL addr Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ¬ Program Counter + 1 Program Counter ¬ addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ¬ 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ¬ 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ¬ 0 PDF ¬ 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ¬ 0 PDF ¬ 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ¬ 0 PDF ¬ 0 TO, PDF Description Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) Rev. 1.00 154 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver CPL [m] Complement Data Memory Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ¬ [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ¬ [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ¬ ACC + 00H or [m] ¬ ACC + 06H or [m] ¬ ACC + 60H or [m] ¬ ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ¬ [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ¬ [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ¬ 0 PDF ¬ 1 TO, PDF Description Operation Affected flag(s) CPLA [m] Description Operation Affected flag(s) DAA [m] Description Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description Operation Affected flag(s) Rev. 1.00 155 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver INC [m] Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ¬ [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ¬ [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ¬ addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ¬ [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ¬ x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ¬ ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ¬ ACC ²OR² [m] Z Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s) Rev. 1.00 156 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver OR A,x Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ¬ ACC ²OR² x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ¬ ACC ²OR² [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ¬ Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ¬ Stack ACC ¬ x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ¬ Stack EMI ¬ 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ [m].7 None Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected flag(s) Rev. 1.00 157 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver RLC [m] Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ¬ [m].i; (i = 0~6) [m].0 ¬ C C ¬ [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ¬ [m].i; (i = 0~6) ACC.0 ¬ C C ¬ [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ¬ [m].(i+1); (i = 0~6) [m].7 ¬ C C ¬ [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ¬ [m].(i+1); (i = 0~6) ACC.7 ¬ C C ¬ [m].0 C Description Operation Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) Rev. 1.00 158 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SBC A,[m] Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ¬ ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ¬ ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ¬ [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ¬ [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ¬ FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ¬ 1 None Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) SDZA [m] Description Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s) Rev. 1.00 159 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SIZ [m] Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ¬ [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ¬ [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ¹ 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ¬ ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ¬ ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ¬ ACC - x OV, Z, AC, C Description Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) SUB A,x Description Operation Affected flag(s) Rev. 1.00 160 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SWAP [m] Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 « [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4 ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ¬ [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ¬ program code (low byte) TBLH ¬ program code (high byte) None Description Operation Affected flag(s) SWAPA [m] Description Operation Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) Rev. 1.00 161 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver TABRDL [m] Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ¬ program code (low byte) TBLH ¬ program code (high byte) None Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ¬ ACC ²XOR² [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ¬ ACC ²XOR² [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ¬ ACC ²XOR² x Z Description Operation Affected flag(s) XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Rev. 1.00 162 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Package Information 24-pin SKDIP (300mil) Outline Dimensions A A 13 12 1 B 24 B 1 24 13 12 H C D E F G I E F D G C H I Fig1. Full Lead Packages MS-001d (see fig1) Symbol A B C D E F G H I Fig2. 1/2 Lead Packages Dimensions in inch Min. 1.230 0.240 0.115 0.115 0.014 0.045 ¾ 0.300 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 0.100 ¾ 0.430 Dimensions in mm Min. 31.24 6.10 2.92 2.92 0.36 1.14 ¾ 7.62 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 2.54 ¾ 10.92 Max. 32.51 7.11 4.95 3.81 0.56 1.78 ¾ 8.26 ¾ Max. 1.280 0.280 0.195 0.150 0.022 0.070 ¾ 0.325 ¾ Symbol A B C D E F G H I Rev. 1.00 163 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver MS-001d (see fig2) Symbol A B C D E F G H I Dimensions in inch Min. 1.160 0.240 0.115 0.115 0.014 0.045 ¾ 0.300 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 0.100 ¾ 0.430 Dimensions in mm Min. 29.46 6.10 2.92 2.92 0.36 1.14 ¾ 7.62 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 2.54 ¾ 10.92 Max. 30.35 7.11 4.95 3.81 0.56 1.78 ¾ 8.26 ¾ Max. 1.195 0.280 0.195 0.150 0.022 0.070 ¾ 0.325 ¾ Symbol A B C D E F G H I Rev. 1.00 164 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver MO-095a (see fig2) Symbol A B C D E F G H I Dimensions in inch Min. 1.145 0.275 0.120 0.110 0.014 0.045 ¾ 0.300 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 0.100 ¾ 0.430 Dimensions in mm Min. 29.08 6.99 3.05 2.79 0.36 1.14 ¾ 7.62 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 2.54 ¾ 10.92 Max. 30.10 7.49 3.81 3.81 0.56 1.52 ¾ 8.26 ¾ Max. 1.185 0.295 0.150 0.150 0.022 0.060 ¾ 0.325 ¾ Symbol A B C D E F G H I Rev. 1.00 165 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver 24-pin SOP (300mil) Outline Dimensions 24 A 13 B 1 12 C C' G H D E F a MS-013 Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min. 0.393 0.256 0.012 0.598 ¾ ¾ 0.004 0.016 0.008 0° Nom. ¾ ¾ ¾ ¾ ¾ 0.050 ¾ ¾ ¾ ¾ Dimensions in mm Min. 9.98 6.50 0.30 15.19 ¾ ¾ 0.10 0.41 0.20 0° Nom. ¾ ¾ ¾ ¾ ¾ 1.27 ¾ ¾ ¾ ¾ Max. 10.64 7.62 0.51 15.57 2.64 ¾ 0.30 1.27 0.33 8° Max. 0.419 0.300 0.020 0.613 0.104 ¾ 0.012 0.050 0.013 8° Rev. 1.00 166 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver 24-pin SSOP (150mil) Outline Dimensions 24 A 13 B 1 12 C C' G H D E F a Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min. 0.228 0.150 0.008 0.335 0.054 ¾ 0.004 0.022 0.007 0° Nom. ¾ ¾ ¾ ¾ ¾ 0.025 ¾ ¾ ¾ ¾ Dimensions in mm Min. 5.79 3.81 0.20 8.51 1.37 ¾ 0.10 0.56 0.18 0° Nom. ¾ ¾ ¾ ¾ ¾ 0.64 ¾ ¾ ¾ ¾ Max. 6.20 3.99 0.30 8.79 1.52 ¾ 0.25 0.71 0.25 8° Max. 0.244 0.157 0.012 0.346 0.060 ¾ 0.010 0.028 0.010 8° Rev. 1.00 167 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver 28-pin SKDIP (300mil) Outline Dimensions A 28 15 14 1 B H C D E F G I Symbol A B C D E F G H I Dimensions in inch Min. 1.375 0.278 0.125 0.125 0.016 0.050 ¾ 0.295 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 0.100 ¾ 0.375 Dimensions in mm Min. 34.93 7.06 3.18 3.18 0.41 1.27 ¾ 7.49 ¾ Nom. ¾ ¾ ¾ ¾ ¾ ¾ 2.54 ¾ 9.53 Max. 35.43 7.57 3.43 3.68 0.51 1.78 ¾ 8.00 ¾ Max. 1.395 0.298 0.135 0.145 0.020 0.070 ¾ 0.315 ¾ Symbol A B C D E F G H I Rev. 1.00 168 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver 28-pin SOP (300mil) Outline Dimensions 28 A 15 B 1 14 C C' G H D E F a MS-013 Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min. 0.393 0.256 0.012 0.697 ¾ ¾ 0.004 0.016 0.008 0° Nom. ¾ ¾ ¾ ¾ ¾ 0.050 ¾ ¾ ¾ ¾ Dimensions in mm Min. 9.98 6.50 0.30 17.70 ¾ ¾ 0.10 0.41 0.20 0° Nom. ¾ ¾ ¾ ¾ ¾ 1.27 ¾ ¾ ¾ ¾ Max. 10.64 7.62 0.51 18.11 2.64 ¾ 0.30 1.27 0.33 8° Max. 0.419 0.300 0.020 0.713 0.104 ¾ 0.012 0.050 0.013 8° Rev. 1.00 169 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver 28-pin SSOP (150mil) Outline Dimensions 28 A 15 B 1 C C' 14 G H a F D E Symbol A B C C¢ D E F G H a Symbol A B C C¢ D E F G H a Dimensions in inch Min. 0.228 0.150 0.008 0.386 0.054 ¾ 0.004 0.022 0.007 0° Nom. ¾ ¾ ¾ ¾ ¾ 0.025 ¾ ¾ ¾ ¾ Dimensions in mm Min. 5.79 3.81 0.20 9.80 1.37 ¾ 0.10 0.56 0.18 0° Nom. ¾ ¾ ¾ ¾ ¾ 0.64 ¾ ¾ ¾ ¾ Max. 6.20 3.99 0.30 10.01 1.52 ¾ 0.25 0.71 0.25 8° Max. 0.244 0.157 0.012 0.394 0.060 ¾ 0.010 0.028 0.010 8° Rev. 1.00 170 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver 44-pin QFP (10mm´10mm) Outline Dimensions C D G 23 I 34 22 L F A B E 44 12 K 1 11 a J 33 H Symbol A B C D E F G H I J K L a Symbol A B C D E F G H I J K L a Dimensions in inch Min. 0.512 0.390 0.512 0.390 ¾ ¾ 0.075 ¾ 0.010 0.029 0.004 ¾ 0° Nom. ¾ ¾ ¾ ¾ 0.031 0.012 ¾ ¾ ¾ ¾ ¾ 0.004 ¾ Dimensions in mm Min. 13.00 9.90 13.00 9.90 ¾ ¾ 1.90 ¾ 0.25 0.73 0.10 ¾ 0° Nom. ¾ ¾ ¾ ¾ 0.80 0.30 ¾ ¾ ¾ ¾ ¾ 0.10 ¾ Max. 13.40 10.10 13.40 10.10 ¾ ¾ 2.20 2.70 0.50 0.93 0.20 ¾ 7° Max. 0.528 0.398 0.528 0.398 ¾ ¾ 0.087 0.106 0.020 0.037 0.008 ¾ 7° Rev. 1.00 171 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Reel Dimensions T2 D A B C T1 SOP 24W (300mil), SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.0±1.0 100.0±1.5 13.0 +0.5/-0.2 2.0±0.5 24.8 +0.3/-0.2 30.2±0.2 SSOP 24S (150mil), SSOP 28S (150mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.0±1.0 100.0±1.5 13.0 +0.5/-0.2 2.0±0.5 16.8 +0.3/-0.2 22.2±0.2 Rev. 1.00 172 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Carrier Tape Dimensions P0 D E F W C P1 t B0 D1 P A0 K0 R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . SOP 24W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0±0.3 12.0±0.1 1.75±0.1 11.5±0.1 1.55 1.50 +0.10/-0.00 +0.25/-0.00 4.0±0.1 2.0±0.1 10.9±0.1 15.9±0.1 3.1±0.1 0.35±0.05 21.3±0.1 Rev. 1.00 173 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SSOP 24S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.0 +0.3/-0.1 8.0±0.1 1.75±0.10 7.5±0.1 1.5 1.50 +0.1/-0.0 +0.25/-0.00 4.0±0.1 2.0±0.1 6.5±0.1 9.5±0.1 2.1±0.1 0.30±0.05 13.3±0.1 SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.0±0.3 12.0±0.1 1.75±0.10 11.5±0.1 1.5 1.50 +0.1/-0.0 +0.25/-0.00 4.0±0.1 2.0±0.1 10.85±0.10 18.34±0.10 2.97±0.10 0.35±0.01 21.3±0.1 Rev. 1.00 174 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver SSOP 28S (150mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 16.0±0.3 8.0±0.1 1.75±0.1 7.5±0.1 1.55 1.50 +0.10/-0.00 +0.25/-0.00 4.0±0.1 2.0±0.1 6.5±0.1 10.3±0.1 2.1±0.1 0.30±0.05 13.3±0.1 Rev. 1.00 175 February 1, 2011 BS85B12-3/BS85C20-3 Touch Key Flash MCU with LCD/LED Driver Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright Ó 2011 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 176 February 1, 2011

下载 PDF

BS85C20-3 价格&库存

-> 查询更多价格&库存

很抱歉，暂时无法提供与“BS85C20-3”相匹配的价格&库存，您可以联系我们找货

免费人工找货

搜索历史

BS85C20-3

相关技术文章