HA0003E

HT46R4A Cost-Effective A/D Type 8-Bit MCU Technical Document · Tools Information · FAQs · Application Note - HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM - HA0049E Read and Write Control of the HT1380 - HA0051E Li Battery Charger Demo Board - Using the HT46R47 - HA0052E Microcontroller Application - Battery Charger - HA0083E Li Battery Charger Demo Board - Using the HT46R46 - HA0075E MCU Reset and Oscillator Circuits Application Note Features · Operating voltage: · Up to 0.5ms instruction cycle with 8MHz system clock fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V · Max of 27 bidirectional I/O lines · External interrupt input shared with I/O line · Two 8-bit programmable Timer/Event Counters with at VDD=5V · 6-level subroutine nesting · 6 channel 9-bit resolution A/D converter · Dual channel 8-bit PWM output shared with I/O lines · Bit manipulation instruction · Table read instructions · 63 powerful instructions · All instructions executed in one or two machine overflow interrupt · Integrated crystal and RC oscillator · Watchdog Timer · 4096´15 program memory · 192´8 data memory · PFD for audio frequency generation · Power down and wake-up functions to reduce power cycles · Low voltage reset function · 28-pin SKDIP/SOP, 32-pin DIP, 44-QFP package consumption General Description The HT46R4A is a device from the Cost-Effective A/D Type Series of MCUs. As an 8-bit high performance RISC architecture microcontroller, the device is designed especially for applications that interface directly to analog signals, such as those from sensors. The devices include an integrated multi-channel Analog to Digital Converter in addition to two Pulse Width Modulation outputs. The usual Holtek MCU features such as power down and wake-up functions, oscillator options, programmable frequency divider, etc. combine to ensure user applications require a minimum of external components. The benefits of integrated A/D and PWM functions, in addition to low power consumption, high performance, I/O flexibility and low-cost, provides the device with the versatility to suit a wide range of application possibilities such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers, etc. As is the case with all Holtek microcontroller devices, the HT46R4A is fully supported by a full suite of profesional hardware and software tools, containing comprehensive features to ensure user applications are designed and debugged in as short a time as possible. Rev. 1.00 1 November 28, 2007 HT46R4A Block Diagram S y s te m R C / X 't a l O s c illa t o r P ro g ra m C o u n te r A d d re s s D e c o d e r T im in g G e n e ra to r In s tr u c tio n D ecoder In s tr u c tio n R e g is te r P ro g ra m M e m o ry W DT O s c illa to r D a ta M e m o ry S ta c k S ta c k P o in te r A /D C o n v e rte r R eset& LVR A d d re s s D e c o d e r M U X MUX M e m o ry P o in te r ACC L o o k -u p T a b le R e g is te r L o o k -u p T a b le P o in te r T o P ro g ra m M e m o ry C o n fig u r a tio n O p tio n ALU S h ifte r C o n fig . R e g is te r PW M C o n fig . R e g is te r T im e r / C o u n te r PFD C o n fig . R e g is te r In te rru p t C ir c u it C o n fig . I/O R e g is te r P o r ts D e v ic e P r o g r a m m in g C ir c u itr y Pin Assignment P B 5 /A N 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P B 4 /A N 4 P B 5 /A N 5 P B 4 /A N 4 P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS PC0 PC1 PC2 9 10 11 12 13 14 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PB6 PB7 P A 4 /T M R 0 P A 5 /IN T PA6 P A 7 /T M R 1 OSC2 OSC1 VDD RES P D 1 /P W M 1 P D 0 /P W M 0 PC4 PC3 P A 3 /P F D PA2 PA1 PA0 P B 3 /A N 3 P B 2 /A N 2 P B 1 /A N 1 P B 0 /A N 0 VSS PC0 PC1 PC2 PC3 PC4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 HT46R4A 3 2 D IP -A PB6 PB7 P A 4 /T M R 0 P A 5 /IN T PA6 P A 7 /T M R 1 OSC2 OSC1 VDD RES PD2 P D 1 /P W M 1 P D 0 /P W M 0 PC7 PC6 PC5 PB PB PB PB 0 2 1 3 PA PA PA N /A N /A N /A N /A N VS N PC C 1 0 C 1 0 S 0 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 N N N N PB PB N P B 5 /A N P B 4 /A N N P A 3 /P F D 44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 C C C C C C 4 5 6 7 NC PA PA PA PA NC NC 2 33 32 31 30 H T46R 4A 4 4 Q F P -A 29 28 27 26 25 24 23 4 /T M R 0 5 /IN T 6 7 /T M R 1 OSC2 OSC1 VDD NC RES PD2 P D 1 /P W M 1 P D 0 /P W M 0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 HT46R4A 2 8 S K D IP -A /S O P -A Rev. 1.00 2 November 28, 2007 HT46R4A Pin Description Pin Name PA0~PA2 PA3/PFD PA4/TMR0 PA5/INT PA6 PA7/TMR1 PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6~PB7 PC0~PC7 I/O Configuration Option Description Bidirectional 8-bit input/output port. Each individual pin on this port can be configured as a wake-up input by a configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA3, PA4, PA7 and PA5 are pin-shared with PFD, TMR0, TMR1 and INT, respectively. I/O Pull-high Wake-up PA3 or PFD I/O Pull-high Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D input, the I/O function and pull-high resistor options are disabled automatically. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Bidirectional 3-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration option determines which pins on the port have pull-high resistors. The PWM outputs are pin-shared with pins PD0 and PD1 selected via configuration options. OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. Schmitt Trigger reset input. Active low. Positive power supply Negative power supply, ground I/O Pull-high PD0/PWM0 PD1/PWM1 I/O PD2 Pull-high I/O or PWM OSC1 OSC2 RES VDD VSS Note: I O I ¾ ¾ Crystal or RC ¾ ¾ ¾ 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have a pull-high resistor. 3. Pins PC5~PC7 and pin PD2 exist but are not bounded out on the 28-pin package. 4. Unbounded pins should be setup as outputs or as inputs with pull-high resistors to conserve power. Absolute Maximum Ratings Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Storage Temperature ............................-50°C to 125°C Operating Temperature...........................-40°C to 85°C IOH Total............................................................-100mA Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.00 3 November 28, 2007 HT46R4A D.C. Characteristics Test Conditions Symbol Parameter VDD VDD Operating Voltage Operating Current (Crystal OSC) Operating Current (RC OSC) Operating Current (Crystal OSC, RC OSC) Standby Current (WDT Enabled) Standby Current (WDT Disabled) Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset I/O Port Sink Current 5V IOH 3V I/O Port Source Current 5V RPH VAD EAD IADC 3V Pull-high Resistance 5V A/D Input Voltage A/D Conversion Error Additional Power Consumption if A/D Converter is Used ¾ ¾ 3V 5V ¾ ¾ 3V 5V 3V 5V 5V 3V 5V 3V 5V ¾ ¾ ¾ ¾ ¾ 3V Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz ADC disable No load, fSYS=4MHz ADC disable No load, fSYS=8MHz ADC disable No load, system HALT No load, system HALT ¾ ¾ ¾ ¾ ¾ VOL=0.1VDD VOL=0.1VDD VOH=0.9VDD VOH=0.9VDD ¾ ¾ ¾ ¾ ¾ 2.2 3.3 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 20 10 0 ¾ ¾ ¾ ¾ ¾ 0.6 2 0.8 2.5 4 ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 3.0 8 20 -4 -10 60 30 ¾ ±0.5 0.5 1.5 5.5 5.5 1.5 4 1.5 4 8 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 ¾ ¾ ¾ ¾ 100 50 VDD ±1 1 3 V V mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA kW kW V LSB mA mA Min. Typ. Max. Unit Ta=25°C IDD1 IDD2 IDD3 ISTB1 ISTB2 VIL1 VIH1 VIL2 VIH2 VLVR IOL Rev. 1.00 4 November 28, 2007 HT46R4A A.C. Characteristics Test Conditions Symbol Parameter VDD fSYS System Clock ¾ ¾ ¾ ¾ 3V Watchdog Oscillator Period 5V tWDT1 tWDT2 tRES tSST tLVR tINT tAD tADC tADCS Watchdog Time-out Period (RC) Watchdog Time-out Period (System Clock) External Reset Low Pulse Width System Start-up Timer Period Low Voltage Reset Time Interrupt Pulse Width A/D Clock Period A/D Conversion Time A/D Sampling Time ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5.5V ¾ ¾ ¾ ¾ ¾ Wake-up from HALT ¾ ¾ ¾ ¾ ¾ 400 400 0 0 45 32 2 15 Ta=25°C Min. Typ. ¾ ¾ ¾ ¾ 90 65 ¾ ¾ ¾ 1024 1 ¾ ¾ 76 32 Max. 4000 8000 4000 8000 180 130 2 16 Unit kHz kHz kHz kHz ms ms tWDTOSC tSYS ms *tSYS ms ms ms tAD2 tAD2 fTIMER Timer I/P Frequency (TMR) tWDTOSC 217 1 ¾ 0.25 1 1 ¾ ¾ 218 ¾ ¾ 2 ¾ ¾ ¾ ¾ Note: *tSYS=1/fSYS Rev. 1.00 5 November 28, 2007 HT46R4A System Architecture A key factor in the high-performance features of the Holtek microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and O s c illa to r C lo c k ( S y s te m C lo c k ) P h a s e C lo c k T 1 P h a s e C lo c k T 2 P h a s e C lo c k T 3 P h a s e C lo c k T 4 P ro g ra m C o u n te r PC PC+1 PC+2 execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fSYS/4 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as ²JMP² or ²CALL² that demand a jump to a non-consecutive Program Memory address. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user. P ip e lin in g F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 ) F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C ) F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 ) System Clocking and Pipelining 1 2 3 4 : 5 : 6 D ELAY: NOP M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ] F e tc h In s t. 1 E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7 Instruction Fetching Rev. 1.00 6 November 28, 2007 HT46R4A When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and can be read nor written to. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organised into 6 levels and is neither part of the data nor part of the program space, and is neither be read nor written to. The activated level is indexed by the Stack Pointer, SP, and can neither be read nor written to. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. P ro g ra m C o u n te r T o p o f S ta c k S ta c k P o in te r S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry B o tto m o f S ta c k S ta c k L e v e l N Program Counter Bits Mode b11 Initial Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow A/D Converter Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine PC11 PC10 #11 S11 #10 S10 PC9 #9 S9 PC8 #8 S8 0 0 0 0 0 b10 0 0 0 0 0 b9 0 0 0 0 0 b8 0 0 0 0 0 b7 0 0 0 0 0 b6 0 0 0 0 0 b5 0 0 0 0 0 b4 0 0 0 0 1 b3 0 0 1 1 0 b2 0 1 0 1 0 b1 0 0 0 0 0 b0 0 0 0 0 0 Program Counter + 2 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0 Program Counter Note: PC11~PC8: Current Program Counter bits @7~@0: PCL bits #11~#0: Instruction code address bits S11~S0: Stack register bits The Program Counter is 12 bits wide, i.e. from b11~b0. Rev. 1.00 7 November 28, 2007 HT46R4A Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: · Arithmetic operations: ADD, ADDM, ADC, ADCM, · Location 008H This internal vector is used by the Timer/Event Counter 0. If a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. · Location 00CH This internal vector is used by the Timer/Event Counter 1. If a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. · Location 010H SUB, SUBM, SBC, SBCM, DAA · Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA · Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, This internal vector is used by the A/D converter. When an A/D conversion cycle is complete, the program will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full. 000H 004H 008H 00CH In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r 0 In te r r u p t V e c to r T im e r /E v e n t C o u n te r 1 In te r r u p t V e c to r A /D C o n v e r te r In te r r u p t S u b r o u tin e P ro g ra m M e m o ry RLC · Increment and Decrement INCA, INC, DECA, DEC · Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Program Memory The Program Memory is the location where the user code or program is stored. For this device, the type of memory is One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate programming tools, OTP devices offer users the flexibility to freely develop their applications which may be useful during debug or for products requiring frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. Structure The Program Memory has a capacity of 4K by 15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts. · Location 000H 010H n00H nFFH F00H FFFH L o o k - u p T a b le ( 2 5 6 w o r d s ) L o o k - u p T a b le ( 2 5 6 w o r d s ) 1 5 b its N o te : n ra n g e s fro m 0 to F Program Memory Structure Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the ²TABRDC[m]² or ²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as ²0². This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. · Location 004H This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. Rev. 1.00 8 November 28, 2007 HT46R4A The diagram illustrates the addressing/data flow of the look-up table: P ro g ra m C o u n te r H ig h B y te TBLP P ro g ra m M e m o ry TBLH T a b le C o n te n ts H ig h B y te S p e c ifie d b y [m ] T a b le C o n te n ts L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data lotempreg1 tempreg2 db db : : a,06h tblp,a : : tempreg1 ? ? cated in the last page which is stored there using the ORG statement. The value at this ORG statement is ²F00H² which refers to the start address of the last page within the 4K Program Memory. The table pointer is setup here to have an initial value of ²06H². This will ensure that the first data read from the data table will be at the Program Memory address ²F06H² or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the ²TABRDL [m]² instruction is executed. ; temporary register #1 ; temporary register #2 mov mov ; initialise table pointer - note that this address ; is referenced ; to the last page or present page tabrdl ; ; ; ; transfers value in table referenced by table pointer to tempregl data at prog. memory address ²F06H² transferred to tempreg1 and TBLH dec tabrdl tblp tempreg2 ; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address ²F05H² transferred to tempreg2 and TBLH in this example the data ²1AH² is transferred to tempreg1 and data ²0FH² to register tempreg2 the value ²00H² will be transferred to the high byte register TBLH : : org dc F00h ; sets initial address of last page 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Instruction Table Location Bits b11 1 b10 PC10 1 b9 PC9 1 b8 PC8 1 b7 @7 @7 b6 @6 @6 b5 @5 @5 b4 @4 @4 b3 @3 @3 b2 @2 @2 b1 @1 @1 b0 @0 @0 TABRDC [m] PC11 TABRDL [m] Table Location Note: PC11~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits The Table address location is 12 bits, i.e. from b11~b0. Rev. 1.00 9 November 28, 2007 HT46R4A Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at consecutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dictated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the address ²00H². Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. 00H S p e c ia l P u r p o s e D a ta M e m o ry 3FH 40H G e n e ra l P u rp o s e D a ta M e m o ry FFH H T46R 4A that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. By using the ²SET [m].i² and ²CLR [m].i² instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value ²00H². 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 H H H H H H H H H H H H H H H IA R MP AC PC TB TB L LP LH C STATUS IN T C 0 TM R0 TM R0C TM R TM R1 PA PAC PB PBC PC PCC PD PDC PW M PW M H H H 1 C H H H H H H H H Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the ²SET [m].i² and ²CLR [m].i² with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP. H H H H H 0 1 H H H H H IN T C 1 AD AD AD AC RL RH CR SR General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory : U n u s e d , re a d a s "0 0 " Special Purpose Data Memory Rev. 1.00 10 November 28, 2007 HT46R4A Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control and A/D converter operation. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Purpose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H. Indirect Addressing Register - IAR The IAR register, located at Data Memory address ²00H², is not physically implemented. This special register allows what is known as indirect addressing, which permits data manipulation using Memory Pointers instead of the usual direct memory addressing method where the actual memory address is defined. Any actions on the IAR register will result in corresponding read/write operations to the memory location specified by the Memory Pointer MP. Reading the IAR register indirectly will return a result of ²00H² and writing to the register indirectly will result in no operation. Memory Pointer - MP One Memory Pointer, known as MP, is physically implemented in the Data Memory. The Memory Pointer can be written to and manipulated in the same way as normal registers providing an easy way of addressing and tracking data. When using any operation on the indirect addressing register IAR, it is actually the address specified by the Memory Pointer that the microcontroller will be directed to. The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4. data .section ¢data¢ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ¢code¢ org 00h start: mov mov mov mov loop: clr inc sdz jmp continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. IAR mp block loop ; clear the data at address defined by MP ; increment memory pointer ; check if last memory location has been cleared a,04h ; setup size of block block,a a,offset adres1 ; Accumulator loaded with first RAM address mp,a ; setup memory pointer with first RAM address Rev. 1.00 11 November 28, 2007 HT46R4A Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers - TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are executed. Its value can be changed, for example using the ²INC² or ²DEC² instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the ²HALT² or ²CLR WDT² instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. · C is set if an operation results in a carry during an ad- dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. · AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. · Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. · OV is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. · PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. · TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. b7 TO PDF OV Z AC b0 C S T A T U S R e g is te r Ar Ca Au Ze Ov ith m e r r y fla x ilia r y r o fla g e r flo w g tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 " S y s te m M Pow erdow W a tc h d o g N o t im p le m Status Register Rev. 1.00 12 November 28, 2007 HT46R4A In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Register - INTC0, INTC1 These 8-bit registers, known as INTC0 and INTC1, control the operation of both the external and internal interrupts. By setting various bits within these registers using standard bit manipulation instructions, the enable/disable function of the external interrupts and each of the internal interrupts can be independently controlled. A master interrupt bit within these registers, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI² instruction. Note In situations where other interrupts may require servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine has been entered. table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC and PDC, also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the ²SET [m].i² and ²CLR [m].i² instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. Pulse Width Modulator Registers - PWM0, PWM1 The device contains two Pulse Width Modulators. Each one has its own related independent control register. For devices with two PWM functions, their control register names are PWM0 and PWM1. The 8-bit contents of these registers, defines the duty cycle value for the modulation cycle of the corresponding Pulse Width Modulator. A/D Converter Registers - ADRL, ADRH, ADCR, ACSR The device contains a 6-channel 9-bit A/D converter. The correct operation of the A/D requires the use of two data registers, a control register and a clock source register. A high byte data register known as ADRH, and a low byte data register known as ADRL. These are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. The channel selection and configuration of the A/D converter is setup via the control register ADCR while the A/D clock frequency is defined by the clock source register, ACSR. Timer/Event Counter Registers - TMR0, TMR0C, TMR1, TMR1C The device contains two integrated 8-bit size Timer/ Event Counters. These have associated registers known as TMR0 and TMR1, where the timer¢s values are located. Two associated control registers, known as TMR0C and TMR1C contain the setup information for these two timers. Note that all timer registers can be directly written to in order to preload their contents with fixed data to allow different time intervals to be setup. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC and PD. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory Rev. 1.00 13 November 28, 2007 HT46R4A Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device offers up to 27 bidirectional input/output lines labeled with port names PA, PB, PC and PD. These I/O ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]², where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via configuration options and are implemented using a weak PMOS transistor. Port A Wake-up Each device has a HALT instruction enabling the microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a Power Down condition, the device will remain in a low-power state until a Port A pin receives a high to low going edge. This function is especially suitable for applications that can be woken up via external switches. Note that each pin on Port A can be selected individually to have this wake-up feature. I/O Port Control Registers Each I/O port has its own control register PAC, PBC, PCC and PDC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control. · External Interrupt Input The external interrupt pin INT is pin-shared with the I/O pin PA5. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC register must be disabled. · External Timer Clock Input The external timer pins TMR0 and TMR1 are pin-shared with the I/O pins PA4 and PA7, respectively. To configure these pins to operate as timer inputs, the corresponding control bits in the timer control register must be correctly set. For applications that do not require an external timer input, these pin can be used as normal I/O pins. Note that if used as normal I/O pins the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation. · PFD Output Each device contains a PFD function whose single output is pin-shared with PA3. The output function of this pin is chosen via a configuration option and remains fixed after the device is programmed. Note that the corresponding bit of the port control register, PAC.3, must setup the pin as an output to enable the PFD output. If the PAC port control register has setup the pin as an input, then the pin will function as a normal logic input with the usual pull-high option, even if the PFD configuration option has been selected. · PWM Outputs The devices contain two PWM outputs PWM0 and PWM1 are pin shared with pins PD0 and PD1, respectively. The PWM output functions are chosen via configuration options and remain fixed after the device is programmed. Note that the corresponding bit or bits of the port control register, PDC, must setup the pin as an output to enable the PWM output. If the PDC port control register has setup the pin as an input, then the pin will function as a normal logic input Rev. 1.00 14 November 28, 2007 HT46R4A with the usual pull-high option, even if the PWM configuration option has been selected. · A/D Inputs I/O Pin Structures The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The device has six A/D converter inputs. All of these analog inputs are pin-shared with I/O pins on Port B. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no configuration options associated with the A/D function. If used as I/O pins, then full pull-high resistor configuration options remain, however if used as A/D inputs then any pull-high resistor options associated with these pins will be automatically disconnected. C o n tr o l B it Q D CK S Q D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r P u ll- H ig h O p tio n V DD W eak P u ll- u p I/O D a ta B it Q D CK S Q M P in W r ite D a ta R e g is te r R e a d D a ta R e g is te r S y s te m W a k e -u p U X W a k e - u p O p tio n P A o n ly Non-pin-shared Function Input/Output Ports D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n V DD W eak P u ll- u p D a ta B it Q D CK S Q M P A 4 /T M R 0 P A 5 /IN T P A 7 /T M R 1 W r ite D a ta R e g is te r Read IN TM R TM R Sy D a ta T fo r 0 fo r 1 fo r s te m Re PA PA PA Wa g is te r 5 o n ly 4 o n ly 7 o n ly k e -u p U X W a k e - u p O p tio n PA4/PA5 Input/Output Ports Rev. 1.00 15 November 28, 2007 HT46R4A V C o n tr o l B it Q D CK S Q P A 3 /P F D P D 0 /P W M 0 P D 1 /P W M 1 P u ll- H ig h O p tio n DD D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r W eak P u ll- u p D a ta B it Q D W r ite D a ta R e g is te r CK S Q M U X PFD orPW M W a v e fo rm M U X P F D /P W M O p tio n R e a d D a ta R e g is te r PA3/PFD and PD/PWM Input/Output Ports V C o n tr o l B it Q D CK S Q P u ll- H ig h O p tio n DD D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r W eak P u ll- u p P B 0 /A N 0 ~ P B 5 /A N 5 D a ta B it Q D CK S Q M U X W r ite D a ta R e g is te r R e a d D a ta R e g is te r PCR2 PCR1 PCR0 T o A /D C o n v e rte r A n a lo g In p u t S e le c to r AC S2~ACS0 PB Input/Output Ports Rev. 1.00 16 November 28, 2007 HT46R4A Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC, PBC, PCC and PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA, PB, PC and PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the ²SET [m].i² and ²CLR [m].i² instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4 register which defines the timer options and determines how the timer is to be used. The devices can have the timer clock configured to come from the internal clock source. In addition, the timer clock source can also be configured to come from an external timer pin. An external clock source is used when the timer is in the event counting mode, the clock source being provided on pin-shared pin PA4/TMR0 or PA7/TMR1. Depending upon the condition of the T0E or T1E bit in the corresponding timer control register, each high to low, or low to high transition on the external timer input pin will increment the counter by one. Configuring the Timer/Event Counter Input Clock Source The internal timer¢s clock can originate from various sources, depending upon which timer is chosen. The internal clock input timer source is used when the timer is in the timer mode or in the Pulse Width Measurement mode. Depending upon which timer is chosen this system clock timer source may be first divided by a prescaler, the division ratio of which is conditioned by the timer control register bits PSC2~PSC0. An external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin, TMR0 or TMR1 depending upon which timer is used. Depending upon the condition of the T0E or T1E bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. Timer Register - TMR0, TMR1 The timer register are special function register location within the special purpose Data Memory where the actual timer value is stored. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the PA4/TMR0 or PA7/TMR1 pin. The timer will count from the initial value loaded by the preload register to the full count value of FFH at which point the timer overflows and an internal interrupt signal generated. The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 00H to FFH the preload register must first be cleared to 00H. It should be noted that after power-on the preload register will be in an unknown condition. Note that if the Timer/Event Counter is not running and data is written to its preload register, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. P o rt D a ta W r ite to P o r t R e a d fro m P o rt Read/Write Timing Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer/Event Counters The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The device contains two 8-bit count up timers. With three different operating modes, the timers can be configured to operate as a general timer, an external event counter or as a Pulse Width Measurement device. The provision of an internal 8stage prescaler to the one clock circuitry of the timer/ event counters gives added range to the timer. There are two types of registers related to the Timer/Event Counters. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associated register is the timer control Rev. 1.00 17 November 28, 2007 HT46R4A D a ta B u s P r e lo a d R e g is te r PSC2~PSC0 T0M 1 (1 /1 ~ 1 /1 2 8 ) T im e r /E v e n t C o u n te r M o d e C o n tro l T0O N T im e r /E v e n t C o u n te r 8 - B it T im e r /E v e n t C o u n te r ¸2 O v e r flo w to In te rru p t PFD T0M 0 R e lo a d fS YS 8 - s ta g e P r e s c a le r P A 4 /T M R 0 T0E 8-bit Timer/Event Counter 0 Structure D a ta B u s P r e lo a d R e g is te r T1M 1 T1M 0 T im e r /E v e n t C o u n te r T1O N 8 - B it T im e r /E v e n t C o u n te r O v e r flo w to In te rru p t R e lo a d P A 7 /T M R 1 fS YS /4 T im e r /E v e n t C o u n te r M o d e C o n tro l T1E 8-bit Timer/Event Counter 1 Structure Timer Control Register - TMR0C, TMR1C The flexible features of the Holtek microcontroller Timer/ Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. The device contains two timer control registers known as TMR0C and TMR1C. It is the timer control register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the Pulse Width Measurement mode, bits 7 and 6 of the Timer Control Register, which are known as the bit pair T0M1/T0M0 or T1M1/T1M0 respectively, depending upon which timer is used, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as T0ON or T1ON, depending upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. Timer/Event Counter 0 also contains a prescaler function, with bits 0~2 of the Timer Control Register determining the division ratio of the input clock. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the Event Count or Pulse Width Measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as T0E or T1E, depending upon which timer is used. Configuring the Timer Mode In this mode, the timer can be utilized to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, the bit pair, T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must be set to 1 and 0 respectively. In this mode the internal clock is used as the timer clock. Note that for the Timer/Event Counter 0, the timer input clock frequency is further divided by a prescaler, the value of which is determined by the bits PSC2~PSC0 in the Timer Control Register. The timer-on bit, T0ON or T1ON depending upon which timer is used, must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will preload the value already loaded into the preload register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up sources, however, the internal interrupts can be disabled by ensuring that the ET0I and ET1I bits of the respective interrupt register are reset to zero. It should be noted that a timer overflow is one of the interrupt and wake-up sources. Rev. 1.00 18 November 28, 2007 HT46R4A b7 T0M 1 T0M 0 T0O N T0E b0 PSC2PSC1PSC0 TM R0C T im e r P PSC2 0 0 0 0 1 1 1 1 E ventC 1:coun 0:coun P u ls e W 1 : s ta rt 0 : s ta rt R e g is te r r e s c a le r R a te S e le PSC0 PSC1 0 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1 o u n te r A c tiv e E d g t o n fa llin g e d g e t o n r is in g e d g e id th M e a s u r e m e n c o u n tin g o n r is in g c o u n tin g o n fa llin g ct T im e r 1 :1 1 :2 1 :4 1 :8 1 :1 1 :3 1 :6 1 :1 e S e le c t R a te 6 2 4 28 t A c tiv e E d g e S e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e T im e r /E v e n t C o u n te r 0 C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c t T0M 1 T0M 0 0 no m od 0 0 eventc 1 1 tim e r m 0 1 p u ls e w 1 e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e Timer/Event Counter 0 Control Register b7 T1M 1 T1M 0 T1O N T1E b0 TM R1C R e g is te r N o t im p le m e n te d , r e a d a s " 0 " Ev 1: 0: Pu 1: 0: ent cou cou ls e s ta r s ta r Coun nton nton W id th tcoun tcoun te r A c fa llin g r is in g M eas tin g o tin g o tiv e E d g edge edge u re m e n n r is in g n fa llin g e S e le c t t A c tiv e E d g e S e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e T im e r /E v e n t C o u n te r 1 C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c t T1M 1 T1M 0 0 no m od 0 0 eventc 1 1 tim e r m 0 1 p u ls e w 1 e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e Timer/Event Counter 1 Control Register Rev. 1.00 19 November 28, 2007 HT46R4A P r e s c a le r O u tp u t In c re m e n t T im e r C o n tr o lle r T im e r + 1 T im e r + 2 T im e r + N T im e r + N + 1 Timer Mode Timing Chart E x te rn a l E v e n t In c re m e n t T im e r C o u n te r T im e r + 1 T im e r + 2 T im e r + 3 Event Counter Mode Timing Chart Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer pin, can be recorded by the internal timer. For the timer to operate in the event counting mode, the bit pair T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must be set to 0 and 1 respectively. The timer-on bit T0ON or T1ON, depending upon which timer is used, must be set high to enable the timer to count. Depending upon which counter is used, if T0E or T1E is low, the counter will increment each time the external timer pin receives a low to high transition. If T0E or T1E is high, the counter will increment each time the external timer pin receives a high to low transition. As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will then preload the value already loaded into the preload register. As the external timer pins are pin-shared with other I/O pins, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event Counter in the event counting mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that a timer overflow is one of the interrupt and wake-up sources. Also in the Event Counting mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the Power Down Mode. As a result when the timer overflows it will generate a wake-up and if the interrupts are enabled also generate a timer interrupt signal. Configuring the Pulse Width Measurement Mode In this mode, the width of external pulses applied to the pin-shared external pin PA4/TMR0 or PA7/TMR1 can be measured. In the Pulse Width Measurement Mode the timer clock source is supplied by the internal clock. For the timer to operate in this mode, the bit pair T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must both be set high. Depending upon which counter is used, if T0E or T1E is low, once a high to low transition has been received on the PA4/TMR0 or PA7/TMR1 pin, the timer will start counting until the PA4/TMR0 or PA7/TMR1 pin returns to its original high level. At this point the T0ON or T1ON bit, depending upon which counter is used, will be automatically reset to zero and the timer will stop counting. If the T0E or T1E bit is high, the timer will begin counting once a low to high transition has been received on the PA4/TMR0 or PA7/TMR1 pin and stop counting when the PA4/TMR0 or PA7/TMR1 pin returns to its original low level. As before, the T0ON or T1ON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the T0ON or T1ON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the T0ON or T1ON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on the PA4/TMR0 or PA7/TMR1 pin. As the T0ON or T1ON bit has now been reset, any further transitions on the external timer pin, will be ignored. Not until the T0ON or T1ON bit is again set high by the program can the timer begin further Pulse Width Measurements. In this way, single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the PA4/TMR0 or PA7/TMR1 pin and not by the logic level. As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will also be reset to the value already loaded into the preload register. As the external timer pins are pin-shared with other I/O pins, to ensure that the pins are configured to operate as pulse width measuring input pins, two things have to happen. The first is to ensure that the T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event Counter in the pulse width measuring mode, the second is to ensure that the port control register configures the pin as an input. It should be noted that a timer overflow is one of the interrupt and wake-up sources. Rev. 1.00 20 November 28, 2007 HT46R4A E x te r n a l T im e r P in In p u t T0O N orT1O N ( w ith T 0 E o r T 1 E = 0 ) P r e s c a le r O u tp u t In c re m e n t T im e r C o u n te r T im e r +1 +2 +3 +4 P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 . Pulse Width Measure Mode Timing Chart T im e r O v e r flo w PFD C lo c k P A 3 D a ta PFD O u tp u t a t P A 3 PFD Output Control Programmable Frequency Divider - PFD The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via configuration option, however, if not selected, the pin can operate as a normal I/O pin. The timer overflow signal from Timer/Event Counter 0 is the clock source for the PFD circuit. The output frequency is controlled by loading the required values into the timer registers and programming the prescaler bits to give the required division ratio. The counter, driven by the system clock which is divided by the prescaler value, will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The counter will then be automatically reloaded with the preload register value and continue counting-up. For the PFD output to function, it is essential that the corresponding bit of the Port A control register PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be used as a normal input pin. The PFD output will only be activated if bit PA3 is set to ²1². This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is cleared to ²0². Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very precise values of frequency can be generated. Prescaler Bits PSC0~PSC2 of the TMR0C register can be used to define the pre-scaling stages of the internal clock source Rev. 1.00 21 of Timer/Event Counter 0. The Timer/Event Counter 0 overflow signal can be used to generate signals for the PFD and Timer 0 interrupt. I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of the external PA4/TMR0 or PA7/TMR1 pin for correct operation. As these pins are shared pins they must be configured correctly to ensure they are setup for use as Timer/Event Counter inputs and not as normal I/O pins. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Register PAC bit 4 or bit 7 must be set high to ensure that the pin is setup as an input. Any pull-high resistor configuration option on this pin will remain valid even if the pin is used as a Timer/Event Counter input. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external November 28, 2007 HT46R4A timer input pin. As this is an external event and not synchronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialised before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialised the timer can be turned on and off by controlling the enable bit in the timer control register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter 0 is turned on, by setting bit 4 of the TMR0C as an independent instruction. The Timer/ Event Counter 0 can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter 0 to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector reti org 08h ; Timer/Event Counter interrupt vector jmp tmrint0 ; jump here when Timer/Event Counter 0 overflows : org 20h ; main program ;internal Timer/Event Counter 0 interrupt routine tmrint0: : ; Timer/Event Counter 0 main program placed here : reti : : begin: ;setup Timer registers mov a,09bh ; setup Timer preload value mov tmr0,a; mov a,081h ; setup Timer control register mov tmrc0,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,005h ; enable Master and Timer/Event Counter 0 interrupt mov intc0,a set tmr0c.4 ; start Timer/Event Counter 0 - note mode bits must be previously setup Rev. 1.00 22 November 28, 2007 HT46R4A Pulse Width Modulator The device contains two Pulse Width Modulation, PWM, outputs. Useful for such applications such as motor speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. Channels 2 PWM Mode 6+2 Output Pins PD0/ PD1 Register Name PWM0/ PWM1 6+2 PWM Mode Each full PWM cycle, as it is controlled by an 8-bit PWM, PWM0 or PWM1 register, has 256 clock periods. However, in the 6+2 PWM Mode, each PWM cycle is subdivided into four individual sub-cycles known as modulation cycle 0~modulation cycle 3, denoted as ²i² in the table. Each one of these four sub-cycles contains 64 clock cycles. In this mode, a modulation frequency increase by a factor of four is achieved. The 8-bit PWM, PWM0 or PWM1 register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. Parameter AC (0~3) i