HT1621/HT1621G
RAM Mapping 32´4 LCD Controller for I/O MCU
PATENTED
PAT No. : TW 099352
Features
· Operating voltage: 2.4V~5.2V
· 32´4 LCD driver
· Built-in 256kHz RC oscillator
· Built-in 32´4 bit display RAM
· External 32.768kHz crystal or 256kHz frequency
· 3-wire serial interface
source input
· Internal LCD driving frequency source
· Selection of 1/2 or 1/3 bias, and selection of 1/2 or
· Software configuration feature
1/3 or 1/4 duty LCD applications
· Data mode and command mode instructions
· Internal time base frequency sources
· R/W address auto increment
· Two selectable buzzer frequencies (2kHz/4kHz)
· Three data accessing modes
· Power down command reduces power consumption
· VLCD pin for adjusting LCD operating voltage
· Built-in time base generator and WDT
· HT1621: 44-pin LQFP package
· Time base or WDT overflow output
HT1621B: 48-pin SSOP/LQFP packages
HT1621G: Gold bumped chip
· 8 kinds of time base/WDT clock sources
General Description
systems. Only three or four lines are required for the interface between the host controller and the HT1621.
The HT1621 contains a power down command to reduce power consumption.
The HT1621 is a 128 pattern (32´4), memory mapping,
and multi-function LCD driver. The S/W configuration
feature of the HT1621 makes it suitable for multiple LCD
applications including LCD modules and display sub-
Selection Table
HT162X
HT1620
HT1621
HT1622
HT16220
HT1623
HT1625
HT1626
COM
4
4
8
8
8
8
16
SEG
32
32
32
32
48
64
48
Built-in Osc.
¾
Ö
Ö
¾
Ö
Ö
Ö
Crystal Osc.
Ö
Ö
¾
Ö
Ö
Ö
Ö
Rev. 3.20
1
November 25, 2014
PATENTED
HT1621/HT1621G
Block Diagram
D is p la y R A M
O S C O
O S C I
C o n
a n
T im
C ir c
C S
R D
W R
tro l
d
in g
u it
C O M 0
C O M 3
L C D D r iv e r /
B ia s C ir c u it
S E G 0
D A T A
S E G 3 1
V D D
V L C D
V S S
B Z
T o n e F re q u e n c y
G e n e ra to r
B Z
Note:
W a tc h d o g T im e r
a n d
T im e B a s e G e n e r a to r
IR Q
CS: Chip selection
BZ, BZ: Tone outputs
WR, RD, DATA: Serial interface
COM0~COM3, SEG0~SEG31: LCD outputs
IRQ: Time base or WDT overflow output
Pin Assignment
4 3
S E G 1 3
S E G 1
7
4 2
S E G 1 4
S E G 0
8
4 1
S E G 1 5
C S
9
4 0
S E G 1 6
R D
1 0
3 9
S E G 1 7
1
4 0 3 9 3 8 3 7 3 6 3 5 3 4
3 3
2
3 2
3
3 1
4
3 0
3 7
S E G 1 9
V S S
1 3
3 6
S E G 2 0
O S C O
1 4
3 5
S E G 2 1
O S C I
1 5
3 4
S E G 2 2
V L C D
1 6
3 3
S E G 2 3
V D D
1 7
3 2
S E G 2 4
IR Q
1 8
3 1
S E G 2 5
1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2
B Z
1 9
3 0
S E G 2 6
C
C
C
V
5
2 9
H T 1 6 2 1
4 4 L Q F P -A
6
7
2 8
2 7
8
2 6
9
2 5
1 0
1 1
2 4
2 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
S E G 3 1
4 0
3 9
3 8
3 7
3 6
3
3 4
4
3 3
5
3 2
H T 1 6 2 1 B
4 8 L Q F P -A
6
7
8
3 1
3 0
2 9
9
2 8
1 0
2 7
1 1
2 6
1 2
2 5
1 3
1 4
1 5
1
S E G 3 0
2 5
4 1
3 5
0
2 6
2 4
4 2
1 6
1 8
1 7
2 0
1 9
2 1
2 2
2 3
2 4
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S G E
S E G
S E G
S E G
S E G
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2
2 3
C O M 3
4 3
3
C O M 2
4
S E G 2 9
5
2 7
6
2 2
7
S E G 2 8
C O M 1
8
S E G 2 7
2 8
9
2 9
2 1
0
2 0
1
B Z
C O M 0
4 4
2 4
2 5
2 6
2 8 *
2 7 *
1 2
1 3
4 5
2 9
D A T A
D
1 2
4 6
2
3 0
S E G 1 8
1 1
4 7
4 8
1
3 1
3
2
3 8
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S G E
S E G
S E G
C S
R D
W R
D A T A
V S S
O S C O
O S C I
V L C D
V D D
IR Q
B Z
B Z
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
C O M
C O M
C O M
C O M
1 1
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 2
G 3
G 3
M 3
C S
R D
W R
A T A
V S S
L C D
V D D
B Z
O M 0
O M 1
O M 2
4 4 4 3 4 2 4 1
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
C O
W R
1 1
1 0
G 9
G 8
G 7
G 6
G 5
G 4
G 3
G 2
G 1
6
G 0
S E G 1 2
S E G 2
S E G
S E G
S E
S E
S E
S E
S E
S E
S E
S E
S E
S E
4 4
0
5
9
S E G 1 1
S E G 3
8
4 5
7
4
6
S E G 1 0
S E G 4
5
4 6
4
3
3
S E G 9
S E G 5
2
S E G 8
4 7
1
4 8
2
0
1
S E G 6
S E G 1
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G
S E G 7
N o te : * P le a s e n o te th a t in th e 4 8 - p in L Q F P p a c k a g e ,
th e S E G 2 7 a n d S E G 2 8 p in s a r e n o t in s e q u e n tia l o r d e r .
H T 1 6 2 1 B
4 8 S S O P -A
Rev. 3.20
2
November 25, 2014
PATENTED
HT1621/HT1621G
Pad Assignment
S E G 0
S E G 1
S E G 2
S E G 3
S E G 4
S E G 5
S E G 6
S E G 7
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3
D A T A
4
V S S
5
O S C O
(0 ,0 )
6
O S C I
7
V L C D
8
9
1 3
1 4
1 5
1 6
1 7
1 8
1 9
C O M 1
C O M 2
C O M 3
S E G 3 1
S E G 3 0
S E G 2 9
1 2
C O M 0
1 1
B Z
1 0
B Z
IR Q
4 8
2
W R
V D D
C S
R D
1
3 2
S E G 1 6
3 1
S E G 1 7
3 0
S E G 1 8
2 9
2 8
S E G 1 9
S E G 2 0
2 7
S E G 2 1
2 6
S E G 2 2
2 5
S E G 2 3
2 4
S E G 2 4
2 3
S E G 2 5
2 2
S E G 2 6
2 1
S E G 2 7
2 0
S E G 2 8
Chip size: 82 ´ 83 (mil)2
Bump height: 18mm ± 3mm
Min. Bump spacing: 23.02mm
Bump size: 76 ´ 76mm2
* The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 3.20
3
November 25, 2014
PATENTED
HT1621/HT1621G
Pad Coordinates
Unit: mm
Pad No.
X
Y
Pad No.
X
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
-802.951
-927.055
-927.055
-927.055
-925.358
-925.358
-925.785
-925.785
-925.699
-896.840
-637.515
-452.726
-288.935
-189.915
-84.350
14.669
114.260
213.320
312.380
925.915
925.915
925.915
925.915
925.915
939.295
343.250
244.230
89.374
-52.510
-151.360
-566.516
-675.287
-773.697
-939.537
-935.685
-935.685
-935.685
-935.685
-935.685
-935.685
-940.130
-940.130
-940.130
-867.615
-768.555
-669.495
-570.435
-437.375
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
925.915
925.915
925.915
925.915
925.915
925.915
925.915
925.915
849.589
750.530
651.469
552.409
453.349
354.289
255.230
156.169
57.109
-41.951
-141.010
-240.070
-339.130
-438.190
-537.250
-636.310
-338.315
-239.255
-140.195
-41.134
57.925
156.986
256.046
355.106
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
939.295
Pad Description
Pad No.
1
Pad Name
CS
I/O
Function
I
Chip selection input with pull-high resistor
When the CS is logic high, the data and command read from or written to
the HT1621 are disabled. The serial interface circuit is also reset. But if CS
is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1621 are all enabled.
2
RD
I
READ clock input with pull-high resistor
Data in the RAM of the HT1621 are clocked out on the falling edge of the RD
signal. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data.
3
WR
I
WRITE clock input with pull-high resistor
Data on the DATA line are latched into the HT1621 on the rising edge of the
WR signal.
4
DATA
I/O
Serial data input/output with pull-high resistor
5
VSS
¾
Negative power supply, ground
7
OSCI
I
6
OSCO
O
8
VLCD
I
9
VDD
¾
Positive power supply
10
IRQ
O
Time base or WDT overflow flag, NMOS open drain output
11, 12
BZ, BZ
O
2kHz or 4kHz tone frequency output pair
13~16
COM0~COM3
O
LCD common outputs
48~17
SEG0~SEG31
O
LCD segment outputs
Rev. 3.20
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads
can be left open.
LCD power input
4
November 25, 2014
PATENTED
HT1621/HT1621G
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+5.5V
Storage Temperature ............................-50oC to 125oC
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40oC to 85oC
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
VDD
Operating Voltage
IDD1
Operating Current
Ta=25°C
Test Conditions
VDD
Conditions
¾
¾
3V
5V
3V
IDD2
Operating Current
5V
3V
IDD3
Operating Current
5V
No load/LCD ON
On-chip RC oscillator
No load/LCD ON
Crystal oscillator
No load/LCD ON
External clock source
3V
ISTB
Standby Current
No load, Power down mode
5V
3V
VIL
Input Low Voltage
3V
Input High Voltage
IOH1
IOL2
IOH2
IOL3
IOH3
2.4
¾
5.2
V
¾
150
300
mA
¾
300
600
mA
¾
60
120
mA
¾
120
240
mA
¾
100
200
mA
¾
200
400
mA
¾
0.1
5
mA
¾
0.3
10
mA
0
¾
0.6
V
0
¾
1.0
V
2.4
¾
3.0
V
4.0
¾
5.0
V
VOL=0.3V
0.5
1.2
¾
mA
5V
VOL=0.5V
1.3
2.6
¾
mA
3V
VOH=2.7V
-0.4
-0.8
¾
mA
5V
VOH=4.5V
-0.9
-1.8
¾
mA
3V
VOL=0.3V
80
150
¾
mA
5V
VOL=0.5V
150
250
¾
mA
3V
VOH=2.7V
-80
-120
¾
mA
5V
VOH=4.5V
-120
-200
¾
mA
3V
VOL=0.3V
60
120
¾
mA
5V
VOL=0.5V
120
200
¾
mA
3V
VOH=2.7V
-40
-70
¾
mA
5V
VOH=4.5V
-70
-100
¾
mA
60
120
200
kW
30
60
100
kW
DATA, BZ, BZ
LCD Common Sink Current
LCD Common Source Current
LCD Segment Sink Current
LCD Segment Source Current
Pull-high Resistor
DATA, WR, CS, RD
5V
Rev. 3.20
Unit
3V
DATA, BZ, BZ, IRQ
3V
RPH
Max.
DATA, WR, CS, RD
5V
IOL1
Typ.
DATA, WR, CS, RD
5V
VIH
Min.
5
November 25, 2014
PATENTED
HT1621/HT1621G
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
192
256
320
kHz
fSYS1
System Clock
3V
On-chip RC oscillator
fSYS2
System Clock
¾
Crystal oscillator
¾
32768
¾
Hz
fSYS3
System Clock
¾
External clock source
¾
256
¾
kHz
¾
On-chip RC oscillator
¾
fSYS1/1024
¾
Hz
¾
Crystal oscillator
¾
fSYS2/128
¾
Hz
¾
External clock source
¾
fSYS3/1024
¾
Hz
¾
n: Number of COM
¾
n/fLCD
¾
s
4
¾
150
kHz
4
¾
300
kHz
¾
¾
75
kHz
¾
¾
150
kHz
1.5
2.0
2.5
kHz
3.0
4.0
5.0
kHz
CS
250
300
¾
ns
Write mode
3.34
¾
125
Read mode
6.67
¾
¾
Write mode
1.67
¾
125
Read mode
3.34
¾
¾
fLCD
LCD Clock
tCOM
LCD Common Period
fCLK1
Serial Data Clock (WR pin)
3V
Duty cycle 50%
5V
3V
fCLK2
Serial Data Clock (RD pin)
Duty cycle 50%
5V
Tone Frequency (2kHz)
fTONE
3V
On-chip RC oscillator
Tone Frequency (4kHz)
Serial Interface Reset Pulse
Width (Figure 3)
tCS
¾
3V
WR, RD Input Pulse Width
(Figure 1)
tCLK
5V
ms
ms
tr, tf
Rise/Fall Time Serial Data Clock
Width (Figure 1)
¾
¾
¾
120
160
ns
tsu
Setup Time for DATA to WR, RD
Clock Width (Figure 2)
¾
¾
60
120
¾
ns
th
Hold Time for DATA to WR, RD
Clock Width (Figure 2)
¾
¾
250
300
¾
ns
tsu1
Setup Time for CS to WR, RD
Clock Width (Figure 3)
¾
¾
500
600
¾
ns
th1
Hold Time for CS to WR, RD Clock
Width (Figure 3)
¾
¾
250
300
¾
ns
tOFF
VDD OFF Times (Figure 4)
¾
VDD drop down to 0V
20
¾
¾
ms
tSR
VDD Rising Slew Rate (Figure 4)
¾
¾
0.05
¾
¾
V/ms
tRSTD
Delay Time after Reset (Figure 4)
¾
¾
1
¾
¾
ms
Note:
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
Rev. 3.20
6
November 25, 2014
PATENTED
tf
W R , R D
C lo c k
V a lid D a ta
tr
V
9 0 %
5 0 %
1 0 %
HT1621/HT1621G
tC
tC
L K
D D
D B
G N D
D D
G N D
ts
L K
th
u
W R , R D
C lo c k
Figure 1
V
5 0 %
V
5 0 %
D D
G N D
Figure 2
tC
C S
V
th
u 1
G N D
0 V
1
V
5 0 %
F ir s t C lo c k
tS
D D
5 0 %
ts
W R , R D
C lo c k
V D D
S
L a s t C lo c k
D D
tO
F F
R
0 .9 V
D D
tR
S T D
G N D
C S
Figure 3
Figure 4 Power-on Reset Timing
Rev. 3.20
7
November 25, 2014
PATENTED
HT1621/HT1621G
Functional Description
Display Memory - RAM
S E G 0
0
system power down command. But if the external clock
source is chosen as the system clock, using the SYS
DIS command can neither turn the oscillator off nor
carry out the power down mode. The crystal oscillator
option can be applied to connect an external frequency
source of 32kHz to the OSCI pin. In this case, the system fails to enter the power down mode, similar to the
case in the external 256kHz clock source operation. At
the initial system power on, the HT1621 is at the SYS
DIS state.
S E G 1
1
Time Base and Watchdog Timer (WDT)
S E G 2
2
S E G 3
3
S E G 3 1
3 1
The static display memory (RAM) is organized into 32´4
bits and stores the displayed data. The contents of the
RAM are directly mapped to the contents of the LCD
driver. Data in the RAM can be accessed by the READ,
WRITE, and READ-MODIFY-WRITE commands. The
following is a mapping from the RAM to the LCD pattern:
C O M 3
D 3
C O M 2
D 2
C O M 1
C O M 0
D 1
D 0
The time base generator is comprised by an 8-stage
count-up ripple counter and is designed to generate an
accurate time base. The watch dog timer (WDT), on the
other hand, is composed of an 8-stage time base generator along with a 2-stage count-up counter, and is designed to break the host controller or other subsystems
from abnormal states such as unknown or unwanted
jump, execution errors, etc. The WDT time-out will result
in the setting of an internal WDT time-out flag. The outputs of the time base generator and of the WDT time-out
flag can be connected to the IRQ output by a command
option. There are totally eight frequency sources available for the time base generator and the WDT clock.
The frequency is calculated by the following equation.
A d d r e s s 6 b its
(A 5 , A 4 , ..., A 0 )
A d d r
D a ta
D a ta 4 b its
(D 3 , D 2 , D 1 , D 0 )
RAM Mapping
System Oscillator
32kHz
2n
where the value of n ranges from 0 to 7 by command options. The 32kHz in the above equation indicates that
the source of the system frequency is derived from a
crystal oscillator of 32.768kHz, an on-chip oscillator
(256kHz), or an external frequency of 256kHz.
fWDT =
The HT1621 system clock is used to generate the time
base/Watchdog Timer (WDT) clock frequency, LCD
driving clock, and tone frequency. The source of the
clock may be from an on-chip RC oscillator (256kHz), a
crystal oscillator (32.768kHz), or an external 256kHz
clock by the S/W setting. The configuration of the system oscillator is as shown. After the SYS DIS command
is executed, the system clock will stop and the LCD bias
generator will turn off. That command is, however, available only for the on-chip RC oscillator or for the crystal
oscillator. Once the system clock stops, the LCD display
will become blank, and the time base/WDT lose its function as well.
If an on-chip oscillator (256kHz) or an external 256kHz
frequency is chosen as the source of the system frequency, the frequency source is by default prescaled to
32kHz by a 3-stage prescaler. Employing both the time
base generator and the WDT related commands, one
should be careful since the time base generator and
WDT share the same 8-stage counter. For example, invoking the WDT DIS command disables the time base
generator whereas executing the WDT EN command
not only enables the time base generator but activates
the WDT time-out flag output (connect the WDT
The LCD OFF command is used to turn the LCD bias
generator off. After the LCD bias generator switches off
by issuing the LCD OFF command, using the SYS DIS
command reduces power consumption, serving as a
O S C I
O S C O
C r y s ta l O s c illa to r
3 2 7 6 8 H z
E x te r n a l C lo c k S o u r c e
2 5 6 k H z
S y s te m
C lo c k
1 /8
O n - c h ip R C O s c illa to r
2 5 6 k H z
System Oscillator Configuration
Rev. 3.20
8
November 25, 2014
PATENTED
S y s te m C lo c k
f= 3 2 k H z
T im e r /W D T
C lo c k S o u r c e s
/2 n
n = 0 ~ 7
T IM E R
/2 5 6
V
W D T
/4
HT1621/HT1621G
E N /D IS
IR Q
W D T E N /D IS
D D
Q
D
C K
C L R
IR Q
E N /D IS
R
W D T
Timer and WDT Configurations
Tone Output
time-out flag to the IRQ pin). After the TIMER EN command is transferred, the WDT is disconnected from the
IRQ pin, and the output of the time base generator is connected to the IRQ pin. The WDT can be cleared by executing the CLR WDT command, and the contents of the time
base generator is cleared by executing the CLR WDT or
the CLR TIMER command. The CLR WDT or the CLR
TIMER command should be executed prior to the WDT
EN or the TIMER EN command respectively. Before executing the IRQ EN command the CLR WDT or CLR
TIMER command should be executed first. The CLR
TIMER command has to be executed before switching
from the WDT mode to the time base mode. Once the
WDT time-out occurs, the IRQ pin will stay at a logic low
level until the CLR WDT or the IRQ DIS command is issued. After the IRQ output is disabled the IRQ pin will remain at the floating state. The IRQ output can be
enabled or disabled by executing the IRQ EN or the IRQ
DIS command, respectively. The IRQ EN makes the
output of the time base generator or of the WDT time-out
flag appear on the IRQ pin. The configuration of the time
base generator along with the WDT are as shown. In the
case of on-chip RC oscillator or crystal oscillator, the
power down mode can reduce power consumption
since the oscillator can be turned on or off by the corresponding system commands. At the power down mode
the time base/WDT loses all its functions.
A simple tone generator is implemented in the HT1621.
The tone generator can output a pair of differential driving signals on the BZ and BZ, which are used to generate a single tone. By executing the TONE4K and
TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K commands
set the tone frequency to 4kHz and 2kHz, respectively.
The tone output can be turned on or off by invoking the
TONE ON or the TONE OFF command. The tone outputs, namely BZ and BZ, are a pair of differential driving
outputs used to drive a piezo buzzer. Once the system is
disabled or the tone output is inhibited, the BZ and the
BZ outputs will remain at low level.
LCD Driver
The HT1621 is a 128 (32´4) pattern LCD driver. It can be
configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of
LCD driver by the S/W configuration. This feature
makes the HT1621 suitable for multiply LCD applications. The LCD driving clock is derived from the system
clock. The value of the driving clock is always 256Hz even
when it is at a 32.768kHz crystal oscillator frequency, an
on-chip RC oscillator frequency, or an external frequency. The LCD corresponding commands are summarized in the table.
The bold form of 1 0 0, namely 1 0 0, indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first
command, will be omitted. The LCD OFF command
turns the LCD display off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns
the LCD display on by enabling the LCD bias generator.
The BIAS and COM are the LCD panel related com-
On the other hand, if an external clock is selected as the
source of system frequency the SYS DIS command
turns out invalid and the power down mode fails to be
carried out. That is, after the external clock source is selected, the HT1621 will continue working until system
power fails or the external clock source is removed. After the system power on, the IRQ will be disabled.
Name
Command Code
Function
LCD OFF
10000000010X
Turn off LCD outputs
LCD ON
10000000011X
Turn on LCD outputs
1000010abXcX
c=0: 1/2 bias option
c=1: 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
BIAS & COM
Rev. 3.20
9
November 25, 2014
PATENTED
level pulse is required to initialize the serial interface of the
HT1621. The DATA line is the serial data input/output line.
Data to be read or written or commands to be written have
to be passed through the DATA line. The RD line is the
READ clock input. Data in the RAM are clocked out on the
falling edge of the RD signal, and the clocked out data will
then appear on the DATA line. It is recommended that the
host controller read in correct data during the interval between the rising edge and the next falling edge of the RD
signal. The WR line is the WRITE clock input. The data,
address, and command on the DATA line are all clocked
into the HT1621 on the rising edge of the WR signal. There
is an optional IRQ line to be used as an interface between
the host controller and the HT1621. The IRQ pin can be
selected as a timer output or a WDT overflow flag output
by the S/W setting. The host controller can perform the
time base or the WDT function by being connected with
the IRQ pin of the HT1621.
mands. Using the LCD related commands, the HT1621
can be compatible with most types of LCD panels.
Command Format
The HT1621 can be configured by the S/W setting. There
are two mode commands to configure the HT1621 resources and to transfer the LCD display data. The configuration mode of the HT1621 is called command mode, and
its command mode ID is 1 0 0. The command mode consists of a system configuration command, a system
frequency selection command, a LCD configuration command, a tone frequency selection command, a timer/WDT
setting command, and an operating command. The data
mode, on the other hand, includes READ, WRITE, and
READ-MODIFY-WRITE operations. The following are the
data mode IDs and the command mode ID:
Operation
HT1621/HT1621G
Mode
ID
Read
Data
110
Write
Data
101
Crystal Selection
Read-Modify-Write
Data
101
Command
100
A 32768Hz crystal can be directly connected to the
HT1621 via OSCI and OSCO. In order to obtain the correct frequency, two additional load capacities (C1, C2)
are needed. The value of the capacity depends on how
accurate the crystal is. We suggest that you can follow
the table, which suggests the value of capacities. The
table illustrates the suggestion value of capacities (C1,
C2).
Command
The mode command should be issued before the data
or command is transferred. If successive commands
have been issued, the command mode ID, namely 1 0 0,
can be omitted. While the system is operating in the
non-successive command or the non-successive address data mode, the CS pin should be set to ²1² and the
previous operation mode will be reset also. Once the CS
pin returns to ²0² a new operation mode ID should be issued first.
3 2 7 6 8 H z
O S C I
O S C O
C 1
C 2
Interfacing
Only four lines are required to interface with the
HT1621. The CS line is used to initialize the serial interface circuit and to terminate the communication between
the host controller and the HT1621. If the CS pin is set to 1,
the data and command issued between the host controller
and the HT1621 are first disabled and then initialized. Before issuing a mode command or mode switching, a high
Crystal Error
Capacity Value
±10ppm
0~10p
10~20ppm
10~20p
Timing Diagrams
READ Mode (Command Code : 1 1 0)
C S
W R
R D
D A T A
Rev. 3.20
1
1
0
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 )
10
1
1
0
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
November 25, 2014
PATENTED
HT1621/HT1621G
READ Mode (Successive Address Reading)
C S
W R
R D
1
D A T A
0
1
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )
M e m o ry A d d re s s (M A ) D a ta (M A )
WRITE Mode (Command Code : 1 0 1)
C S
W R
1
D A T A
1
0
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 )
1
1
0
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
WRITE Mode (Successive Address Writing)
C S
W R
1
D A T A
0
1
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )
M e m o ry A d d re s s (M A ) D a ta (M A )
Read-Modify-Write Mode (Command Code : 1 0 1)
C S
W R
R D
D A T A
Rev. 3.20
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3
M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 ) D a ta (M A 1 )
11
1
0
1
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )
November 25, 2014
PATENTED
HT1621/HT1621G
Read-Modify-Write Mode (Successive Address Accessing)
C S
W R
R D
1
D A T A
1
0
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
M e m o ry A d d re s s (M A ) D a ta (M A )
D a ta (M A )
D a ta (M A + 1 ) D a ta (M A + 1 ) D a ta (M A + 2 )
Command Mode (Command Code : 1 0 0)
C S
W R
1
D A T A
0
0
C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0
C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0
C o m m a n d 1
C o m m a n d ...
C o m m a n d i
C o m m a n d
o r
D a ta M o d e
Mode (Data and Command Mode)
C S
W R
D A T A
C o m m a n d
o r
D a ta M o d e
A d d re s s & D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
C o m m a n d
o r
D a ta M o d e
A d d re s s a n d D a ta
R D
Note:
It is recommended that the host controller should read in the data from the DATA line between the rising edge
of the RD line and the falling edge of the next RD line.
Rev. 3.20
12
November 25, 2014
PATENTED
HT1621/HT1621G
Application Circuits
Host Controller with an HT1621 Display System
C S
*
V D D
R D
W R
C lo c k
*
H T 1 6 2 1 B
B Z
R
P e z o
IR Q
u t
B Z
S C I
S C
E x te r n a l C o lc k 1
V R
V L C D
D A T A
M C U
*
C
M 0 ~ C
M 3
S E G 0 ~ S E G 3 1
E x te r n a l C o lc k 2
n -c h p
S C
1 /2 o r 1 /3 B a s ; 1 /2 , 1 /3 o r 1 /4 D u ty
L C D
C ry s ta l
3 2 7 6 8 H z
P a n e l
C 1
C 2
Note:
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU.
The voltage applied to VLCD pin must be equal to or lower than VDD.
Adjust VR to fit user's LCD panel display voltage (VLCD)
Adjust R (external pull-high resistance) to fit user¢s time base clock.
In order to obtain the correct frequency, two additional load capacities (C1, C2) are needed. The value of the
capacity depends on how accurate the crystal is. We suggest that you can follow the table, which suggests the
value of capacities.
The table illustrates the suggestion value of capacities (C1,C2)
Crystal Error
Capacity Value
±10ppm
0~10p
10~20ppm
10~20p
Command Summary
ID
Command Code
D/C
READ
Name
110
A5A4A3A2A1A0D0D1D2D3
D
Read data from the RAM
WRITE
101
A5A4A3A2A1A0D0D1D2D3
D
Write data to the RAM
READ-MODIFYWRITE
101
A5A4A3A2A1A0D0D1D2D3
D
READ and WRITE to the RAM
SYS DIS
100
0000-0000-X
C
Turn off both system oscillator and LCD
Yes
bias generator
SYS EN
100
0000-0001-X
C
Turn on system oscillator
LCD OFF
100
0000-0010-X
C
Turn off LCD bias generator
LCD ON
100
0000-0011-X
C
Turn on LCD bias generator
TIMER DIS
100
0000-0100-X
C
Disable time base output
WDT DIS
100
0000-0101-X
C
Disable WDT time-out flag output
TIMER EN
100
0000-0110-X
C
Enable time base output
WDT EN
100
0000-0111-X
C
Enable WDT time-out flag output
Rev. 3.20
13
Function
Def.
Yes
November 25, 2014
PATENTED
Name
ID
Command Code
D/C
HT1621/HT1621G
Function
Def.
TONE OFF
100
0000-1000-X
C
Turn off tone outputs
TONE ON
100
0000-1001-X
C
Turn on tone outputs
CLR TIMER
100
0000-11XX-X
C
Clear the contents of time base generator
CLR WDT
100
0000-111X-X
C
Clear the contents of WDT stage
XTAL 32K
100
0001-01XX-X
C
System clock source, crystal oscillator
RC 256K
100
0001-10XX-X
C
System clock source, on-chip RC oscillator
EXT 256K
100
0001-11XX-X
C
System clock source, external clock source
C
LCD 1/2 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
BIAS 1/2
BIAS 1/3
100
0010-abX0-X
100
0010-abX1-X
C
LCD 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
Yes
TONE 4K
100
010X-XXXX-X
C
Tone frequency, 4kHz
TONE 2K
100
011X-XXXX-X
C
Tone frequency, 2kHz
IRQ DIS
100
100X-0XXX-X
C
Disable IRQ output
IRQ EN
100
100X-1XXX-X
C
Enable IRQ output
F1
100
101X-X000-X
C
Time base/WDT clock output:1Hz
The WDT time-out flag after: 4s
F2
100
101X-X001-X
C
Time base/WDT clock output:2Hz
The WDT time-out flag after: 2s
F4
100
101X-X010-X
C
Time base/WDT clock output:4Hz
The WDT time-out flag after: 1s
F8
100
101X-X011-X
C
Time base/WDT clock output:8Hz
The WDT time-out flag after: 1/2s
F16
100
101X-X100-X
C
Time base/WDT clock output:16Hz
The WDT time-out flag after: 1/4s
F32
100
101X-X101-X
C
Time base/WDT clock output:32Hz
The WDT time-out flag after: 1/8s
F64
100
101X-X110-X
C
Time base/WDT clock output:64Hz
The WDT time-out flag after: 1/16s
F128
100
101X-X111-X
C
Time base/WDT clock output:128Hz
The WDT time-out flag after: 1/32s
TEST
100
1110-0000-X
C
Test mode, user don¢t use.
NORMAL
100
1110-0011-X
C
Normal mode
Note:
Yes
Yes
Yes
Yes
X : Don,t care
A5~A0 : RAM addresses
D3~D0 : RAM data
D/C : Data/command mode
Def. : Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command
mode ID. If successive commands have been issued, the command mode ID except for the first command will
be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from
an on-chip 256kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 256kHz clock. Calculation of the
frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1621 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1621.
Rev. 3.20
14
November 25, 2014
PATENTED
HT1621/HT1621G
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for the
latest version of the Package/Carton Information.
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 3.20
15
November 25, 2014
PATENTED
HT1621/HT1621G
44-pin LQFP (10mm´10mm) (FP2.0mm) Outline Dimensions
H
C
D
G
2 3
3 3
I
3 4
2 2
F
A
B
E
1 2
4 4
K
a
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
¾
0.472 BSC
¾
B
¾
0.394 BSC
¾
C
¾
0.472 BSC
¾
D
¾
0.394 BSC
¾
E
¾
0.032 BSC
¾
F
0.012
0.015
0.018
G
0.053
0.055
0.057
H
¾
¾
0.063
I
0.002
¾
0.006
J
0.018
0.024
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 3.20
1 1
Dimensions in mm
Min.
Nom.
Max.
A
¾
12.00 BSC
¾
B
¾
10.00 BSC
¾
C
¾
12.00 BSC
¾
D
¾
10.00 BSC
¾
E
¾
0.80 BSC
¾
F
0.30
0.37
0.45
G
1.35
1.40
1.45
H
¾
¾
1.60
I
0.05
¾
0.15
J
0.45
0.60
0.75
K
0.09
¾
0.20
a
0°
¾
7°
16
November 25, 2014
PATENTED
HT1621/HT1621G
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
1
2 4
C
C '
G
H
D
E
Symbol
F
Dimensions in inch
Min.
Nom.
Max.
A
0.395
¾
0.420
B
0.291
0.295
0.299
C
0.008
¾
0.014
C¢
0.620
0.625
0.630
D
0.095
0.102
0.110
E
¾
0.025 BSC
¾
F
0.008
0.012
0.016
G
0.020
¾
0.040
H
0.005
¾
0.010
a
0°
¾
8°
Symbol
Rev. 3.20
a
Dimensions in mm
Min.
Nom.
Max.
10.67
A
10.03
¾
B
7.39
7.49
7.59
C
0.20
¾
0.34
C¢
15.75
15.88
16.00
D
2.41
2.59
2.79
E
¾
0.64 BSC
¾
F
0.20
0.30
0.41
G
0.51
¾
1.02
H
0.13
¾
0.25
a
0°
¾
8°
17
November 25, 2014
PATENTED
HT1621/HT1621G
48-pin LQFP (7mm´7mm) Outline Dimensions
C
H
D
3 6
G
2 5
I
3 7
2 4
F
A
B
E
4 8
1 3
K
a
J
1
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
¾
0.354 BSC
¾
B
¾
0.276 BSC
¾
C
¾
0.354 BSC
¾
D
¾
0.276 BSC
¾
E
¾
0.020 BSC
¾
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
¾
¾
0.063
I
0.002
¾
0.006
J
0.018
0.024
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 3.20
1 2
Dimensions in mm
Min.
Nom.
Max.
A
¾
9.00 BSC
¾
B
¾
7.00 BSC
¾
C
¾
9.00 BSC
¾
D
¾
7.00 BSC
¾
E
¾
0.50 BSC
¾
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
¾
¾
1.60
I
0.05
¾
0.15
J
0.45
0.60
0.75
K
0.09
¾
0.20
a
0°
¾
7°
18
November 25, 2014
PATENTED
HT1621/HT1621G
Copyright Ó 2014 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and
Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a
risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use
as critical components in life support devices or systems. Holtek reserves the right to alter its
products without prior notification. For the most up-to-date information, please visit our web
site at http://www.holtek.com.tw.
Rev. 3.20
19
November 25, 2014
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