HT1625

HT1625 RAM Mapping 64´8 LCD Controller for I/O MCU Features · Operating voltage: 2.7V~5.2V · Built-in LCD display RAM · Built-in RC oscillator · R/W address auto increment · External 32.768kHz crystal or 32kHz frequency · Two selectable buzzer frequencies (2kHz or 4kHz) source input · Power down command reduces power consumption · 1/4 bias, 1/8 duty, frame frequency is 64Hz · Software configuration feature · Max. 64´8 patterns, 8 commons, 64 segments · Data mode and Command mode instructions · Built-in internal resistor type bias generator · Three data accessing modes · 3-wire serial interface · VLCD pin to adjust LCD operating voltage · 8 kinds of time base or WDT selection · Cascade application · Time base or WDT overflow output · 100-pin QFP package General Description HT1625 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT1625. The HT162X series have many kinds of products that match various applications. HT1625 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 512 patterns (64´8). It also supports serial interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1625 is a memory mapping and multi-function LCD controller. The software configuration feature of the Selection Table HT162X HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 COM 4 4 8 8 8 8 16 SEG 32 32 32 32 48 64 48 Built-in Osc. ¾ Ö Ö ¾ Ö Ö Ö Crystal Osc. Ö Ö ¾ Ö Ö Ö Ö Block Diagram D is p la y R A M O S C O O S C I C S R D W R C o n a n T im C ir c tro l d in g u it C O M 0 L C D D r iv e r / B ia s C ir c u it D A T A S E G 0 V D D S E G 6 3 V S S V L C D B Z B Z Rev. 1.10 C O M 7 T o n e F re q u e n c y G e n e ra to r W a tc h d o g T im e r a n d T im e B a s e G e n e r a to r 1 IR Q September 11, 2002 HT1625 Pin Assignment S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 W R D A T A V S S O S C I O S C O V D D V L C D IR Q B Z B Z T 1 T 2 T 3 N C C O M 0 C O M 1 C O M 2 C O M 3 N C N C N C N C C O M 4 N C C O M 5 N C C O M 6 N C 6 1 6 2 6 3 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 C S R D 1 8 0 2 7 9 3 7 8 4 7 7 5 7 6 6 7 5 7 7 4 8 7 3 9 7 2 1 0 7 1 1 1 7 0 1 2 6 9 1 3 6 8 1 4 6 7 H T 1 6 2 5 1 0 0 Q F P -A 1 5 1 6 1 7 6 6 6 5 6 4 1 8 6 3 1 9 6 2 2 0 6 1 2 1 6 0 2 2 5 9 2 3 5 8 2 4 5 7 2 5 5 6 2 6 5 5 2 7 5 4 2 8 5 3 2 9 3 0 5 2 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 S E N C S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E S E N C N C S E S E S E S E G 4 3 G 4 G 4 G 4 G 3 G 3 G 3 G 3 G 3 G 3 G 3 G 3 G 3 G 3 G 2 G 2 G 2 G 2 G 2 G 2 G 2 G 2 G 2 G 2 G 1 G 1 G 1 0 9 8 7 1 2 3 4 5 9 0 4 3 2 1 2 1 5 8 6 7 6 9 0 8 7 S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G S E G N C N C C O M 1 6 1 5 1 4 1 3 1 2 1 1 2 1 0 9 8 7 6 5 4 3 2 1 0 7 Rev. 1.10 September 11, 2002 HT1625 Pad Assignment 6 9 6 8 S E G 4 3 7 0 S E G 4 4 S E G 4 5 S E G 4 6 8 1 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 S E G 4 7 S E G 4 8 S E G 4 9 S E G 5 0 S E G 5 1 S E G 5 2 S E G 5 3 S E G 5 4 S E G 5 5 S E G 5 6 S E G 5 7 S E G 5 8 S E G 5 9 S E G 6 0 S E G 6 2 V S S S E G 6 1 D A T A S E G 6 3 C S 8 7 8 6 8 5 8 4 8 3 8 2 1 R D 6 7 6 6 2 W R 3 4 5 O S C I 6 O S C O 7 V D D 6 5 S E G 4 2 6 4 S E G 4 1 6 3 S E G 4 0 6 2 S E G 3 9 6 1 S E G 3 8 6 0 S E G 3 7 5 9 S E G 3 6 V L C D 8 5 8 S E G 3 5 IR Q 9 5 7 S E G 3 4 B Z 1 0 5 6 S E G 3 3 B Z 1 1 5 5 S E G 3 2 T 1 1 2 T 2 1 3 5 4 S E G 3 1 T 3 1 4 5 3 S E G 3 0 C O M 0 1 5 5 2 C O M 1 1 6 S E G 2 9 5 1 C O M 2 S E G 2 8 1 7 C O M 3 1 8 5 0 S E G 2 7 4 9 S E G 2 6 C O M 4 (0 , 0 ) 1 9 S E G 1 9 S E G 1 8 S E G 1 7 S E G 1 6 S E G 1 5 S E G 1 4 S E G 1 3 S E G 1 2 S E G 1 1 S E G 1 0 S E G 9 S E G 8 S E G 7 S E G 6 S E G 5 S E G 4 S E G 3 S E G 2 C O M 5 S E G 1 4 2 S E G 0 4 0 4 1 C O M 7 3 8 3 9 C O M 6 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 4 8 S E G 2 5 4 7 S E G 2 4 4 6 S E G 2 3 4 5 S E G 2 2 4 4 S E G 2 1 4 3 S E G 2 0 Chip size: 192 ´ 211 (mil)2 * The IC substrate should be connected to VDD in the PCB layout artwork. Rev. 1.10 3 September 11, 2002 HT1625 Pad Coordinates Unit: mil Pad No. X Y Pad No. X Y 1 -90.18 98.56 45 90.57 -84.53 2 -90.18 91.93 46 90.57 -77.90 3 -90.18 85.30 47 89.80 -68.13 4 -90.18 75.95 48 89.80 -61.50 5 -89.42 57.76 49 89.80 -49.51 6 -89.42 45.77 50 89.80 -42.88 7 -90.18 39.14 51 89.80 -30.90 8 -90.18 32.51 52 89.80 -24.27 9 -90.18 25.03 53 89.80 -12.28 10 -90.18 15.94 54 89.80 11 -90.18 5.82 55 89.80 -5.65 6.33 12 -90.18 -3.61 56 89.80 12.96 13 -90.18 -10.24 57 89.80 24.95 14 -90.18 -16.87 58 89.80 31.58 15 -90.18 -23.50 59 89.80 43.56 16 -90.18 -30.13 60 89.80 50.19 17 -90.18 -36.76 61 89.80 62.18 18 -90.18 -43.39 62 89.80 68.81 19 -90.18 -92.22 63 89.80 80.79 20 -83.17 -99.53 64 89.80 87.42 21 -76.54 -99.53 65 89.38 98.22 22 -69.91 -99.53 66 77.39 98.22 23 -63.28 -99.53 67 70.76 98.22 24 -56.65 -99.53 68 58.78 98.22 25 -50.02 -99.53 69 52.15 98.22 26 -43.39 -99.53 70 40.16 98.22 27 -36.76 -99.53 71 32.09 99.32 28 -30.13 -99.53 72 25.46 99.32 29 -23.50 -99.53 73 18.83 99.32 30 -16.87 -99.53 74 12.20 99.32 31 -10.24 -99.53 75 5.57 99.32 32 -99.53 76 -1.06 99.32 33 -3.61 3.02 -99.53 77 -7.69 99.32 34 9.65 -99.53 78 -14.32 99.32 35 16.28 -99.53 79 -20.95 99.32 36 22.91 -99.53 80 -27.58 99.32 37 29.54 -98.60 81 -34.21 99.32 38 41.52 -98.60 82 -40.84 99.32 39 48.15 -98.60 83 -47.47 99.32 40 60.14 -98.60 84 -54.10 99.32 41 66.77 -98.60 85 -60.73 99.32 42 78.75 -98.60 86 -67.36 99.32 43 90.57 -97.79 87 -73.99 99.32 44 90.57 -91.16 Rev. 1.10 4 September 11, 2002 HT1625 Pad Description Pad No. Pad Name I/O Description 1 RD I READ clock input with pull-high resistor. Data in the RAM of the HT1625 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. 2 WR I WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1625 on the rising edge of the WR signal. 3 DATA I/O Serial data input or output with pull-high resistor 4 VSS ¾ Negative power supply, ground 5 OSCI I 6 OSCO O 7 VDD ¾ 8 VLCD I LCD operating voltage input pad. 9 IRQ O Time base or Watchdog Timer overflow flag, NMOS open drain output 10, 11 BZ, BZ O 2kHz or 4kHz tone frequency output pair 12~14 T1~T3 I Not connected 15~22 COM0~COM7 O LCD common outputs 23~86 SEG0~SEG63 O LCD segment outputs I Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or write to the HT1625 are disabled. The serial interface circuit is also reset. But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1625 are all enabled. 87 CS The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. Positive power supply Absolute Maximum Ratings Supply Voltage .........................................-0.3V to 5.5V Storage Temperature ............................-50°C to 125°C Input Voltage.............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-25°C to 75°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.10 5 September 11, 2002 HT1625 D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current IDD2 IDD11 IDD22 ISTB VIL VIH IOL1 IOH1 IOL1 IOH1 IOL2 IOH2 IOL3 IOH3 RPH Rev. 1.10 Operating Current Operating Current Operating Current Standby Current Input Low Voltage Input High Voltage BZ, BZ, IRQ BZ, BZ DATA DATA LCD Common Sink Current LCD Common Source Current LCD Segment Sink Current LCD Segment Source Current Pull-high Resistor Ta=25°C Test Conditions Min. Typ. Max. Unit 2.7 ¾ 5.2 V No load or LCD ON On-chip RC oscillator ¾ 155 310 mA ¾ 260 420 mA No load or LCD ON Crystal oscillator ¾ 150 310 mA ¾ 250 420 mA No load or LCD OFF On-chip RC oscillator ¾ 8 30 mA ¾ 20 60 mA No load or LCD OFF Crystal oscillator ¾ ¾ 20 mA ¾ ¾ 35 mA ¾ 1 12 mA VDD Conditions ¾ ¾ 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V No load, Power down mode DATA, WR, CS, RD DATA, WR, CS, RD ¾ 2 24 mA 0 ¾ 0.6 V 0 ¾ 1.0 V 2.4 ¾ 3 V 4.0 ¾ 5 V 0.9 1.8 ¾ mA 1.7 3 ¾ mA -0.9 -1.8 ¾ mA 3V VOL=0.3V 5V VOL=0.5V 3V VOH=2.7V 5V VOH=4.5V -1.7 -3 ¾ mA 3V VOL=0.3V 0.9 1.8 ¾ mA 5V VOL=0.5V 1.7 3 ¾ mA 3V VOH=2.7V -0.9 -1.8 ¾ mA 5V VOH=4.5V -1.7 -3 ¾ mA 3V VOL=0.3V 80 160 ¾ mA 5V VOL=0.5V 180 360 ¾ mA 3V VOH=2.7V -40 -80 ¾ mA 5V VOH=4.5V -90 -180 ¾ mA 3V VOL=0.3V 50 100 ¾ mA 5V VOL=0.5V 120 240 ¾ mA 3V VOH=2.7V -30 -60 ¾ mA 5V VOH=4.5V 3V 5V DATA, WR, CS, RD 6 -70 -140 ¾ mA 100 200 300 kW 50 100 150 kW September 11, 2002 HT1625 A.C. Characteristics Symbol fSYS1 fSYS2 Ta=25°C VDD 3V System Clock 5V 3V System Clock 5V fLCD1 LCD Frame Frequency fLCD2 LCD Frame Frequency tCOM LCD Common Period fCLK1 Test Conditions Parameter 3V 5V 3V 5V ¾ 3V Serial Data Clock (WR Pin) 5V 3V fCLK2 Serial Data Clock (RD Pin) tCS Serial Interface Reset Pulse Width (Figure 3) 5V ¾ 3V tCLK WR, RD Input Pulse Width (Figure 1) 5V t r, t f Rise or Fall Time Serial Data Clock Width (Figure 1) 3V tsu Setup Time for DATA to WR, RD Clock Width (Figure 2) 3V th Hold Time for DATA to WR, RD Clock Width (Figure 2) 3V tsu1 Setup Time for CS to WR, RD Clock Width (Figure 3) 3V th1 Hold Time for CS to WR, RD Clock Width (Figure 3) 3V Conditions On-chip RC oscillator External clock source On-chip RC oscillator External clock source Min. Typ. Max. Unit 22 32 40 kHz 24 32 40 kHz ¾ 32 ¾ kHz kHz ¾ 32 ¾ 44 64 80 Hz 48 64 80 Hz ¾ 64 ¾ Hz ¾ 64 ¾ Hz ¾ n/fLCD ¾ sec ¾ ¾ 150 kHz ¾ ¾ 300 kHz ¾ ¾ 75 kHz ¾ ¾ 150 kHz ¾ 250 ¾ ns Write mode 3.34 ¾ ¾ Read mode 6.67 ¾ ¾ Write mode 1.67 ¾ ¾ Read mode 3.34 ¾ ¾ ¾ ¾ 120 ¾ ns ¾ ¾ 120 ¾ ns ¾ ¾ 120 ¾ ns ¾ ¾ 100 ¾ ns ¾ ¾ 100 ¾ ns n: Number of COM Duty cycle 50% Duty cycle 50% CS 5V 5V 5V 5V 5V ms V A L ID D A T A ms tf W R , R D C lo c k 9 0 % 5 0 % 1 0 % tr tC V tC L K D B D D ts G N D Figure 1 W R , R D C lo c k S V th u 1 5 0 % F IR S T C lo c k G N D G N D 1 V L A S T C lo c k D D D D 5 0 % ts V 5 0 % Figure 2 tC C S D D G N D th u L K W R , R D C lo c k V 5 0 % D D G N D Figure 3 Rev. 1.10 7 September 11, 2002 HT1625 Functional Description Display memory - RAM structure If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. The static display RAM is organized into 128´4 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. Buzzer tone output A simple tone generator is implemented in the HT1625. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. Time base and Watchdog Timer - WDT The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR , WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at logic low level until the CLR WDT or the IRQ DIS command is issued. C O M 7 C O M 6 C O M 5 Command format The HT1625 can be configured by the software setting. There are two mode commands to configure the HT1625 resource and to transfer the LCD display data. C O M 3 C O M 4 C O M 2 C O M 1 C O M 0 S E G 0 1 0 S E G 1 3 2 S E G 2 5 4 S E G 3 7 6 S E G 6 3 1 2 7 D 3 D 2 D 1 D 0 A d d r e s s 7 B its (A 6 , A 5 , ...., A 0 ) 1 2 6 A d d r D 3 D a ta D 2 D 1 D 0 A d d r D a ta D a ta 4 B its (D 3 , D 2 , D 1 , D 0 ) RAM mapping T im e B a s e T IM E R /2 5 6 C lo c k S o u r c e V C L R T im e r W D T E N /D IS D D W D T /4 Q D C K C L R IR Q E N /D IS IR Q E N /D IS R W D T Timer and WDT configurations Rev. 1.10 8 September 11, 2002 HT1625 The following are the data mode ID and the command mode ID: Mode ID READ Operation Data 110 WRITE Data 101 READ-MODIFY-WRITE Data 101 Command 100 COMMAND Name If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to ²1² and the previous operation mode will be reset also. The CS pin returns to ²0², a new operation mode ID should be issued first. Command Code Function TONE OFF 0000-1000-X Turn-off tone output TONE 4K 010X-XXXX-X Turn-on tone output, tone frequency is 4kHz TONE 2K 0110-XXXX-X Turn-on tone output, tone frequency is 2kHz Timing Diagrams READ mode (command code : 1 1 0) C S W R R D D A T A 1 0 1 A 6 A 5 A 4 A 3 A 2 A 1 A 0 M e m o ry A d d re s s 1 (M A 1 ) D 0 D 2 D 1 D 3 1 0 1 A 5 A 6 D a ta (M A 1 ) A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3 D a ta (M A 2 ) M e m o ry A d d re s s 2 (M A 2 ) READ mode (successive address reading) C S W R R D D A T A 1 1 0 A 6 A 5 A 4 A 3 A 2 A 1 M e m o ry A d d re s s (M A ) Rev. 1.10 A 0 D 0 D 1 D 2 D a ta (M A ) 9 D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D a ta (M A + 2 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 3 ) September 11, 2002 HT1625 WRITE mode (command code : 1 0 1) C S W R 1 D A T A 1 0 A 5 A 6 A 3 A 4 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 1 (M A 1 ) D 2 D 1 D 3 1 1 0 A 5 A 6 D a ta (M A 1 ) A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 2 (M A 2 ) D 2 D 1 D 3 D a ta (M A 2 ) WRITE mode (successive address writing) C S W R 1 D A T A 1 0 A 5 A 6 A 3 A 4 A 2 A 1 A 0 D 0 D 2 D 1 M e m o ry A d d re s s (M A ) D 3 D 0 D a ta (M A ) D 2 D 1 D 3 D 0 D a ta (M A + 1 ) D 1 D 2 D 3 D 0 D a ta (M A + 2 ) D 2 D 1 D 3 D 0 D a ta (M A + 3 ) READ-MODIFY-WRITE mode (command code : 1 0 1) C S W R R D D A T A 1 1 0 A 5 A 6 A 4 A 3 A 2 A 1 A 0 D 0 M e m o ry A d d re s s 1 (M A 1 ) D 2 D 1 D 3 D 0 D a ta (M A 1 ) D 1 D 2 D 3 1 0 1 A 6 D a ta (M A 1 ) A 5 A 4 A 3 A 2 A 1 A 0 M e m o ry A d d re s s 2 (M A 2 ) D 0 D 2 D 1 D 3 D a ta (M A 2 ) READ-MODIFY-WRITE mode (successive address accessing) C S W R R D D A T A 1 0 1 A 6 A 5 A 4 A 3 A 2 A 1 M e m o ry A d d re s s (M A ) Rev. 1.10 A 0 D 0 D 1 D 2 D 3 D a ta (M A ) D 0 D 1 D 2 D a ta (M A ) 10 D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D a ta (M A + 1 ) D 3 D 0 D 1 D 2 D 3 D 0 D a ta (M A + 2 ) September 11, 2002 HT1625 Command mode (command code : 1 0 0) C S W R D A T A 1 0 0 C 8 C 7 C 6 C 5 C 4 C 3 C o m m a n d 1 C 2 C 1 C 0 C 8 C o m m a n d ... C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 C o m m a n d i C o m m a n d o r D a ta M o d e Mode (data and command mode) C S W R D A T A C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta C o m m a n d o r D a ta M o d e A d d re s s a n d D a ta R D Rev. 1.10 11 September 11, 2002 HT1625 Application Circuits C S * V D D R D *V R W R D A T A M C U V L C D H T 1 6 2 5 *R B Z P ie z o IR Q B Z O S C I C lo c k O u t O S C O C O M 0 ~ C O M 7 S E G 0 ~ S E G 6 3 E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) 1 /4 B ia s , 1 /8 D u ty O n - c h ip O S C L C D P a n e l C ry s ta l 3 2 7 6 8 H z The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. Note: The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW±20%. Adjust R (external Pull-high resistance) to fit user¢s time base clock. Instruction Set Summary Name ID Command Code D/C Function Def. READ 1 1 0 A6A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM WRITE 1 0 1 A6A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM READ-MODIFY1 0 1 A6A5A4A3A2A1A0D0D1D2D3 WRITE D Read and Write data to the RAM SYS DIS 1 0 0 0000-0000-X C Turn off both system oscillator and LCD bias Yes generator SYS EN 1 0 0 0000-0001-X C Turn on system oscillator LCD OFF 1 0 0 0000-0010-X C Turn off LCD display LCD ON 1 0 0 0000-0011-X C Turn on LCD display TIMER DIS 1 0 0 0000-0100-X C Disable time base output Yes WDT DIS 1 0 0 0000-0101-X C Disable WDT time-out flag output Yes TIMER EN 1 0 0 0000-0110-X C Enable time base output WDT EN 1 0 0 0000-0111-X C Enable WDT time-out flag output TONE OFF 1 0 0 0000-1000-X C Turn off tone outputs CLR TIMER 1 0 0 0000-1101-X C Clear the contents of the time base generator CLR WDT 1 0 0 0000-1111-X C Clear the contents of the WDT stage RC 32K 1 0 0 0001-10XX-X C System clock source, on-chip RC oscillator EXT (XTAL) 32K 1 0 0 0001-11XX-X C System clock source, external 32kHz clock source or crystal oscillator 32.768kHz Rev. 1.10 12 Yes Yes Yes September 11, 2002 HT1625 Name ID Command Code D/C Function Def. TONE 4K 1 0 0 010X-XXXX-X C Tone frequency output: 4kHz TONE 2K 1 0 0 0110-XXXX-X C Tone frequency output: 2kHz IRQ DIS 1 0 0 100X-0XXX-X C Disable IRQ output IRQ EN 1 0 0 100X-1XXX-X C Enable IRQ output F1 1 0 0 101X-0000-X C Time base clock output: 1Hz The WDT time-out flag after: 4s F2 1 0 0 101X-0001-X C Time base clock output: 2Hz The WDT time-out flag after: 2s F4 1 0 0 101X-0010-X C Time base clock output: 4Hz The WDT time-out flag after: 1s F8 1 0 0 101X-0011-X C Time base clock output: 8Hz The WDT time-out flag after: 1/2s F16 1 0 0 101X-0100-X C Time base clock output: 16Hz The WDT time-out flag after: 1/4s F32 1 0 0 101X-0101-X C Time base clock output: 32Hz The WDT time-out flag after: 1/8s F64 1 0 0 101X-0110-X C Time base clock output: 64Hz The WDT time-out flag after: 1/16s F128 1 0 0 101X-0111-X C Time base clock output: 128Hz The WDT time-out flag after: 1/32s TEST 1 0 0 1110-0000-X C Test mode, user don¢t use. NORMAL 1 0 0 1110-0011-X C Normal mode Note: Yes Yes Yes X : Don¢t care A6~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1625 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1625. Rev. 1.10 13 September 11, 2002 HT1625 Package Information 100-pin QFP (14´20) outline dimensions C H D 8 0 G 5 1 I 5 0 8 1 F A B E 3 1 1 0 0 K = J 1 Symbol A Rev. 1.10 3 0 Dimensions in mm Min. Nom. Max. 18.50 ¾ 19.20 B 13.90 ¾ 14.10 C 24.50 ¾ 25.20 D 19.90 ¾ 20.10 E ¾ 0.65 ¾ F ¾ 0.30 ¾ G 2.50 ¾ 3.10 H ¾ ¾ 3.40 I ¾ 0.10 ¾ J 1 ¾ 1.40 K 0.10 ¾ 0.20 a 0° ¾ 7° 14 September 11, 2002 HT1625 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 15 September 11, 2002