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HT1635D

HT1635D

  • 厂商:

    HOLTEK(合泰)

  • 封装:

    LQFP-64(7x7)

  • 描述:

  • 数据手册
  • 价格&库存
HT1635D 数据手册
HT1635C/HT1635D 44×8 LED Driver Features General Description • Operating voltage: 2.4V~5.5V The HT1635C/HT1635D series is a memory mapping LED display controller/driver. The maximum display capacity of the device is 352 patterns composed of 44 rows and 8 commons. The devices can generate 16 LED illumination levels using software controlled PWM circuitry. A serial interface is provided to allow the device to receive instructions for its command mode and data mode. Only two or four lines are required to interface the device to a host controller. The display capacity can be easily extended by cascading the devices thus expanding its application possibilities. The device is compatible with most microcontrollers offering easy interfacing via its two serial interfaces, an I2C bus or a 4-wire serial bus. • LED display -- 44 row and 8 Columns • 88×4 bit RAM display data storage • 16-level PWM brightness control • Integrated 256kHz RC oscillator • I2C-bus or 4-wire serial interface • Data mode & command mode instructions • Cascade function for extend applications • Selectable NMOS open drain output driver and PMOS open drain output driver for COM lines • 64-pin LQFP package Applications • Industrial control displays • Digital clocks, thermometers, counters, electronic meters • Instrumentation readouts • Other consumer applications • LED displays Selection Table Most features are common to these devices and the main feature distinguishing them is communication interface. In real applications, the recommended operating voltage ranges from 4.5V to 5.5V. The following table summarises the main features of each device. Part No HT1635C VDD Max. Resolution Row×Common Row Source Current (Min.) Row Sink Current (Min.) Com Source Current (Min.) 4.5V~5.5V 44x8 50mA 10mA 45mA HT1635D Part No HT1635C Com Sink Current (Min.) PWM Gray Scale 250mA 16-Level for Global HT1635D Rev. 1.00 Interface 4-Wire Package 64LQFP IC 2 1 July 09, 2021 HT1635C/HT1635D Block Diagram Display RAM CSB/A0 2 RDB/A1 Control & Timing Circuit WRB/SCL VDD ROW0 DATA/SDA ROW43 LED Driver COM7 COM0 IFS 2 VDD VSS OSC Timing Generator SYNC VSS PWM Control Pin Assignment ROW28 ROW27 ROW26 ROW25 ROW24 ROW23 ROW22 ROW21 ROW20 ROW19 ROW18 ROW17 ROW16 ROW15 ROW14 ROW13 ROW12 ROW11 ROW10 ROW9 ROW8 VDD ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 VSS OSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 HT1635C 41 64 LQFP-A 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 VDD ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 VSS COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS COM0 VDD SYNC CSB RDB WRB DATA Rev. 1.00 2 July 09, 2021 HT1635C/HT1635D ROW28 ROW27 ROW26 ROW25 ROW24 ROW23 ROW22 ROW21 ROW20 ROW19 ROW18 ROW17 ROW16 ROW15 ROW14 ROW13 ROW12 ROW11 ROW10 ROW9 ROW8 VDD ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0 VSS OSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 HT1635D 41 64 LQFP-A 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ROW29 ROW30 ROW31 ROW32 ROW33 ROW34 ROW35 VDD ROW36 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 VSS COM7 COM6 COM5 COM4 COM3 COM2 COM1 VSS COM0 VDD SYNC A0 A1 SCL SDA Pin Description Pin Name I/O Function COM0~COM7 O LED common output lines. ROW0~ROW43 O LED row output lines. VDD — Positive power supply. In PCB Layout that must connect all of the VDD pins to the power plane. VSS — Negative power supply. In PCB Layout that must connect all of the VSS pins to the GND plane. DATA/SDA I/O Serial data input/output pin. Data is input to / comes out from the shift register at rising edge of the clock. • I2C interface serial data (SDA) Input/Output. NMOS open-drain output • 4-wire serial interface serial data input/output. Input has pull-high resistor and output is CMOS type. WRB/SCL I Serial clock input pin. • I2C interface serial clock SCL input. • 4-wire serial interface WRITE Clock (CLK) input. Connected to pull-high resistor. Data on the DATA line is latched into the device on the rising edge of the WRB signal. I • I2C interface device address data input pin. • 4-wire serial interface READ clock input. Connected to pull-high resistor. The device RAM data is clocked out on the falling edge of RDB. The clocked out data will appear on the DATA line. The host controller can use the next rising edge to latch the clocked out data. I • I2C interface device address data input pin. • Chip select input. Connected to pull-high resistor. When CSB is high, a data and command instruction read from or written to the device is disabled and the serial interface circuit is also reset. If CSB is low data and command instruction transmission between the host controller and the device is enabled. I/O • If the RC MASTER MODE command is programmed, the system clock is sourced from the internal RC oscillator and the system clock is output on the OSC pin. • If the SLAVE MODE or EXT CLK MASTER MODE command is programmed, the system clock is sourced from an external clock on the OSC pin. I/O • If the RC MASTER MODE or EXT CLK MASTER MODE command is programmed, the synchronous signal is output on the SYNC pin. • If the SLAVE MODE command is programmed, the synchronous signal is input on the SYNC pin. RDB/A1 CSB/A0 OSC SYNC Rev. 1.00 3 July 09, 2021 HT1635C/HT1635D Absolute Maximum Ratings Power Dissipation (PD)(@Ta=25˚C)....................2.5W Supply Voltage........................... VSS-0.3V to VSS+6.0V (@Ta=85˚C)....................1.0W Max junction Temperature (Tj)........................... 125˚C Input Voltage............................. VSS-0.3V to VDD+0.3V Storage Temperature............................. -50˚C to 125˚C Thermal Resistance (Rth).................................40˚C/W Operating Temperature........................... -40˚C to 85˚C Note: 1. These are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. 2. For the actual usage, please refer to the PD-Ta characteristics diagram in the package specification, follow the power supply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. D.C. Characteristics Symbol Parameter VDD=2.4V~5.5V; Ta=25°C Test Conditions Min. Typ. Max. Unit 2.4 5 5.5 V — 0.3 0.6 mA 5V No load, Power down mode — 1 2 μA Input Low Voltage DATA, WRB, RDB, SDA, SCL, 5V CSB, OSC, SYNC 0 — 0.3VDD V VIH Input High Voltage 5V 0.7VDD — 5 V IOL1 OSC, SYNC, DATA, SDA Pins Sink Current 5V VOL=0.5V 18 25 — mA IOH1 OSC, SYNC, DATA Pins Source Current 5V VOH=4.5V -10 -13 — mA IOL2 ROW Sink Current 5V VOL=0.5V 10 13 — mA IOH2 ROW Source Current 5V VOH=4.5V -50 -70 — mA IOL3 COM Sink Current 5V VOL=0.5V 250 400 — mA IOH3 COM Source Current 5V VOH=4.5V -45 -60 — mA RPH Pull-high Resistor 5V DATA, WRB, RDB, CSB 18 27 40 kΩ VDD Conditions Operating Voltage — — IDD Operating Current No load, LED on, 5V On-chip RC oscillator ISTB Standby Current VIL VDD Rev. 1.00 DATA, WRB, RDB, SDA, SCL, CSB, OSC, SYNC 4 July 09, 2021 HT1635C/HT1635D A.C. Characteristics I2C Serial Bus VDD=2.4V~5.5V, Ta=25°C Symbol Parameter Condition — VDD=2.4V to 5.5V VDD=3.0V to 5.5V Unit Min. Max. Min. Max. — 100 — 400 kHz 4.7 — 1.3 — μs 4 — 0.6 — μs fSCL Clock Frequency tBUF Bus Free Time Time in which the bus must be free before a new transmission can start tHD: STA Start Condition Hold Time After this period, the first clock pulse is generated tLOW SCL Low Time — 4.7 — 1.3 — μs tHIGH SCL High Time — 4 — 0.6 — μs 4.7 — 0.6 — μs ns Only relevant for repeated START condition tSU: STA Start Condition Setup Time tHD: DAT Data Hold Time — 0 — 0 — tSU: DAT Data Setup Time — 250 — 100 — ns tR SDA and SCL Rise Time Note — 1 — 0.3 μs tF SDA and SCL Fall Time Note — 0.3 — 0.3 μs tSU: STO Stop Condition Setup Time — 4 — 0.6 — μs tAA Output Valid from Clock — — 3.5 — 0.9 μs tSP Input Filter Time Constant (SDA and SCL Pins) — 20 — 20 ns Noise suppression time Note: These parameters are periodically sampled but not 100% tested. SDA tf tLOW tSU:DAT tr tHD:STA tBUF tSP SCL S tHD:STA tHD:DAT tAA tHIGH tSU:STA tSU:STO Sr P S SDA OUT I2C Bus Timing Rev. 1.00 5 July 09, 2021 HT1635C/HT1635D 4-wire Serial Bus VDD=2.4V~5.5V; Ta=25°C Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit kHz fsys System Clock 5V On-chip RC oscillator 230 256 282 fLED LED Frame Rate 5V 1/8 duty — fSYS/2624 — Hz fclk1 Serial Data Clock (WRB Pin) 5V Duty cycle 50% — — 1 MHz fclk2 Serial Data Clock (RDB Pin) 5V Duty cycle 50% tcs Serial Interface Reset Pulse Width — CSB — — 500 kHz 250 — — ns Write mode 0.5 — — Read mode 1 — — tclk WRB, RDB Input Pulse Width 5V μs tr, tf Rise/Fall Time for WRB, RDB Signal (Figure 1) — — — 50 100 ns tsu Setup Time for DATA to WRB Clock Width (Figure 2) — — 50 100 — ns th Hold Time for DATA to WRB Clock Width (Figure 2) — — 100 200 — ns tsu1 Setup Time for CSB to WRB, RDB Clock Width (Figure 3) — — 200 300 — ns th1 Hold Time for CSB to WRB, RDB Clock Width (Figure 3) — — 100 200 — ns tod Data Output Delay Time (Figure 4) — — — 100 200 ns tOFF VDD Off Times (Figure 5) — VDD drop down to 0V 10 — — ms tSR VDD Rising Slew Rate (Figure 5) — — 0.1 — 0.8 V/ms tRSTD Delay Time After Reset (Figure 5) — — 1 — — ms Note: 1. If the conditions of the Power on Reset timing are not satisfied during power ON/OFF, the internal Power on Reset (POR) circuit will not operate normally. 2. During normal operation, if the VDD drops below the minimum voltage as defined in the operating voltage spec, then the conditions for the Power on Reset timing must also be satisfied. This means that VDD must drop to 0V and remain there for 20ms (min.) before rising to the normal operating voltage. 3. Data transfers on the I2C-bus or 4-wire serial bus should be avoided for 1 ms following a power-on to allow the reset sequence to complete Rev. 1.00 6 July 09, 2021 HT1635C/HT1635D tf WRB, RDB Clock tr 90% tCLK 90% 50% 10% 10% tCLK 50% 50% Figure 1 Valid Data Data tsu WRB Clock th 50% Figure 2 CSB 50% tsu1 WRB, RDB Clock 50% 50% th1 tCS 50% 50% First clock Data Figure 3 Last clock 50% tod RDB Clock 50% Figure 4 VDD tSR 0% toff tRSTD 0.9VDD CSB 50% Figure 5 Rev. 1.00 7 July 09, 2021 HT1635C/HT1635D Functional Description clock, using the SYS DIS command can neither turn the oscillator off nor execute the power down mode. The crystal oscillator option can also be used where an external frequency source is connected to the OSC pin. In this case, the system will fail to enter the power down mode, similar to the case for the external clock source operation. After an initial system power on, the device will be in the SYS DIS state. Power-on Reset After power is applied, the devices will be initialised by an internal power-on reset circuit. The status of the internal circuits after initialisation is as follows: • System Oscillator will be off • COM0~COM7 outputs status is high impedance. External Clock Source • The row CMOS outputs will all be low OSC • The LED display will be in an off state SEL bit • Dimming is set to 16/16duty System Clock On-Chip RC Oscillator 256kHz • The Blinking function will be in an off state. SEL bit System Oscillator Configuration Data transfers on the I2C-bus or 4-wire serial bus should be avoided for 1 ms following a power-on to allow the reset initialisation operation to complete. Display Data Address Pointer The address mechanism for the display RAM is implemented using the address pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialisation of the address pointer by the address pointer command. System Oscillator The system clock is used to generate the time base clock frequency LED-driving clock. The clock may be sourced from an on-chip 256kHz RC oscillator or from an external clock using software setups. After the SYS DIS command is executed, the system clock will stop and the LED duty cycle generator will turn off. This command is however available only for the on-chip RC oscillator. Once the system clock stops the LED display will become blank and the time base will also stop functioning. The LED OFF command is used to turn the LED duty cycle generator off. After the LED duty cycle generator switches off by issuing the LED OFF command, using the SYS DIS command will reduce the power consumption, allowing it to operate as a system power down command. However if the external clock source is chosen as the system Blinker The device contains a versatile blinking function. The whole display can be made to flash at frequencies selected by the Blink command. The blinking frequencies are integer multiples of the system frequency. The ratios between the system oscillator and the blinking frequencies depend upon the mode in which the device is operating, as follows: • Blinking frequency = 2Hz ROWn 0.25sec 0.25sec Turn ON Turn OFF Blink ON Blink OFF Example of Waveform for Blinker Display Memory – RAM Structure • The display RAM is a static 88×4-bit RAM which stores the LED data. Logic “1” in the RAM bit-map indicates an “on” state of the corresponding LED Row. Similarly, a logic 0 indicates the “off” state. • There is a one-to-one correspondence between the RAM addresses and the Row outputs, and between the individual bits of a RAM word and the column outputs. The following shows the mapping from the RAM to the LED pattern: COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 ROW0 01H 00H ROW1 03H 02H ROW2 05H 04H Rev. 1.00 8 July 09, 2021 HT1635C/HT1635D COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 ROW3 07H ROW4 09H 06H 08H ROW5 0BH 0AH ROW6 0DH 0CH ROW7 0FH 0EH ROW8 11H 10H ROW9 13H 12H ROW10 15H 14H ROW11 17H 16H ROW12 19H 18H ROW13 1BH 1AH ROW14 1DH 1CH ROW15 1FH 1EH ROW16 21H 20H ROW17 23H 22H ROW18 25H 24H ROW19 27H 26H ROW20 29H 28H ROW21 2BH 2AH ROW22 2DH 2CH ROW23 2FH 2EH ROW24 31H 30H ROW25 33H 32H ROW26 35H 34H ROW27 37H 36H ROW28 39H 38H ROW29 3BH 3AH ROW30 3DH 3CH ROW31 3FH 3EH ROW32 41H 40H ROW33 43H 42H ROW34 45H 44H ROW35 47H 46H ROW36 49H 48H ROW37 4BH 4AH ROW38 4DH 4CH ROW39 4FH 4EH ROW40 51H 50H ROW41 53H 52H ROW42 55H 54H ROW43 57H 56H D3 D2 D1 D0 Addr Data D3 D2 D1 D0 Addr Data 44ROW & 8COM for 88 × 4 Display RAM Note: 1.The LED display RAM address is specified by the Address Set command. The address will be automatically incremented by one after the 4-bit data is shifted in. 2. It is recommended to initialize the display RAM data by clearing all RAM data before the LED display function is activated. If the RAM data is not initialized before enabling the LED display function, it may result in abnormal LED display effect after executing the LED ON command. Rev. 1.00 9 July 09, 2021 HT1635C/HT1635D LED Driver The devices include a 352 (44×8) pattern LED driver. This can be setup in a 44x8 format where the COM outputs can be configured as N-MOS open drain outputs or as P-MOS open drain outputs using software setups. This feature allows the device to be used in multiple LED applications. The LED drive mode waveforms and scanning is as follows: 1. N-MOS Open Drain for 44×8 Driver Mode 1 Frame = 8*328*tSYS 4*tSYS ROWn 328*tSYS ON 8*tSYS OFF ON COM0 OFF ON COM1 OFF ON COM6 OFF ON COM7 OFF VDD OSC SYNC VSS VDD 2.0*tSYS VSS ROWn 8*tSYS COM0 4*tSYS COM7 OSC SYNC 2.0*tSYS Note: tSYS=1/fSYS Rev. 1.00 10 July 09, 2021 HT1635C/HT1635D 2. P-MOS Open Drain for 44×8 Driver Mode 1 Frame = 8*328*tSYS 4*tSYS ROWn 328*tSYS ON 8*tSYS OFF ON COM0 OFF ON COM1 OFF ON COM6 OFF ON COM7 OFF VDD OSC SYNC 2.0*tSYS 2.0*tSYS VSS VDD VSS ROWn 8*tSYS COM0 4*tSYS COM7 OSC SYNC 2.0*tSYS Note: tSYS=1/fSYS Rev. 1.00 11 July 09, 2021 HT1635C/HT1635D Digital Dimming The devices contain versatile dimming functions. The complete display can be dimmed using pulse width modulation techniques for the ROW driver with the Dimming command. The relationship between the ROW and COM digital dimming duty times are shown in the accompanying diagram. On COM ROW (1/16) duty ROW (2/16) duty ROW (3/16) duty ROW (4/16) duty ROW (5/16) duty ROW (6/16) duty ROW (7/16) duty ROW (8/16) duty ROW (9/16) duty ROW (10/16) duty ROW (11/16) duty ROW (12/16) duty ROW (13/16) duty ROW (14/16) duty ROW (15/16) duty ROW (16/16) duty 4*tSYS 1*T Off On Off On 2*T Off On 3*T Off On 4*T Off On 5*T Off On 6*T Off On 7*T Off On 8*T Off On 9*T Off On 10*T Off On 11*T Off On 12*T Off On 13*T Off On 14*T 15*T 16*T Off On Off On Off Note: T=20×tSYS tSYS=1/fSYS Rev. 1.00 12 July 09, 2021 HT1635C/HT1635D 4-wire Serial Interface Interfacing Only four lines are required to interface to the HT1635C. The CSB line is used to initialise the serial interface circuit and to terminate the communication between the host controller and the device. If the CSB pin is set high, the data and command issued between the host controller and the device are first disabled and then initialised. Before issuing a mode command or before mode switching, a high level pulse is required to initialise the device serial interface. The DATA line is the serial data input/output line. Data to be read or written or commands to be written have to be transferred on the DATA line. The RDB line is the READ clock input. Data in the RAM is clocked out on the falling edge of the RDB signal and will appear on the DATA line. It is recommended that the host controller read in the correct data during the interval between the rising edge and the next falling edge of the RDB signal. The WRB line is the WRITE clock input. The data, address, and command on the DATA line are all clocked into the device on the rising edge of the WRB signal. Command Format Software setups are used to configure the devices. There are two mode commands to configure the device resources and to transfer the LED display data. The configurations are setup using the command mode which has a command mode ID of 100. The command mode consists of a system configuration command, a system frequency selection command, an LED configuration command and an operating command. The data mode includes READ, WRITE, and READ-MODIFY-WRITE operations. The accompanying table shows the data and command mode IDs. Mode ID Read Operation Data 110 Write Data 101 Read-Modify-Write Data 101 Command 100 Command The mode command should be issued before any data or other commands are transferred. If successive commands have been issued, the command mode ID, namely 100, can be omitted. While the system is operating in the non-successive command or the nonsuccessive address data mode, the CSB pin should be set to “1” and the previous operation mode will be reset also. Once the CSB pin returns to “0”, a new operation mode ID should be issued first. 4-Wire Timing Diagram Read Mode − ID = 110 CSB WRB RDB DATA 1 1 Data Mode Rev. 1.00 0 A6 A5 A4 A3 A2 A1 Memory Address1 (MA1) A0 D0 D1 D2 D3 Data (MA1) 1 1 0 A6 A5 A4 A3 Memory Address1 (MA2) 13 A2 A1 A0 D0 D1 D2 D3 Data (MA2) July 09, 2021 HT1635C/HT1635D Read Mode − Successive Address Reading CSB WRB RDB 1 DATA 1 0 A6 Data Mode A5 A4 A3 A2 A1 A0 D0 D1 Memory Address (MA1) D2 D3 D0 Data (MA1) D1 D2 D3 D0 D1 D2 D3 D0 Data (MA1+2) Data (MA1+1) D1 D2 D3 D0 Data (MA1+3) D1 D2 D3 D0 D2 D3 Data (MA1+4) Note: After reaching the display memory location 0X57H the pointer will reset to 0X00H. Write Mode − ID = 101 CSB WRB 1 DATA 0 1 A6 A5 Data Mode A4 A3 A2 A1 A0 D0 D1 Memory Address1 (MA1) D2 D3 1 0 1 Data (MA1) A6 A5 A4 A3 A2 A1 A0 D0 D1 Memory Address2 (MA2) Data (MA2) Write Mode − Successive Address Writing CSB WRB DATA 1 0 A6 1 A5 A4 A3 A2 A1 A0 D0 D1 Memory Address (MA1) Data Mode D2 D3 D0 Data (MA1) D1 D2 D3 D0 D1 D2 D3 D0 Data (MA1+2) Data (MA1+1) D1 D2 D3 D0 Data (MA1+3) D1 D2 D3 D0 Data (MA1+4) Note: After reaching the display memory location 0X57H the pointer will reset to 0X00H. Read-Modify-Write Mode − ID = 101 CSB WRB RDB DATA 1 0 1 A6 Data Mode A5 A4 A3 A2 A1 A0 D0 Memory Address1 (MA1) D1 D2 D3 D0 Data (MA1) D1 D2 D3 1 0 Data (MA1) 1 A6 A5 A4 A3 A2 A1 A0 D0 Memory Address2 (MA2) D1 D2 D3 D0 Data (MA2) D1 D2 D3 Data (MA2) Read-Modify-Write Mode − Successive Address Accessing CSB WRB RDB DATA 1 0 1 Data Mode Rev. 1.00 A6 A5 A4 A3 A2 A1 Memory Address (MA) A0 D0 D1 D2 Data (MA) D3 D0 D1 D2 Data (MA) D3 D0 D1 D2 Data (MA+1) 14 D3 D0 D1 D2 Data (MA+1) D3 D0 D1 D2 Data (MA+2) D3 D0 D1 D2 Data (MA+2) D3 D0 D1 D2 Data (MA+3) D3 D0 D1 D2 D3 Data (MA+3) July 09, 2021 HT1635C/HT1635D Command Mode − ID = 100 CSB ~ ~ WRB ~ ~ 1 DATA 0 0 C8 C7 C6 Command Mode C5 C4 C3 C2 C1 C0 C8 ~ ~ C0 C8 C7 C6 C5 Command … Command1 C4 C3 Command n C2 C1 ~ C0 ~ Command or Data mode Command or Data or Address Mode − Data and Command Mode CSB WRB DATA Command or Data mode Address and Data Address and Data Command or Data mode Command or Data mode Address and Data 4-wire Serial Bus Command Summary Name ID Command code D/C Function Def. Read 110 A6A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM Write 101 A6A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM Read-Modify-Write 101 A6A5A4A3A2A1A0D0D1D2D3 D READ and WRITE to the RAM SYS DIS 100 0000-0000-X C Turn off both system oscillator and LED duty cycle generator SYS EN 100 0000-0001-X C Turn on system oscillator LED OFF 100 0000-0010-X C Turn off LED duty cycle generator LED ON 100 0000-0011-X C Turn on LED duty cycle generator Blink OFF 100 0000-1000-X C Turn off blinking function Blink_ON_2Hz 100 0000-1001-X C Turn on 2Hz blinking function Blink_ON_1Hz 100 0000-1010-X C Turn on 1Hz blinking function Blink_ON_0.5Hz 100 0000-1011-X C Turn on 0.5Hz blinking function Slave Mode RC Master Mode0 RC Master Mode1 EXT CLK Master Mode0 EXT CLK MASTER MODE1 100 100 100 100 100 0001-0XXX-X C 0001-100X-X C 0001-101X-X C 0001-110X-X C 0001-111X-X C Yes Yes Yes • • • • Slave mode Clock source from external clock System clock input is on the OSC pin Synchronous signal input is on the SYNC pin • • • • • Master mode Clock source from on-chip RC oscillator OSC pin remains low SYNC pin remains high Single chip application only • • • • Master mode Clock source from on-chip RC oscillator System clock output on the OSC pin Synchronous signal output on the SYNC pin • • • • • Master mode Clock source from external clock, System clock input on the OSC pin SYNC pin remains high Single chip application only • • • • Master mode Clock source from external clock System clock input on the OSC pin Synchronous signal output on the SYNC pin Yes Note: It is not recommended to change between MASTER and SLAVE mode after system enable (SYS_EN=1). Rev. 1.00 15 July 09, 2021 HT1635C/HT1635D Name COM OPTION PWM Duty ID Command code D/C Function 100 0010-aXXX-X C Bit “a” : Open drain type selection a=0: N-MOS a=1: P-MOS 100 101X-0000-X C PWM 1/16 Duty 100 101X-0001-X C PWM 2/16 Duty 100 101X-0010-X C PWM 3/16 Duty 100 101X-0011-X C PWM 4/16 Duty 100 101X-0100-X C PWM 5/16 Duty 100 101X-0101-X C PWM 6/16 Duty 100 101X-0110-X C PWM 7/16 Duty 100 101X-0111-X C PWM 8/16 Duty 100 101X-1000-X C PWM 9/16 Duty 100 101X-1001-X C PWM 10/16 Duty 100 101X-1010-X C PWM 11/16 Duty 100 101X-1011-X C PWM 12/16 Duty 100 101X-1100-X C PWM 13/16 Duty 100 101X-1101-X C PWM 14/16 Duty 100 101X-1110-X C PWM 15/16 Duty 100 101X-1111-X C PWM 16/16 Duty Def. a=0 Yes Note: 1. X: Don’t care 2. A7~A0: RAM addresses 3. D3~D0: RAM data 4. D/C: Data/command mode 5.Def.: Power on reset default 6. All the bold forms, namely 110, 101, and 100, are mode commands. Among these, 100 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base clock frequency can be derived from an on-chip RC oscillator or an external clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialise the device after a power on reset, as if the power on reset fails, this will lead to device malfunction. Rev. 1.00 16 July 09, 2021 HT1635C/HT1635D I2C Serial Interface P SDA Sr The HT1635D includes an I2C serial interface. The I2C bus is a bidirectional, two-line communication link between different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are connected to a positive supply via a pull-up resistor. When the bus is free both lines are high. The output stages of devices connected to the bus must have open-drain or open-collector types in order to implement a wired or function. Data transfer is initiated only when the bus is not busy. SCL S or Sr 8 9 1 2 3-8 9 ACK P or Sr ACK • A slave receiver which is addressed must generate an acknowledge, ACK, after the reception of each byte. • The device that provides an acknowledge must pull down the SDA line during the acknowledge clock pulse so that it remains at a stable low level during the high period of this clock pulse. • A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high during the 9th pulse so as to not acknowledge. The master will generate a STOP or a repeated START condition. SDA SCL Data line stable: Change of data allowed Data valid START And STOP Conditions • A high to low transition on the SDA line while SCL is high defines a START condition. DATA Output By Transmiter • A low to high transition on the SDA line while SCL is high defines a STOP condition. DATA Output By Receiver not acknowledge acknowledge • START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. SCL From Master SDA 2 7 8 9 S clk pulse for acknowledgement Slave Addressing • The device requires an 8-bit slave address word following a start condition to enable the chip for a write operation. The device address words consist of a mandatory one, zero sequence for the first four most significant bits. Refer to the diagram showing the slave Address. This is common to all LED devices. SDA SCL 1 START condition • The bus stays busy if a repeated START(Sr) is generated instead of a STOP condition. The START(S) and repeated START(Sr) conditions are functionally identical. SCL P • The slave address byte is the first byte received following the START condition from the master device. The first seven bits of the first byte make up the slave address. The eighth bit defines whether a read or write operation is to be performed. When the R/W bit is “1”, then a read operation is selected. A “0” selects a write operation. STOP condition Byte Format Every byte put on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. Rev. 1.00 7 • Each byte of eight bit length is followed by one acknowledge bit. This acknowledge bit is a low level placed on the bus by the receiver. The master generates an extra acknowledge related clock pulse. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can only change when the clock signal on the SCL line is low as shown in the accompanying diagram. START condition 2 Acknowledge Data Validity S 1 • The address bits are “1, 1, 0, 1, 0, A1, A0”. When an address byte is sent, the device compares the first seven bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line. 17 July 09, 2021 HT1635C/HT1635D Slave Address MSB LSB 1 1 0 1 0 A1 A0 R/W I2C Timing Diagram Write Operation – Command Byte Byte write operation requires a START condition, slave address with R/W bit, a command (1st), a register byte command (2nd) and a STOP condition for the command byte. Slave Address S 1 1 0 1 0 A1 A0 0 Command byte Register byte BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Write ACK ACK 1 st P ACK 2nd Write Operation – Write Display RAM Single Data Byte A display RAM data byte write operation requires a START condition, a slave address with a write control bit, a valid display data input /output command, Address byte, a Data byte and a STOP condition. Slave Address S 1 1 0 1 0 Command byte A1 A0 0 1 0 0 0 Write ACK 0 Address byte 0 0 0 X A6 A5 ACK 1st A4 A3 DATA byte A2 A1 A0 D0 D1 ACK 2nd D2 D3 D0 D1 D2 P D3 ACK 3rd Write Operation – Page Write Display Data Operation Following a START condition, the slave address together with the R/W bit is placed on the bus. The addressed device will then be provided with an address, which is the address pointer where the data is to be written. The data to be written then follows after which the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. After reaching the display memory location 0X57H the pointer will reset to 0X00H Slave Address S 1 1 0 1 0 Command byte A 1 A 0 1 0 0 0 0 0 0 Address byte 0 0 Write ACK D 0 D 1 D 2 n data Data byte D D D 3 0 1 D 2 D 3 A7 A6 A5 A4 A3 A2 A1 A0 ACK D 0 (n+1) data D 1 D 2 Data byte D D D 3 0 1 (n+2) data D 2 ACK D 3 D 0 (n+3) data D 1 D 2 Data byte D D D 3 0 1 (n+x) data ACK ACK ACK D 2 D 3 (n+x+1) data P ACK Note: The relationship between the LED Display Input/ Output Data transfer format and the RAM mapping data format is shown below. MSB SDA Data D0 LSB D1 D2 D3 Address n Rev. 1.00 D0 D1 D2 D3 Address n+1 18 July 09, 2021 HT1635C/HT1635D Read Operation – Read Display Data Operation In this mode, the master reads the device data after setting the slave address. Following the R/W bit, which is zero, and the acknowledge bit, then follows the display data address setting command code (1st). After this is the address pointer (An) which is written to the address pointer (2nd). Next comes the START condition and slave address, followed by an R/W bit which is high. The data which was addressed is then transmitted. The address pointer is only incremented on reception of an acknowledge clock. The device will place the data at address An+1 onto the bus. The master reads and acknowledges the new byte and the address pointer is incremented to “An+2”. • If the memory location exceeds the limit value of 0X57H, the memory pointer will return to 00H. • If only a read command is sent to the I2C interface, then dummy data is sent out. • This cycle for reading consecutive addresses will continue until the master sends a NACK and STOP condition. • Read display data format Slave Address S 1 1 0 1 0 Command byte A1 A0 1 0 Write Slave Address S 1 1 0 1 0 0 0 0 A0 1 D0 Read D1 D2 D3 D0 n data Address byte 0 0 0 ACK X A6 A5 A4 A3 D2 D3 D0 D1 (n+1) data D2 D3 D0 (n+2) data A0 Data byte D1 D2 D3 D0 D1 (n+3) data D2 D3 D0 (n+x) data ACK ACK A1 ACK Data byte D1 A2 ACK Data byte A1 0 ACK D1 D2 D3 P (n+x+1) data NACK ACK I2C Bus Command Summary Display Data Input Command This command sends data from the MCU to the device memory map. (MSB) (LSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit7 Bit0 Function Byte Display Data Input/ output command 1st 1 0 0 0 0 0 0 0 Address pointer 2nd X A6 A5 A4 A3 A2 A1 A0 Note R/W Def W Displays data start address of the memory map W 00H Note: • Power on status: the address is set to 00H. • If the programmed command is not defined the function will not be affected. System Mode Command This command controls the system oscillator on/off and display on/off. Function Byte (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 System mode setting command 1st 1 0 0 0 0 0 1 0 W System oscillator and display on/off setting 2nd X X X X X X P1 P0 W Note R/W Def 00H Note: Name SYS DIS and LED off SYS EN and LED off SYS EN and LED on P1 0 1 1 Bit P0 X 0 1 System Oscillator LED Display Off On On Off Off On • Power on status: Display off and disable the internal system oscillator. • If the programmed command is not defined, the function will not be affected. Rev. 1.00 19 July 09, 2021 HT1635C/HT1635D Blinking Frequency Command This command defines the blinking frequency of the display modes. Byte (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Blinking frequency command 1st 1 0 0 0 0 1 0 0 W Blinking frequency setting 2nd X X X X X X P1 P0 W Function Note R/W Def 00H Note: Bit P1 0 0 1 1 Blinking Frequency P0 0 1 0 1 Blinking off 2Hz 1Hz 0.5Hz • Power on status: Blinking function is switched off. • If the programmed command is not defined, the function will not be affected. COM Option Command Function (MSB) (LSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit7 Bit0 Byte Note R/W Def Driver output of COM setting command 1st 1 0 0 0 1 0 0 0 W COM pin option setting 2nd X X X X X X X P0 W 00H Note: Bit P0 0 1 COM pin open drain type selection N-MOS P-MOS • Power on status: The COM N-MOS open drain output is setup. • If the programmed command is not defined the function will not be affected. Cascade Set Mode Command This command will select master/slave mode and input clock source. (MSB) (LSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit7 Bit0 Function Byte Note R/W Cascade set mode command 1st 1 0 1 0 0 0 0 0 W Master/ slave select and input clock source setting 2nd X X X X X P2 P1 P0 W Def 04H Note: Name RC Master Mode0 RC Master Mode1 EXT CLK Master Mode0 EXT CLK Master Mode1 Slave Mode P2 Bit P1 P0 1 0 0 1 0 1 1 1 0 1 1 1 0 X X Master/Slave Input Clock Select Source Sync pin Note Status Always Only single chip Output Hi-Z Output high application On Chip RC Master mode Oscillator Output Output Master mode External OSC Slave mode External OSC OSC pin Status Input Always Only single chip Output high application Input Output Input Input • Power on status: The RC MASTER MODE0 is selected. • It is not recommended to change between MASTER and SLAVE mode after a system enable (SYS_EN=1) • If the programmed command is not defined the function will not be affected. Rev. 1.00 20 July 09, 2021 HT1635C/HT1635D PWM Duty Command This command controls the row pulse width. Function Byte (MSB) (LSB) Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit7 Bit0 Note R/W Def PWM setting command 1st 1 1 0 0 0 0 0 0 W Pulse width of ROW setting 2nd X X X X P3 P2 P1 P0 W 0FH Note: P3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 P2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit P1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 P0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 PWM duty 1/16 2/16 3/16 4/16 5/16 6/16 7/16 8/16 9/16 10/16 11/16 12/16 13/16 14/16 15/16 16/16 • Power on status: 16/16 PWM duty is selected. • If the programmed command is not defined the function will not be affected. Rev. 1.00 21 July 09, 2021 HT1635C/HT1635D Application Circuits LED Matrix Circuit ROW0 ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW37 ROW38 ROW39 ROW40 ROW41 ROW42 ROW43 COM0 COM1 COM6 COM7 LED Display -- 44 ROW × 8 COM Rev. 1.00 22 July 09, 2021 HT1635C/HT1635D Communication Bus Type Circuit The deivce are compatible with most microcontrollers and communicates using two serial interfaces, an I2C bus or a 4-wire serial bus. VDD VDD VDD MCU HT1635C 0.1uF ROW 0 ~ ROW 43 Port A CSB Port B WRB Port C RDB Port D DATA COM 0 ~ COM 7 OSC VSS VSS 4-Wire Serial Bus VDD VDD MCU VDD 4.7kΩ 4.7kΩ HT1635D 0.1uF ROW 0 ~ SCL Port B SDA Port C A0 Port D A1 ROW 43 COM 0 ~ Port A COM 7 OSC VSS VSS I2C Serial Bus Rev. 1.00 23 July 09, 2021 HT1635C/HT1635D Low Power LED Application – Direct Drive 44 ROW × 8 COM Example: N-MOS Open Drain Output R*44 ROW 0 ~ ~ 4 MCU ROW 0 ROW 43 ROW 43 HT1635C/HT1635D LED Matrix Communication bus COM 0 COM 0 ~ ~ COM 7 COM 7 Note: 1. Values of the R resistors are selected depending on the power consumption of the LEDs. 2. In PCB Layout that must connect all of the VDD pins to the power plane. 3. In PCB Layout that must connect all of the VSS pins to the GND plane. High Power LED Application – COM with Transistor Buffer 44 ROW × 8 COM Example – P-MOS Open Drain Output and 8 COM Option R*44 ROW 0 ~ 4 ~ MCU ROW 0 ROW 43 ROW 43 HT1635C/HT1635D LED Matrix Communication bus COM 0 ~ COM 0 R*8 ~ COM 7 COM 7 NPN*8 R*8 Note: 1. Values of the R resistors are selected depending on the power consumption of the LEDs. 2. In PCB Layout that must connect all of the VDD pins to the power plane. 3. In PCB Layout that must connect all of the VSS pins to the GND plane. Rev. 1.00 24 July 09, 2021 HT1635C/HT1635D Cascade Function Low Power LED Application − In the Case, the COM Pins Output Must be Set to N-MOS Open Drain Outputs • Example 1: Direct Driving for 4-wire Serial Bus LED Matrix LED Matrix ROW 0 ROW 43 COM 0 COM 7 ROW 0 ROW 43 LED Matrix COM 0 COM 7 ROW 0 R*44 R*44 ROW 0 ROW 43 COM 0 COM 7 HT1635C (Master) VDD 0.1uF VSS CSB WRB RDB ROW 43 COM 0 SYNC COM 7 HT1635C (Slave) 0.1uF OSC COM 7 VSS ROW 0 CSB WRB RDB DATA ROW 43 COM 0 COM 7 HT1635C (Slave) 0.1uF VSS SYNC COM 0 COM 7 VDD ROW 0 VDD OSC ROW 43 R*44 VDD ROW 0 VDD DATA COM 0 R*44 VDD VDD LED Matrix ROW 43 CSB WRB RDB DATA ROW 0 ROW 43 OSC VSS SYNC COM 0 COM 7 OSC SYNC HT1635C (Slave) VDD 0.1uF CSB WRB RDB DATA VDD VDD 0.1uF MCU VSS 4-Wire Serial bus Note: 1. Cascading can also be implemented using software. Users must set the Master in the master mode and the Slave in the slave mode using the commands. The CSB pin must be connected to the MCU individually for independent read and write. 2. Values of the R resistors are selected depending on the power consumption of the LEDs. 3. In PCB Layout that must connect all of the VDD pins to the power plane. 4. In PCB Layout that must connect all of the VSS pins to the GND plane. • Example 2: Direct Driving for I2C Serial Bus LED Matrix LED Matrix ROW 0 ROW 43 COM 0 COM 7 ROW 0 ROW 43 LED Matrix COM 0 COM 7 ROW 0 R*44 R*44 ROW 0 ROW 43 0.1uF VSS COM 0 COM 7 HT1635D (Master) VDD A0 A1 SCL SDA ROW 43 SYNC VSS COM 0 COM 7 A0 ROW 0 A1 SCL SDA ROW 43 VSS COM 0 COM 7 HT1635D (Slave) 0.1uF SYNC COM 0 COM 7 COM 0 COM 7 OSC SYNC R*44 VDD OSC ROW 43 VDD ROW 0 HT1635D (Slave) 0.1uF OSC COM 7 VDD ROW 0 VDD VDD VDD LED Matrix COM 0 R*44 VDD VDD ROW 43 A0 A1 SCL SDA ROW 0 ROW 43 HT1635D (Slave) VDD 0.1uF OSC SYNC VDD VSS A0 A1 SCL SDA VDD VDD 4.7KΩ 4.7KΩ VDD 0.1uF VSS MCU I2C Serial bus Note: 1.Cascading can also be implemented using software. Users must set the Master in the master mode and the Slave in the slave mode using the commands. The CSB pin must be connected to the MCU individually for independent read and write. 2. Values of the R resistors are selected depending on the power consumption of the LEDs. 3. In PCB Layout that must connect all of the VDD pins to the power plane. 4. In PCB Layout that must connect all of the VSS pins to the GND plane. Rev. 1.00 25 July 09, 2021 HT1635C/HT1635D High Power LED Application − In the Case, the COM Pins Output Must be Set to P-MOS Open Drain Outputs. • Example 1: COM with Transistor Buffer for 4-wire Serial Bus LED Matrix LED Matrix ROW 0 ROW 43 COM 0 COM 7 ROW 0 LED Matrix ROW 43 COM 0 NPN*8 COM 7 ROW 0 R*8 COM 0 0.1uF CSB VSS WRB RDB DATA COM 7 ROW 0 ROW 43 COM 0 COM 7 HT1635C (Slave) 0.1uF SYNC R*8 R*8 R*8 VDD VDD OSC NPN*8 R*44 R*8 HT1635C (Master) VSS CSB VDD ROW 0 ROW 43 COM 0 0.1uF OSC SYNC COM 7 HT1635C (Slave) VDD WRB RDB DATA COM 7 COM 0 R*8 VDD ROW 43 ROW 43 NPN*8 R*8 VDD ROW 0 R*44 R*8 ROW 0 COM 8 COM 0 NPN*8 R*43 R*44 VDD LED Matrix ROW 43 VSS CSB ROW 0 ROW 44 0.1uF WRB RDB DATA OSC SYNC COM 0 COM 7 OSC SYNC HT1635C (Slave) VDD VSS CSB WRB RDB DATA VDD VDD 0.1uF MCU VSS 4-Wire Serial bus Note: 1. Cascading can also be implemented using software. Users must set the Master in the master mode and the Slave in the slave mode using the commands. The CSB pin must be connected to the MCU individually for independent read and write. 2. Values of the R resistors are selected depending on the power consumption of the LEDs. 3. In PCB Layout that must connect all of the VDD pins to the power plane. 4. In PCB Layout that must connect all of the VSS pins to the GND plane. • Example 2: COM with Transistor Buffer for I2C Serial Bus LED Matrix LED Matrix ROW 0 COM 0 ROW 43 COM 7 ROW 0 LED Matrix COM 0 ROW 43 COM 7 ROW 0 VSS COM 0 COM 7 HT1635D (Master) A0 A1 SCL SDA ROW 0 ROW 43 OSC SYNC VSS COM 0 COM 7 HT1635D (Slave) VDD A0 A1 SCL SDA ROW 0 ROW 43 VSS SYNC COM 0 COM 7 HT1635D (Slave) 0.1uF OSC R*8 R*8 VDD VDD VDD VDD NPN*8 VDD 0.1uF COM 7 R*44 R*8 VDD ROW 43 COM 0 ROW 43 R*8 R*8 R*8 ROW 0 ROW 0 R*44 R*8 R*8 VDD COM 7 NPN*8 R*44 VDD LED Matrix COM 0 NPN*8 NPN*8 R*44 0.1uF ROW 43 A0 A1 SCL SDA ROW 0 ROW 43 OSC SYNC VDD VSS COM 0 COM 7 OSC SYNC HT1635D (Slave) VDD 0.1uF A0 A1 SCL SDA VDD VDD 4.7KΩ 4.7KΩ VDD 0.1uF MCU VSS I2C Serial bus Note: 1. Cascading can also be implemented using software. Users must set the Master in the master mode and the Slave in the slave mode using the commands. The CSB pin must be connected to the MCU individually for independent read and write. 2. Values of the R resistors are selected depending on the power consumption of the LEDs. 3. In PCB Layout that must connect all of the VDD pins to the power plane. 4. In PCB Layout that must connect all of the VSS pins to the GND plane. Rev. 1.00 26 July 09, 2021 HT1635C/HT1635D Cascade Control Flow Power On SYS DIS (Master,Slave) COM OPTION (Master,Slave) MASTER MODE (Master) SLAVE MODE (Slave) SYS ON (Master,Slave) Write RAM Data (Master,Slave) LED ON (Master,Slave) Update RAM Data (Master,Slave) Rev. 1.00 27 July 09, 2021 HT1635C/HT1635D Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/ Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 28 July 09, 2021 HT1635C/HT1635D 64-pin LQFP (7mm×7mm) Outline Dimensions                           Symbol Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.016 BSC — F 0.005 0.007 0.009 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Rev. 1.00 Dimensions in inch Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.40 BSC — F 0.13 0.18 0.23 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° — 7° 29 July 09, 2021 HT1635C/HT1635D Copyright© 2021 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com. Rev. 1.00 30 July 09, 2021
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HT1635D
    •  国内价格
    • 1+6.62040
    • 10+5.50800
    • 30+4.95720

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