HT24LC64

HT24LC64 CMOS 64K 2-Wire Serial EEPROM Features Block Diagram • Operating voltage: 1.8V~5.5V for temperature -40°C to +85°C    • Low power consumption –– Operation: 5mA max. –– Standby: 3μA max.                  ­  • Internal organization: 8192×8   • 2-wire serial interface • Write cycle time: 5ms max.                 
                 • Automatic erase-before-write operation • Partial page write allowed      • 32-byte Page Write Mode                
         • Write operation with built-in timer    • Hardware controlled write protection • 40-year data retention • 106 rewrite cycles per word Pin Assignment • 8-pin DIP/SOP/TSSOP package               General Description   The HT24LC64 is a 64K-bit 2-wire serial read/write non-volatile memory device using the CMOS floating gate process. Its 65536 bits of memory are organized into 8192 words and 8 bits per word. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. Up to eight HT24LC64 devices may be connected to the same two-wire bus. The HT24LC64 has high reliability endurance of 1M erase/write cycles and 40-year data retention.                                   Pin Description Pin Name I/O A0~A2 SDA SCL I Description Address inputs I/O Serial data I Serial clock input WP I Write protect VSS — Negative power supply, ground VCC — Positive power supply Rev. 1.50 1 January 16, 2014 HT24LC64 Absolute Maximum Ratings Supply Voltage .......................... VSS−0.3V to VSS+6.0V Storage Temperature............................−50°C to 125°C Input Voltage............................. VSS−0.3V to VCC+0.3V Operating Temperature..........................−40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ″Absolute Maximum Ratings″ may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=-40°C~+85°C Test Conditions VCC Conditions Min. Typ. Max. Unit VCC Operating Voltage — -40°C to +85°C 1.8 — 5.5 V ICC1 Operating Current 5V Read at 400kHz — — 2 mA ICC2 Operating Current 5V Write at 400kHz — — 5 mA VIL Input Low Voltage — — -0.45 — 0.3VCC V VIH Input High Voltage — — 0.7VCC — VCC+0.5 V VOL Output Low Voltage 2.4V IOL=2.1mA — — 0.4 V 1.8V IOL=0.7mA — — 0.2 V ILI Input Leakage Current (A0~A2, SCL, SDA) 5V VIN=0 or VCC — — 1 μA ILO Output Leakage Current 5V VOUT=0 or VCC — — 1 μA VIN=0 or VCC — — 3 μA SDA, SCL=VCC A0, A1, A2, WP=VSS — — 1 μA — — 2 μA — — 1 μA 5V ISTB Standby Current VIN=0 or VCC 1.8V SDA, SCL=VCC A0, A1, A2, WP=VSS CIN Input Capacitance (See Note) — f=1MHz, 25°C — — 6 pF COUT Output Capacitance (See Note) — f=1MHz, 25°C — — 8 pF Note: These parameters are periodically sampled but not 100% tested. Rev. 1.50 2 January 16, 2014 HT24LC64 A.C. Characteristics Symbol Ta=-40°C~+85°C Parameter Remark VCC=1.8V~5.0V VCC=2.5V~5.0V Min. Max. Min. Max. Unit fSK Clock Frequency — — 400 — 1000 kHz tHIGH Clock High Time — 600 — 400 — ns tLOW Clock Low Time — 1200 — 600 — ns tr SDA and SCL Rise Time Note — 300 — 300 ns tf SDA and SCL Fall Time Note — 300 — 300 ns tHD:STA START Condition Hold Time After this period the first clock pulse is generated 600 — 250 — ns tSU:STA START Condition Setup Time Only relevant for repeated START condition 600 — 250 — ns tHD:DAT Data Input Hold Time — 0 — 0 — ns tSU:DAT Data Input Setup Time — 150 — 100 — ns tSU:STO STOP Condition Setup Time — 600 — 250 — ns tAA Output Valid from Clock — — 900 — 600 ns tBUF Bus Free Time Time in which the bus must be free before a new transmission can start 1200 — 500 — ns tSP Input Filter Time Constant Noise suppression time (SDA and SCL Pins) — 50 — 50 ns tWR Write Cycle Time — 5 — 5 Endurance 25°C, Page Mode — 5.0V 1,000,000 ms Write Cycles Note: These parameters are periodically sampled but not 100% tested. For relative timing, refer to timing diagrams. Rev. 1.50 3 January 16, 2014 HT24LC64 Functional Description • Stop condition A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram). • Serial clock – SCL The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device. • Serial data – SDA The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices. • Acknowledge All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. • Address Inputs – A0, A1, A2 The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected. When the pins are hard wired, as many as eight 64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The code for the selected device is setup by connecting these inputs to either VSS or VCC. If any pin is left unconnected in a floating state will be internally read as having a low input, VSS, value.                      • Write protect – WP The HT24LC64 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to VSS or left floating. When the write protect pin is connected to VCC, the write protection feature is enabled and operates as shown in the following table. WP Pin Status Full Array (64K) VSS or floating Normal Read/Write Operations                                     Device Addressing The 64K EEPROM devices require an 8-bit device address word following a start condition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram showing the Device Address). This is common to all the EEPROM device. The 64K EEPROM uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hard wired input pins. Protect Array VCC           The 8th bit device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Memory Organization Internally organized with 8192 8-bit words, the 64K requires a 13-bit data word address for random word addressing. If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state. Device Operations • Clock and data transition Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition.                         • Start condition A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition Timing diagram). Rev. 1.50 4 January 16, 2014 HT24LC64 Write Operations • Write protect The HT24LC64 has a write-protect function and programming will then be inhibited when the WP pin is connected to VCC. Under this mode, the HT24LC64 is used as a serial ROM. • Byte write A write operation requires two data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle to the nonvolatile memory. All inputs are disabled during this write cycle and EEPROM will not respond until the write operation is completed (refer to Byte write timing). • Read operations The HT24LC64 supports three read operations, namely, current address read, random address read and sequential read. During read operation execution, the read/write select bit should be set to "1".               • Page write The 64K EEPROM is capable of a 32-byte page write. A page write is initiated in the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges the receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Page write timing).                                                           The data word address lower 5 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location.
         Acknowledge Polling Flow • Current address read The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address remains valid between operations as long as the chip power is maintained. The address will roll over during read from the last byte of the last memory page to the first byte of the first page. The address will roll over during write from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but generates a following stop condition (refer to Current read timing). When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. • Acknowledge polling To maximise bus throughput, one technique is to allow the master to poll for an acknowledge signal after the start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned. The master can send the next read/write command when the ACK signal has finally been received. Rev. 1.50
 5 January 16, 2014 HT24LC64 • Random read Arandom read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller should respond with a "no ACK" signal (high) followed by a stop condition (refer to Random read timing).                                                   • Sequential read Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is terminated when the microcontroller does not respond with a zero but generates a following stop condition.                                Byte Write Timing                                                                                 
                    Page Write Timing                                            Current Read Timing                                                                                       

                        Random Read Timing D a ta (n ) D a ta (n + 1 ) D a ta (n + 2 ) D a ta (n + x ) S to p R e a d D e v ic e A d d re s s S D A L in e N o A C K A C K A C K A C K A C K R /W Sequential Read Timing Rev. 1.50 6 January 16, 2014 HT24LC64 Timing Diagrams                                                                                            Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command. Rev. 1.50 7 January 16, 2014 HT24LC64 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.50 8 January 16, 2014 HT24LC64 8-pin DIP (300mil) Outline Dimensions               Symbol Min. Nom. Max. A 0.355 0.365 0.400 B 0.240 0.250 0.280 C 0.115 0.130 0.195 D 0.115 0.130 0.150 E 0.014 0.018 0.022 F 0.045 0.060 0.070 G — 0.100 BSC — H 0.300 0.310 0.325 I — — 0.430 Symbol Rev. 1.50 Dimensions in inch Dimensions in mm Min. Nom. Max. 10.16 A 9.02 9.27 B 6.10 6.35 7.11 C 2.92 3.30 4.95 D 2.92 3.30 3.81 E 0.36 0.46 0.56 F 1.14 1.52 1.78 G — 2.54 BSC — H 7.26 7.87 8.26 I — — 10.92 9 January 16, 2014 HT24LC64 8-pin SOP (150mil) Outline Dimensions              Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — 0.020 C 0.012 — C′ — 0.193 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.50   Dimensions in mm Min. Nom. Max. A —F 6.00 BSC — B — 3.90 BSC — C 0.31 — 0.51 C′ — 4.90 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 10 January 16, 2014 HT24LC64 8-pin TSSOP Outline Dimensions                         Symbol      Dimensions in inch Min. Nom. Max. A — — 0.047 A1 0.002 — 0.006 A2 0.031 0.039 0.041 B 0.007 — 0.012 C 0.004 — 0.006 D 0.114 0.118 0.122 E — 0.252 BSC — E1 0.169 0.173 0.177 e — 0.026 BSC — L 0.018 0.024 0.030 L1 — 0.039 BSC — y — 0.004 — θ 0° — 8° Symbol Rev. 1.50    Dimensions in mm Min. Nom. Max. A — — 1.20 A1 0.05 — 0.15 A2 0.80 1 1.05 B 0.19 — 0.30 C 0.09 — 0.16 D 2.90 3.00 3.10 E — 6.40 BSC — E1 4.30 4.40 4.50 e — 0.65 BSC — L 0.45 0.60 0.75 L1 — 1.0 BSC — y — 0.10 — θ 0° — 8° 11 January 16, 2014 HT24LC64 Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.50 12 January 16, 2014