HT32F53231/HT32F53241
HT32F53242/HT32F53252
Datasheet
32-Bit Arm® Cortex®-M0+ 5V CAN Microcontroller,
up to 128 KB Flash and up to 16 KB SRAM with 2 Msps ADC, CMP,
CAN, PDMA, DIV, USART, UART, SPI, I2C, GPTM, MCTM,
PWM, BFTM, EBI, LEDC, CRC, UID, RTC and WDT
Revision: V1.00
Date: March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Table of Contents
1 General Description................................................................................................. 6
2 Features.................................................................................................................... 7
3 Overview................................................................................................................. 16
Device Information................................................................................................................ 16
Block Diagram...................................................................................................................... 17
Memory Map......................................................................................................................... 19
Clock Structure..................................................................................................................... 22
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Table of Contents
Core........................................................................................................................................ 7
On-Chip Memory.................................................................................................................... 7
Flash Memory Controller – FMC............................................................................................. 7
Reset Control Unit – RSTCU.................................................................................................. 7
Clock Control Unit – CKCU..................................................................................................... 8
Power Management Control Unit – PWRCU.......................................................................... 8
External Interrupt / Event Controller – EXTI........................................................................... 8
Comparator – CMP (HT32F53242/HT32F53252 Only).......................................................... 9
Analog to Digital Converter – ADC......................................................................................... 9
I/O Ports – GPIO..................................................................................................................... 9
Motor Control Timer – MCTM .............................................................................................. 10
General-Purpose Timer – GPTM.......................................................................................... 10
Pulse-Width-Modulation Timer – PWM................................................................................. 10
Basic Function Timer – BFTM.............................................................................................. 11
Watchdog Timer – WDT........................................................................................................ 11
Real-Time Clock – RTC........................................................................................................ 11
Inter-integrated Circuit – I2C................................................................................................. 11
Serial Peripheral Interface – SPI.......................................................................................... 12
Universal Synchronous Asynchronous Receiver Transmitter – USART............................... 12
Universal Asynchronous Receiver Transmitter – UART....................................................... 13
Controller Area Network – CAN............................................................................................ 13
Cyclic Redundancy Check – CRC........................................................................................ 13
Peripheral Direct Memory Access – PDMA.......................................................................... 14
Hardware Divider – DIV........................................................................................................ 14
LED Controller – LEDC......................................................................................................... 14
External Bus Interface – EBI (HT32F53242/HT32F53252 Only).......................................... 15
Unique Identifier – UID......................................................................................................... 15
Debug Support...................................................................................................................... 15
Package and Operation Temperature................................................................................... 15
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
4 Pin Assignment...................................................................................................... 23
5 Electrical Characteristics...................................................................................... 38
6 Package Information............................................................................................. 51
SAW Type 32-pin QFN (4mm × 4mm × 0.75mm) Outline Dimensions................................. 52
SAW Type 46-pin QFN (6.5mm × 4.5mm × 0.75mm) Outline Dimensions........................... 53
48-pin LQFP (7mm × 7mm) Outline Dimensions.................................................................. 54
64-pin LQFP (7mm × 7mm) Outline Dimensions.................................................................. 55
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Table of Contents
Absolute Maximum Ratings.................................................................................................. 38
Recommended DC Operating Conditions............................................................................ 38
On-Chip LDO Voltage Regulator Characteristics.................................................................. 38
Power Consumption............................................................................................................. 39
Reset and Supply Monitor Characteristics............................................................................ 41
External Clock Characteristics.............................................................................................. 41
Internal Clock Characteristics............................................................................................... 43
System PLL Characteristics.................................................................................................. 43
Memory Characteristics........................................................................................................ 43
I/O Port Characteristics......................................................................................................... 44
ADC Characteristics............................................................................................................. 45
Internal Reference Voltage Characteristics.......................................................................... 46
Comparator Characteristics.................................................................................................. 46
GPTM / MCTM / PWM Characteristics................................................................................. 47
I2C Characteristics................................................................................................................ 47
SPI Characteristics............................................................................................................... 48
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
List of Tables
Table 1. Features and Peripheral List...................................................................................................... 16
Table 2. Register Map.............................................................................................................................. 20
Table 3. HT32F53242/HT32F53252 Pin Assignment ............................................................................. 30
Table 4. HT32F53231/HT32F53241 Pin Assignment.............................................................................. 32
Table 6. HT32F53231/HT32F53241 Pin Description............................................................................... 36
Table 7. Absolute Maximum Ratings........................................................................................................ 38
Table 8. Recommended DC Operating Conditions.................................................................................. 38
Table 9. LDO Characteristics................................................................................................................... 38
Table 10. HT32F53242/HT32F53252 Power Consumption Characteristics............................................ 39
Table 11. HT32F53231/HT32F53241 Power Consumption Characteristics............................................ 40
Table 12. VDD Power Reset Characteristics............................................................................................. 41
Table 13. LVD / BOD Characteristics....................................................................................................... 41
Table 14. High Speed External Clock (HSE) Characteristics................................................................... 41
Table 15. Low Speed External Clock (LSE) Characteristics.................................................................... 42
Table 16. High Speed Internal Clock (HSI) Characteristics..................................................................... 43
Table 17. Low Speed Internal Clock (LSI) Characteristics....................................................................... 43
Table 18. System PLL Characteristics..................................................................................................... 43
Table 19. Flash Memory Characteristics.................................................................................................. 43
Table 20. I/O Port Characteristics............................................................................................................ 44
Table 21. ADC Characteristics................................................................................................................. 45
Table 22. Internal Reference Voltage Characteristics.............................................................................. 46
Table 23. Comparator Characteristics..................................................................................................... 46
Table 24. GPTM / MCTM / PWM Characteristics.................................................................................... 47
Table 25. I2C Characteristics.................................................................................................................... 47
Table 26. SPI Characteristics................................................................................................................... 48
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List of Tables
Table 5. HT32F53242/HT32F53252 Pin Description............................................................................... 33
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
List of Figures
Figure 1. HT32F53242/HT32F53252 Block Diagram.............................................................................. 17
Figure 2. HT32F53231/HT32F53241 Block Diagram.............................................................................. 18
Figure 3. Memory Map............................................................................................................................. 19
Figure 4. Clock Structure......................................................................................................................... 22
Figure 6. HT32F53242/HT32F53252 46-pin QFN Pin Assignment......................................................... 24
Figure 7. HT32F53242/HT32F53252 48-pin LQFP Pin Assignment....................................................... 25
Figure 8. HT32F53242/HT32F53252 64-pin LQFP Pin Assignment....................................................... 26
Figure 9. HT32F53231/HT32F53241 32-pin QFN Pin Assignment......................................................... 27
Figure 10. HT32F53231/HT32F53241 46-pin QFN Pin Assignment....................................................... 28
Figure 11. HT32F53231/HT32F53241 48-pin LQFP Pin Assignment...................................................... 29
Figure 12. ADC Sampling Network Model............................................................................................... 45
Figure 13. I2C Timing Diagram................................................................................................................. 48
Figure 14. SPI Timing Diagram – SPI Master Mode................................................................................ 49
Figure 15. SPI Timing Diagram – SPI Slave Mode with CPHA = 1.......................................................... 50
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List of Figures
Figure 5. HT32F53242/HT32F53252 32-pin QFN Pin Assignment......................................................... 23
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
1
General Description
The Holtek HT32F53231/HT32F53241/HT32F53242/HT32F53252 devices are high performance,
low power consumption 32-bit microcontrollers based around an Arm ® Cortex®-M0+ processor
core. The Cortex®-M0+ is a next-generation processor core which is tightly coupled with Nested
Vectored Interrupt Controller (NVIC), SysTick timer and including advanced debug support.
The above features ensure that the devices are suitable for use in a wide range of applications,
especially in areas such as consumer products, handheld equipment, automotive, industrial
automation control, battery management system, electronic equipment and so on.
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1 General Description
The devices operate at a frequency of up to 60 MHz with a Flash accelerator to obtain maximum
efficiency. It provides up to 128 KB of embedded Flash memory for code/data storage and up to 16
KB of embedded SRAM memory for system operation and application program usage. A variety
of peripherals, such as Hardware Divider DIV, PDMA, ADC, I2C, UART, USART, SPI, MCTM,
CMP, GPTM, PWM, BFTM, LEDC, EBI, CAN, CRC-16/32, 96-bit Unique ID, RTC, WDT, SWDP (Serial Wire Debug Port), etc., are also implemented in the devices. Several power saving modes
provide the flexibility for maximum optimization between wakeup latency and power consumption,
an especially important consideration in low power applications.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
2
Features
Core
32-bit Arm® Cortex®-M0+ processor core
▆ Up to 60 MHz operating frequency
▆ Single-cycle multiplication
▆ Integrated Nested Vectored Interrupt Controller (NVIC)
▆ 24-bit SysTick timer
▆
On-Chip Memory
Up to 128 KB on-chip Flash memory for instruction/data and option byte storage
Up to 16 KB on-chip SRAM
▆ Supports multiple boot modes
▆
▆
The Arm® Cortex®-M0+ processor access and debug access share the single external interface to
external AHB peripherals. The processor access takes priority over debug access. The maximum
address range of the Cortex®-M0+ is 4 GB since it has a 32-bit bus address width. Additionally,
a pre-defined memory map is provided by the Cortex®-M0+ processor to reduce the software
complexity of repeated implementation by different device vendors. However, some regions are
used by the Arm® Cortex®-M0+ system peripherals. Refer to the Arm® Cortex®-M0+ Technical
Reference Manual for more information. Figure 3 in the Overview chapter shows the memory map
of the HT32F53231/HT32F53241 and HT32F53242/HT32F53252 series of devices, including code,
SRAM, peripheral and other pre-defined regions.
Flash Memory Controller – FMC
Flash accelerator to obtain maximum efficiency
32-bit word programming with In System Programming (ISP) and In Application Programming
(IAP)
▆ Flash protection capability to prevent illegal access
▆
▆
The Flash Memory Controller, FMC, provides all the necessary functions and pre-fetch buffer for
the embedded on-chip Flash Memory. Since the access speed of the Flash Memory is slower than
the CPU, a wide access interface with a pre-fetch buffer is provided for the Flash Memory in order
to reduce the CPU waiting time which will cause CPU instruction execution delays. Flash Memory
word programming/page erase functions are also provided.
Reset Control Unit – RSTCU
▆
Rev. 1.00
Supply supervisor
● Power On Reset / Power Down Reset – POR / PDR
● Brown-out Detector – BOD
● Programmable Low Voltage Detector – LVD
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2 Features
The Cortex®-M0+ processor is a very low gate count, highly energy efficient processor that is
intended for microcontroller and deeply embedded applications that require an area optimized,
low-power processor. The processor is based on the ARMv6-M architecture and supports Thumb®
instruction sets, single-cycle I/O ports, hardware multiplier and low latency interrupt respond time.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
The Reset Control Unit, RSTCU, has three kinds of reset, a power on reset, a system reset and an
APB unit reset. The power on reset, known as a cold reset, resets the full system during power up.
A system reset resets the processor core and peripheral IP components with the exception of the
SW-DP controller. The resets can be triggered by external signals, internal events and the reset
generators.
Clock Control Unit – CKCU
▆
The Clock Control Unit, CKCU, provides a range of oscillator and clock functions. These include
a High Speed Internal RC oscillator (HSI), a High Speed External crystal oscillator (HSE), a Low
Speed Internal RC oscillator (LSI), a Low Speed External crystal oscillator (LSE), a Phase Lock
Loop (PLL), an HSE clock monitor, clock pre-scalers, clock multiplexers, APB clock divider
and gating circuitry. The AHB, APB and Cortex®-M0+ clocks are derived from the system clock
(CK_SYS) which can come from HSI, HSE, LSI, LSE or system PLL. The Watchdog Timer and
Real-Time Clock (RTC) use either the LSI or LSE as their clock source.
Power Management Control Unit – PWRCU
Flexible power supply: VDD power supply (2.5 V ~ 5.5 V), VDDIO for I/Os (1.8 V ~ 5.5 V)
Integrated 1.5 V LDO regulator for MCU core, peripherals and memories power supply
▆ Two power domains: VDD and VCORE.
▆ Three power saving modes: Sleep, Deep-Sleep1, Deep-Sleep2
▆
▆
Power consumption can be regarded as one of the most important issues for many embedded system
applications. Accordingly the Power Control Unit, PWRCU, in the device provides many types of
power saving modes such as Sleep, Deep-Sleep1 and Deep-Sleep2 modes. These operating modes
reduce the power consumption and allow the application to achieve the best trade-off between the
conflicting demands of CPU operating time, speed and power consumption.
External Interrupt / Event Controller – EXTI
Up to 16 EXTI lines with configurable trigger source and type
All GPIO pins can be selected as EXTI trigger source
▆ Source trigger type includes high level, low level, negative edge, positive edge or both edges
▆ Individual interrupt enable, wakeup enable and status bits for each EXTI line
▆ Software interrupt trigger mode for each EXTI line
▆ Integrated deglitch filter for short pulse blocking
▆
▆
The External Interrupt/Event Controller, EXTI, comprises 16 edge detectors which can generate
a wake-up event or interrupt requests independently. Each EXTI line can also be masked
independently.
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2 Features
External 4 to 16 MHz crystal oscillator
External 32.768 kHz crystal oscillator
▆ Internal 8 MHz RC oscillator trimmed to ±1 % accuracy at 5.0 V operating voltage and 25 °C
operating temperature
▆ Internal 32 kHz RC oscillator
▆ Integrated system clock PLL
▆ Independent clock divider and gating bits for peripheral clock sources
▆
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Comparator – CMP (HT32F53242/HT32F53252 Only)
Rail-to-rail comparators
Configurable negative inputs used for flexible voltage selection
● External CN pin
● Internal 8-bit CVR output
● Internal voltage reference (VREF)
▆ Programmable hysteresis
▆ Programmable respond speed and consumption
▆ Comparator output can be routed to I/O pin, to multiple timers or ADC trigger inputs
▆ 8-bit CVR can be configurable to dedicated I/O for voltage reference
▆ Interrupt generation capability with wakeup from Sleep, Deep-Sleep1 or Deep-Sleep2 mode
through the EXTI controller
▆
▆
Analog to Digital Converter – ADC
12-bit SAR ADC engine
Up to 2 Msps conversion rate
▆ Up to 12 external analog input channels
▆
▆
A 12-bit multi-channel Analog to Digital Converter is integrated in the devices. There are
multiplexed channels, which include 12 external channels on which the external analog signal can
be supplied and 2 internal channels. If the input voltage is required to remain within a specific
threshold window, the Analog Watchdog function will monitor and detect the signals. An interrupt
will then be generated to inform the device that the input voltage is higher or lower than the preset
thresholds. There are three conversion modes to convert an analog signal to digital data. The A/D
conversion can be operated in one shot, continuous and discontinuous conversion mode.
The internal voltage reference (VREF) which can provide a stable reference voltage for the A/D
Converter and Comparators is internally connected to the ADC_IN12 input channel. The precise
voltage of the VREF is individually measured for each part by Holtek during production test.
I/O Ports – GPIO
Up to 54 GPIOs
Port A, B, C, D are mapped to 16-line EXTI interrupts
▆ Almost all I/O pins have configurable output driving current
▆
▆
There are up to 54 General Purpose I/O pins, GPIO, named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15
and PD0 ~ PD5 for the implementation of logic input/output functions. Each of the GPIO ports
has a series of related control and configuration registers to maximize flexibility and to meet the
requirements of a wide range of applications.
The GPIO ports are pin-shared with other alternative functions to obtain maximum functional
flexibility on the package pins. The GPIO pins can be used as alternative functional pins by
configuring the corresponding registers regardless of the input or output pins. The external interrupts
on the GPIO pins of the device have related control and configuration registers in the External
Interrupt Control Unit, EXTI.
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2 Features
The two general purpose comparators, CMP, are implemented within the device. They can be
configured either as standalone comparators or combined with the different kinds of peripheral IP.
Each comparator is capable of asserting interrupts to the NVIC or waking up the CPU from the
Sleep, Deep-Sleep1 or Deep-Sleep2 mode through the EXTI wakeup event management unit.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Motor Control Timer – MCTM
16-bit up, down, up/down auto-reload counter
Up to 4 independent channels
▆ 16-bit programmable prescaler that allows division of the prescaler clock source by any factor
between 1 and 65536 to generate the counter clock frequency
▆ Input Capture function
▆ Compare Match Output
▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
▆ Single Pulse Mode Output
▆ Complementary Outputs with programmable dead-time insertion
▆ Supports 3-phase motor control and hall sensor interface
▆ Break input signals to assert the timer output signals in reset state or in a known state
▆
▆
General-Purpose Timer – GPTM
16-bit up, down, up/down auto-reload counter
Up to 4 independent channels
▆ 16-bit programmable prescaler that allows division of the prescaler clock source by any factor
between 1 and 65536 to generate the counter clock frequency
▆ Input Capture function
▆ Compare Match Output
▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
▆ Single Pulse Mode Output
▆ Encoder interface controller with two inputs using quadrature decoder
▆
▆
The General-Purpose Timer Module, GPTM, consists of one 16-bit up/down-counter, four 16-bit
Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/
status registers. They can be used for a variety of purposes including general time measurement,
input signal pulse width measurement, output waveform generation such as single pulse generation
or PWM output generation. The GPTM supports an Encoder Interface using a decoder with two
inputs.
Pulse-Width-Modulation Timer – PWM
16-bit up, down, up/down auto-reload counter
Up to 4 independent channels for each timer
▆ 16-bit programmable prescaler that allows division of the prescaler clock source by any factor
between 1 and 65536 to generate the counter clock frequency
▆ Compare Match Output
▆ PWM waveform generation with Edge-aligned and Center-aligned Counting Modes
▆ Single Pulse Mode Output
▆
▆
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2 Features
The Motor Control Timer Module, MCTM, consists of a single 16-bit up/down counter, four 16-bit
Capture/Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR), one 8-bit repetition
counter and several control/status registers. It can be used for a variety of purposes which include
input signal pulse width measurement, output waveform generation for signals such as compare
match outputs, PWM outputs or complementary PWM outputs with dead-time insertion. The
MCTM is capable of offering full functional support for motor control, hall sensor interfacing and
break input.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
The Pulse-Width-Modulation Timer, PWM, consists of one 16-bit up/down-counter, four 16-bit
Compare Registers (CRs), one 16-bit Counter-Reload Register (CRR) and several control/status
registers. It can be used for a variety of purposes including general timer and output waveform
generation such as single pulse generation or PWM output.
Basic Function Timer – BFTM
32-bit compare match up-counter – no I/O control
One shot mode – counter stops counting when compare match occurs
▆ Repetitive mode – counter restarts when compare match occurs
▆
The Basic Function Timer Module, BFTM, is a simple 32-bit up-counting counter designed to
measure time intervals and generate one shots or generate repetitive interrupts. The BFTM can
operate in two functional modes, repetitive and one shot modes. In the repetitive mode, the counter
will restart at each compare match event. The BFTM also supports a one shot mode which will force
the counter to stop counting when a compare match event occurs.
Watchdog Timer – WDT
12-bit down-counter with 3-bit prescaler
Provides reset to the system
▆ Programmable watchdog timer window function
▆ Register write protection function
▆
▆
The Watchdog Timer is a hardware timing circuit that can be used to detect a system lock-up due to
software trapped in a deadlock. It includes a 12-bit down-counter, a prescaler, a WDT delta value
register, WDT operation control circuitry and a WDT protection mechanism. If the software does
not reload the counter value before a Watchdog Timer underflow occurs, a reset will be generated
when the counter underflows. In addition, a reset is also generated if the software reloads the counter
before it reaches a delta value. It means that the counter reload must occur when the Watchdog timer
value has a value within a limited window using a specific method. The Watchdog Timer counter
can be stopped when the processor is in the debug mode. The register write protection function can
be enabled to prevent an unexpected change in the Watchdog Timer configuration.
Real-Time Clock – RTC
24-bit up-counter with a programmable prescaler
Alarm function
▆ Interrupt and Wake-up event
▆
▆
The Real-Time Clock, RTC, circuitry includes the APB interface, a 24-bit up-counter, a control
register, a prescaler, a compare register and a status register. The RTC circuits are located in the
VCORE power domain. When the device enters the power-saving mode, the RTC counter is used as a
wakeup timer to let the system resume from the power saving mode.
Inter-integrated Circuit – I2C
Supports both master and slave modes with a frequency of up to 1 MHz
Provides an arbitration function and clock synchronization
▆ Supports 7-bit and 10-bit addressing modes and general call addressing
▆ Supports slave multi-addressing mode using address mask function
▆
▆
The I2C module is an internal circuit allowing communication with an external I2C interface which
is an industry standard two-wire serial interface used for connection to external hardware. These
two serial lines are known as a serial data line, SDA, and a serial clock line, SCL. The I2C module
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2 Features
▆
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
provides three data transfer rates: 100 kHz in the Standard mode, 400 kHz in the Fast mode and 1
MHz in the Fast plus mode. The SCL period generation register is used to setup different kinds of
duty cycle implementations for the SCL pulse.
The SDA line which is connected directly to the I2C bus is a bidirectional data line between the
master and slave devices and is used for data transmission and reception. The I2C also has an
arbitration detect function and clock synchronization function to prevent the situations where more
than one master attempts to transmit data to the I2C bus at the same time.
Supports both master and slave modes
Frequency of up to (fPCLK/2) MHz for the master mode and (fPCLK/3) MHz for the slave mode
▆ FIFO Depth: 8 levels
▆ Multi-master and multi-slave operation
▆
▆
The Serial Peripheral Interface, SPI, provides an SPI protocol data transmit and receive function in
both master and slave modes. The SPI interface uses 4 pins, among which are serial data input and
output lines MISO and MOSI, the clock line, SCK, and the slave select line, SEL. One SPI device
acts as a master device which controls the data flow using the SEL and SCK signals to indicate the
start of data communication and the data sampling rate. To receive a data byte, the streamlined data
bits are latched on a specific clock edge and stored in the data register or in the RX FIFO. Data
transmission is carried out in a similar way but in a reverse sequence. The mode fault detection
provides a capability for multi-master applications.
Universal Synchronous Asynchronous Receiver Transmitter – USART
Supports both asynchronous and clocked synchronous serial communication modes
Programmable baud rate clock frequency up to (fPCLK/16) MHz for asynchronous mode and
(fPCLK/8) MHz for synchronous mode
▆ Full duplex communication
▆ Supports LIN (Local Interconnect Network) mode
▆ Supports single-wire mode
▆ Fully programmable serial communication characteristics including:
● Word length: 7, 8 or 9-bit character
● Parity: Even, odd or no-parity bit generation and detection
● Stop bit: 1 or 2 stop bits generation
● Bit order: LSB-first or MSB-first transfer
▆ Error detection: Parity, overrun and frame error
▆ Auto hardware flow control mode – RTS, CTS
▆ IrDA SIR encoder and decoder
▆ RS485 mode with output enable control
▆ FIFO Depth: 8-level for both receiver and transmitter
▆
▆
The Universal Synchronous Asynchronous Receiver Transceiver, USART, provides a flexible full
duplex data exchange using synchronous or asynchronous data transfer. The USART is used to
translate data between parallel and serial interfaces, and is commonly used for RS232 standard
communication. The USART peripheral function supports four types of interrupt including Line
Status Interrupt, Transmitter FIFO Empty Interrupt, Receiver Threshold Level Reaching Interrupt
and Time Out Interrupt. The USART module includes an 8-level transmitter FIFO, (TX_FIFO) and
an 8-level receiver FIFO (RX_FIFO). The software can detect a USART error status by reading
USART Status & Interrupt Flag Register, USRSIFR. The status includes the type and the condition
of transfer operations as well as several error conditions resulting from Parity, Overrun, Framing and
Break events.
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2 Features
Serial Peripheral Interface – SPI
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Universal Asynchronous Receiver Transmitter – UART
Asynchronous serial communication operating baud-rate clock frequency up to (fPCLK/16) MHz
Full duplex communication
▆ Supports LIN (Local Interconnect Network) mode
▆ Supports single-wire mode
▆ Fully programmable serial communication characteristics including:
● Word length: 7, 8 or 9-bit character
● Parity: Even, odd or no-parity bit generation and detection
● Stop bit: 1 or 2 stop bits generation
● Bit order: LSB-first or MSB-first transfer
▆ Error detection: Parity, overrun and frame error
▆
▆
Controller Area Network – CAN
Conform to ISO11898-1, 2003
32 Message Objects
▆ Each Message Object has its own identifier mask
▆ Programmable FIFO mode (concatenation of Message Objects)
▆ Maskable interrupt
▆ Programmable loop-back mode for self-test operation
▆
▆
The CAN_Core performs communication according to the CAN protocol version 2.0 A, B and ISO
11898-1. The internal State Machine controls the data transfer between the RX/TX Shift Register of
the CAN_Core and the Message RAM as well as the generation of interrupts as programmed in the
Control and Configuration Registers.
Cyclic Redundancy Check – CRC
Supports CRC16 polynomial: 0x8005,
X16 + X15 + X2 + 1
▆ Supports CCITT CRC16 polynomial: 0x1021,
X16 + X12 + X5 + 1
▆ Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7,
X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1
▆ Supports 1’s complement, byte reverse & bit reverse operation on data and checksum
▆ Supports byte, half-word & word data size
▆ Programmable CRC initial seed value
▆ CRC computation executed in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32bit data
▆ Supports PDMA to complete a CRC computation of a block of memory
▆
The CRC calculation unit is an error detection technique test algorithm and is used to verify data
transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as
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2 Features
The Universal Asynchronous Receiver Transceiver, UART, provides a flexible full duplex data
exchange using asynchronous transfer. The UART is used to translate data between parallel and
serial interfaces, and is commonly used for RS232 standard communication. The UART peripheral
function supports Line Status Interrupt. The software can detect a UART error status by reading the
UART Status & Interrupt Flag Register, URSIFR. The status includes the type and the condition of
transfer operations as well as several error conditions resulting from Parity, Overrun, Framing and
Break events.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
its input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is suffixed by
a CRC code and used as a checksum when being sent or stored. Therefore, the received or restored
data stream is calculated by the same generator polynomial as described above. If the new CRC
code result does not match the one calculated earlier, that means the data stream contains a data
error.
Peripheral Direct Memory Access – PDMA
6 channels with trigger source grouping
8-bit, 16-bit and 32-bit width data transfer
▆ Supports linear address, circular address and fixed address modes
▆ 4-level programmable channel priority
▆ Auto reload mode
▆ Supports trigger source:
ADC, SPI, UART, USART, I2C, MCTM, GPTM, PWM and software request
2 Features
▆
▆
The Peripheral Direct Memory Access circuitry, PDMA, moves data between the peripherals and
the system memory on the AHB bus. Each PDMA channel has a source address, destination address,
block length and transfer count. The PDMA can exclude the CPU intervention and avoid interrupt
service routine execution. It improves system performance as the software does not need to connect
each data movement operation.
Hardware Divider – DIV
Signed/unsigned 32-bit divider
Calculate in 8 clock cycles, load in 1 clock cycle
▆ Division by zero error Flag
▆
▆
The divider is the truncated division and requires a software triggered start signal by controlling the
“START” bit in the control register. The divider calculation complete flag will be set to 1 after 8
clock cycles, however, if the divisor register data is zero during the calculation, the division by zero
error flag will be set to 1.
LED Controller – LEDC
Supports 8-segment digital displays up to a maximum of N
● For the HT32F53231/HT32F53241, N = 8
● For the HT32F53242/HT32F53252, N = 12
▆ Supports 8-segment digital displays with common anode or common cathode
▆ Support frame interrupt
▆ Three clock sources: LSI, LSE and PCLK
▆ The LED light on/off times can be controlled using the dead time setting
▆
The LED controller is used to drive 8-segment digital displays. The HT32F53231/HT32F53241
can driver 8-segment digital displays up to 8. The HT32F53242/HT32F53252 can driver 8-segment
digital displays up to 12. Users can flexibly configure the pin position and number of the COMs
according to the digital displays in the application. In a complete frame period, the enabled COMs
will be scanned from the lower to the higher. Taking an example of where four 8-segment LEDs
are used and where COM0, COM5, COM6 and COM7 are enabled. Here COM0, COM5, COM6
and the COM7 will be scanned successively in this sequence within a complete frame period. The
scanning time of each COM port is equal to 1/4 frame, which is subdivided into the dead time duty
and the COM duty. Users can adjust the dead time duty to change the LED brightness.
Rev. 1.00
14 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
External Bus Interface – EBI (HT32F53242/HT32F53252 Only)
Programmable interface for various memory types
Translate the AHB transactions into the appropriate external device protocol
▆ Individual chip select signal for per memory bank
▆ Programmable timing to support a wide range of devices
▆ Automatic translation when AHB transaction width and external memory interface width is
different
▆ Write buffer to decrease the stalling of the AHB write burst transaction
▆ Multiplexed and non-multiplexed address and data line configurations
● Up to 21 address lines
● Up to 16-bit data bus width
▆
▆
Unique Identifier – UID
▆
▆
Total 96-bit UID is unique and not duplicate with other HT32 MCU devices
It is unchangeable and determined by MCU manufacturer
Debug Support
Serial Wire Debug Port – SW-DP
4 comparators for hardware breakpoint or code / literal patch
▆ 2 comparators for hardware watch points
▆
▆
Package and Operation Temperature
32/46-pin QFN and 48-pin LQFP packages for the HT32F53231/HT32F53241
32/46-pin QFN and 48/64-pin LQFP packages for the HT32F53242/HT32F53252
▆ Operation temperature range: -40 °C to 105 °C
▆
▆
Rev. 1.00
15 of 56
March 06, 2024
2 Features
The external bus interface is able to access external parallel interface devices such as SRAM, Flash
and LCD modules. The interface is memory mapped into the CPU internal address map. The data
and address lines are multiplexed in order to reduce the number of pins required to connect to the
external devices. The read/write timing of the bus can be adjusted to meet the timing specification of
the external devices. Note the interface only supports asynchronous 8-bit or 16-bit bus interface.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
3
Overview
Device Information
Table 1. Features and Peripheral List
Main Flash (KB)
HT32F53231
HT32F53241
32
63
Option Bytes Flash (KB)
SRAM (KB)
Timers
1
GPTM
1
2
1
RTC
1
CAN
1
SPI
2
Communication UART
1
2
2
PDMA
6 Channels
—
1
8 × 8-segment
12 × 8-segment
—
2
Hardware Divider
1
CRC-16/32
1
EXTI
16
1
12-bit 2 Msps ADC
Number of channels
GPIO
12 external channels
40 (Max.)
54 (Max.)
CPU frequency
Up to 60 MHz
Operating voltage
2.5 V ~ 5.5 V
Operating temperature
Package
Rev. 1.00
16
2
I2C
CMP
8
2
WDT
LED Controller
127
1
BFTM
EBI
64
8
MCTM
USART
HT32F53252
1
4
PWM
HT32F53242
-40 °C ~ 105 °C
32/46-pin QFN and 48-pin LQFP
16 of 56
32/46-pin QFN and 48/64-pin LQFP
March 06, 2024
3 Overview
Peripherals
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Block Diagram
PA ~ PC[15:0], PD[5:0]
SWCLK SWDIO
BOOT
AF
AF
Powered by VCORE
VDD
HSE
XTALIN
XTALOUT
VSS
FMC
Control
Registers
Bus Matrix
Interrupt request
SRAM
Controller
Divider
SRAM
DMOS
VCORE
Clock and reset control
AHB Peripherals
CKCU&RSTCU
Control Registers
CLDO
LDO
CAP.
VCORE
BOD
LVD
External Bus
Interafce (EBI)
6 Channels
AF
DMA request
AHB to APB
Bridge
AD0~AD15
A0~A20
CS0~CS3
OE, WR, ALE
VCORE
POR
fMax: 60 MHz
HSI
AF
TX, RX
PLL
AF
TX, RX
RTS/TXE
CTS/SCK
8 MHz
AF
AF
Power control
SDA
SCL
AF
CH0~CH3
MOSI, MISO
SCK, SEL
AF
AF
CH0~CH3
PWRCU
AF
LSI
Analog~1
CMP0
CMP
32 kHz
LSE
VDDA
VSSA
Powered by VDDA
Powered by VDD
32,768 Hz
Powered by VCORE
RTCOUT
AF
RTC
12-bit
SAR ADC
AF
ADC_IN11
CN0, CP0
COUT0
CN1, CP1
COUT1
APB
...
AF
ADC_IN0
CH0~CH2
CH0N~CH2N
CH3, BRK
AF
LED_SEG0~7,
LED_COM0~11
AF
CAN_TX,
CAN_RX
WAKEUP
nRST
VDD
VSS
AF
X32KIN
X32KOUT
Power supply:
Bus:
Control signal:
Alternate function:
AF
Figure 1. HT32F53242/HT32F53252 Block Diagram
Rev. 1.00
17 of 56
March 06, 2024
3 Overview
PDMA
PDMA
POR
/PDR
4 ~ 16 MHz
Control
Registers
System
NVIC
IO Port
Cortex®-M0+
Processor
Flash
Memory
AF
Flash Memory
Interface
SW-DP
Powered by VDD
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
PA ~ PC[15:0]
SWCLK SWDIO
BOOT
AF
AF
Powered by VCORE
POR
/PDR
VDD
HSE
XTALIN
XTALOUT
VSS
4 ~ 16 MHz
FMC
Control
Registers
Bus Matrix
Interrupt request
SRAM
Controller
Divider
SRAM
PDMA
CLDO
LDO
VCORE
Clock and reset control
AHB Peripherals
DMOS
VCORE
CKCU&RSTCU
Control Registers
CAP.
BOD
LVD
6 Channels
DMA request
AHB to APB
Bridge
VCORE
POR
fMax: 60 MHz
HSI
AF
TX, RX
PLL
AF
TX, RX
RTS/TXE
CTS/SCK
8 MHz
AF
AF
Power control
AF
APB
AF
CAN_TX,
CAN_RX
SDA
SCL
AF
CH0~CH3
MOSI, MISO
SCK, SEL
AF
Powered by VDD
PWRCU
VSSA
Powered by VDDA
nRST
LSE
VDD
Power supply:
Bus:
Control signal:
Alternate function:
32,768 Hz
Powered by VCORE
WAKEUP
LSI
32 kHz
VDDA
RTCOUT
AF
ADC_IN11
RTC
12-bit
SAR ADC
AF
...
AF
ADC_IN0
CH0~CH3
AF
LED_SEG0~7
~LED_COM0~7
CH0~CH2
CH0N~CH2N
CH3, BRK
VSS
AF
X32KIN
X32KOUT
AF
Figure 2. HT32F53231/HT32F53241 Block Diagram
Rev. 1.00
18 of 56
March 06, 2024
3 Overview
PDMA
Control
Registers
System
NVIC
IO Port
Cortex®-M0+
Processor
Flash
Memory
AF
Flash Memory
Interface
SW-DP
Powered by VDD
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Memory Map
0x400F_FFFF
0x400C_C000
0x400C_A000
0xFFFF_FFFF
Reserved
0xE000_0000
0x7000_0000
Private peripheral bus
Reserved
EBI Selection Bank
64 MB × 4
0x6000_0000
Reserved
0x4010_0000
Peripheral
0x4008_0000
0x4000_0000
AHB peripherals
APB peripherals
512 KB
512 KB
Reserved
SRAM
0x2000_4000
Up to 16 KB on-chip SRAM
Up to
16 KB
0x2000_0000
0x1FF0_0400
0x1FF0_0000
0x1F00_0800
0x1F00_0000
Code
0x0002_0000
Reserved
Option byte alias
1 KB
Reserved
Boot loader
2 KB
Reserved
Up to 128 KB on-chip Flash
Up to
128 KB
DIV
0x400B_8000
Reserved
0x400B_0000
GPIO A ～ D(Note)
0x4009_A000
Reserved
0x4009_8000
EBI(Note)
0x4009_2000
Reserved
0x4009_0000
PDMA
0x4008_C000
Reserved
0x4008_A000
CRC
0x4008_8000
CKCU & RSTCU
0x4008_2000
Reserved
0x4008_0000
FMC
0x4007_8000
0x4007_7000
0x4007_6000
Reserved
AHB
BFTM1
0x4007_2000
BFTM0
Reserved
0x4007_1000
PWM1(Note)
0x4006_F000
Reserved
0x4006_E000
GPTM
0x4006_B000
Reserved
0x4006_A000
RTC & PWRCU
0x4006_9000
Reserved
0x4006_8000
WDT
0x4005_B000
Reserved
0x4005_A000
LEDC
0x4005_9000
Reserved
0x4005_8000
CMP(Note)
0x4004_A000
Reserved
0x4004_9000
I2C1
0x4004_8000
I2C0
0x4004_5000
Reserved
0x4004_4000
SPI1
0x4004_2000
Reserved
0x4004_1000
UART1
0x4004_0000
USART1(Note)
0x4003_2000
Reserved
0x4003_1000
PWM0
0x4002_D000
Reserved
0x4002_C000
MCTM
0x4002_5000
Reserved
0x4002_4000
EXTI
0x4002_3000
Reserved
0x4002_2000
AFIO
0x4001_1000
Reserved
0x4001_0000
ADC
0x4000_E000
Reserved
0x4000_C000
CAN
0x4000_5000
Reserved
0x4000_4000
SPI0
0x4000_2000
Reserved
0x4000_1000
UART0
0x4000_0000
USART0
APB
0x0000_0000
Note: These functions and GPIO D are only available for the HT32F53242/HT32F53252 only, since there is only one USART
and one PWM in the HT32F53231/HT32F53241 devices, their corresponding descriptions do not have serial number "0".
Figure 3. Memory Map
Rev. 1.00
19 of 56
March 06, 2024
3 Overview
0xE010_0000
Reserved
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Table 2. Register Map
End Address
Peripheral
0x4000_0000
0x4000_0FFF
USART0
0x4000_1000
0x4000_1FFF
UART0
0x4000_2000
0x4000_3FFF
Reserved
0x4000_4000
0x4000_4FFF
SPI0
0x4000_5000
0x4000_BFFF
Reserved
0x4000_C000
0x4000_DFFF
CAN
0x4000_E000
0x4000_FFFF
Reserved
0x4001_0000
0x4001_0FFF
ADC
0x4001_1000
0x4002_1FFF
Reserved
0x4002_2000
0x4002_2FFF
AFIO
0x4002_3000
0x4002_3FFF
Reserved
0x4002_4000
0x4002_4FFF
EXTI
0x4002_5000
0x4002_BFFF
Reserved
0x4002_C000
0x4002_CFFF
MCTM
0x4002_D000
0x4003_0FFF
Reserved
0x4003_1000
0x4003_1FFF
PWM0
0x4003_2000
0x4004_0FFF
Reserved
0x4004_0000
0x4004_0FFF
USART1 (Note)
0x4004_1000
0x4004_1FFF
UART1
0x4004_2000
0x4004_3FFF
Reserved
0x4004_4000
0x4004_4FFF
SPI1
0x4004_5000
0x4004_7FFF
Reserved
0x4004_8000
0x4004_8FFF
I2C0
0x4004_9000
0x4004_9FFF
I2C1
0x4004_A000
0x4005_7FFF
Reserved
0x4005_8000
0x4005_8FFF
CMP (Note)
0x4005_9000
0x4005_9FFF
Reserved
0x4005_A000
0x4005_AFFF
LEDC
0x4005_B000
0x4006_7FFF
Reserved
0x4006_8000
0x4006_8FFF
WDT
0x4006_9000
0x4006_9FFF
Reserved
0x4006_A000
0x4006_AFFF
RTC & PWRCU
0x4006_B000
0x4006_DFFF
Reserved
0x4006_E000
0x4006_EFFF
GPTM
0x4006_F000
0x4007_0FFF
Reserved
0x4007_1000
0x4007_1FFF
PWM1 (Note)
0x4007_2000
0x4007_5FFF
Reserved
0x4007_6000
0x4007_6FFF
BFTM0
0x4007_7000
0x4007_7FFF
BFTM1
0x4007_8000
0x4007_FFFF
Reserved
20 of 56
Bus
3 Overview
Rev. 1.00
Start Address
APB
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Start Address
End Address
Peripheral
0x4008_0000
0x4008_1FFF
FMC
0x4008_2000
0x4008_7FFF
Reserved
0x4008_8000
0x4008_9FFF
CKCU & RSTCU
0x4008_BFFF
CRC
0x400A_FFFF
Reserved
0x4009_0000
0x4009_1FFF
PDMA
0x4009_2000
0x4009_7FFF
Reserved
0x4009_8000
0x4009_9FFF
EBI (Note)
0x4009_A000
0x400A_FFFF
Reserved
0x400B_0000
0x400B_1FFF
GPIO A
0x400B_2000
0x400B_3FFF
GPIO B
0x400B_4000
0x400B_5FFF
GPIO C
0x400B_6000
0x400B_7FFF
GPIO D (Note)
0x400B_8000
0x400C_9FFF
Reserved
0x400C_A000
0x400C_BFFF
DIV
0x400C_C000
0x400F_FFFF
Reserved
AHB
Note: These functions are only available for the HT32F53242/HT32F53252 only.
Rev. 1.00
21 of 56
March 06, 2024
3 Overview
0x4008_A000
0x4008_C000
Bus
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Clock Structure
CK_LSE
HSI Auto
Trimming
Controller
CKREFPRE
Prescaler
÷ 1 ~ 32
CKREFEN
Divider
÷2
CK_REF
CK_IN(2)
STCLK
(to SysTick)
÷ 8
8 MHz
HSI RC
FCLK
( free running clock)
PLLSRC
PLLEN
1
HSIEN
CK_PLL
SW[2:0]
PLL
0
4 ~ 16 MHz
HSE XTAL
00x
CK_HSI
HSEEN
HCLKC
( to Cortex®-M0+)
CM0PEN
(control by HW)
HCLKD
( to PDMA)
PDMAEN
fCK_SYS,max = 60 MHz
011
CK_HSE
010
CK_SYS AHB Prescaler
÷ 1,2,4,8,16,32
CRCEN
CK_CRC
( to CRC)
EBIEN
CK_EBI
( to EBI)
DIVEN
CK_DIV
( to DIV)
111
CK_AHB
110
Clock
Monitor
32.768 kHz
LSE OSC
CK_LSE
WDTSRC
LSEEN(1)
32 kHz
LSI RC
1
0
CK_LSI
CK_WDT
CM0PEN
RTCSRC(1)
SRAMEN
CK_RTC
RTCEN(1)
CKOUT
HCLKBM
( to Bus Matrix)
CM0PEN
BMEN
HCLKAPB
( to APB Bridge)
CKOUTSRC[2:0]
000
001
FMCEN
HCLKS
( to SRAM)
WDTEN
1
0
HCLKF
( to Flash)
CM0PEN
CM0PEN
CK_REF
010
HCLKC/16
CK_SYS/16
011
CK_HSE/16
100
101
CK_HSI/16
110
CK_LSI
CK_LSE
APBEN
CK_AHB
Peripherals
Clock
Prescaler
÷ 1,2,4,8
Legend:
HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
Note: 1. These control bits are located in RTC Control Register (RTCCR).
2. The CK_IN signal is sourced from the external CKIN pin.
00
CK_AHB/2
CK_AHB/4
CK_AHB/8
PCLK (AFIO, ADC,
CMP, USARTx,
UARTx, SPIx, I2Cx,
GPTM, MCTM,
PWMx, BFTMx, EXTI,
LEDC, RTC, PWRCU,
WDT, CAN)
01
10
11
SPIxEN
I2CxEN
ADC
Prescaler
÷ 1,2,3,4,8...
CK_ADC IP
ADCEN
Figure 4. Clock Structure
Rev. 1.00
22 of 56
March 06, 2024
3 Overview
CK_GPIO
( to GPIO port)
PAEN
PDEN
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
4
Pin Assignment
HT32F53242/HT32F53252
32 QFN-A
PB4
PB3
PB2
31
30
29
28
27
26
25
AP
AP
VDD
AF1
VDD VDD VDD VDD VDD VDD
VDD
PVDD
AF0
(Default)
4 Pin Assignment
PB5
32
AF0
(Default)
PB7
2
PB8
PA1
1
VDDA
PA0
VSSA
AF0
(Default)
VDD Digital Power Pad
AP
Analog Power Pad
VDD
24
PB1
VDD
23
PB0
VDD
22
PA15
PA2
3
VDD
PA3
4
VDD
P15
1.5 V Power Pad
VDD
21
PA14
PA4
5
VDD
VDD
VDD Digital & Analog I/O Pad
VDD
20
SWDIO
PA13
PA5
6
VDD
VDD
VDD Digital I/O Pad
VDD
19
SWCLK
PA12
PC4
7
VDD
VDD
VDD Domain Pad
VDD
18
PA9_BOOT
PC5
8
VDD
VDD
17
XTALOUT
PB14
P15 PVDD PVDD VDD VDD VDD VDD VDD
9
10
11
12
13
14
15
16
CLDO
VDD_1
VSS_1
nRST
X32KIN
X32KOUT
RTCOUT
XTALIN
AF0
(Default)
PB10
PB11
PB12
PB13
AF1
Figure 5. HT32F53242/HT32F53252 32-pin QFN Pin Assignment
Rev. 1.00
23 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
HT32F53242/HT32F53252
46 QFN-A
PC4
6
VDD
PC5
7
VDD
PC6
8
VDD
PC7
9
VDD
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
AP
AP
AF1
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD PVDD
VDD Power Pad
PIO
VDDIO Power Pad
AP
Analog Power Pad
VDDIO
VDDIO Digital I/O Pad
P15
1.5 V Power Pad
VDD
VDD Digital & Analog I/O Pad
PVDD
AF0
(Default)
4 Pin Assignment
VDD
46
AF0
(Default)
5
VSS_2
PA5
PB2
VDD
PB3
4
PB4
PA4
PB5
VDD
PC1
3
PC2
PA3
PC3
VDD
PB6
2
PB7
PA2
PB8
VDD
VDDA
1
VSSA
PA1
PA0
AF0
(Default)
VDD
VDD Digital I/O Pad
VDD
VDD Domain Pad
P15 PVDD PVDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDIO
VDDIO
12
13
14
15
16
17
18
19
20
21
22
23
VDDIO
VDDIO
31
PB1
VDDIO
30
PB0
VDDIO
29
PA15
VDDIO
28
PA14
VDDIO
27
SWDIO
PA13
VDDIO
26
SWCLK
PA12
VDDIO
25
PA11
VDDIO
24
PA10
CLDO
VDD_1
VSS_1
nRST
PB9
X32KIN
X32KOUT
RTCOUT
XTALIN
XTALOUT
PB15
PC0
PA8
PA9_BOOT
PB10
PB11
PB12
PB13
PB14
AF1
11
32
AF0
(Default)
10
PIO
Figure 6. HT32F53242/HT32F53252 46-pin QFN Pin Assignment
Rev. 1.00
24 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
HT32F53242/HT32F53252
48 LQFP-A
5
47
46
45
44
43
42
41
40
39
38
37
AP
AP
AF0
(Default)
AF1
4 Pin Assignment
PA4
48
AF0
(Default)
VDD
PB2
4
PB3
PA3
PB4
VDD
PB5
3
PC1
PA2
PC2
VDD
PC3
2
PB6
PA1
PB7
VDD
PB8
1
VDDA
PA0
VSSA
AF0
(Default)
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
PVDD
VDD Power Pad
AP
Analog Power Pad
P15
1.5 V Power Pad
VDD
VDD Digital & Analog IO Pad
VDD
PA5
6
VDD
PA6
7
VDD
VDD
VDD Digital I/O Pad
PA7
8
VDD
VDD
VDD Domain Pad
PC4
9
VDD
PIO
VDDIO Power Pad
PC5
10
VDD
VDDIO
VDDIO Digital I/O Pad
PVDD
36
VSS_2
PIO
35
VDDIO
VDDIO
34
PB1
VDDIO
33
PB0
VDDIO
32
PA15
VDDIO
31
PA14
VDDIO
30
SWDIO
PA13
VDDIO
29
SWCLK
PA12
VDDIO
28
PA11
VDDIO
27
PA10
PC6
11
VDD
VDDIO
26
PA9_BOOT
PC7
12
VDD
VDDIO
25
PA8
P15 PVDD PVDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
15
16
17
18
19
20
21
22
23
24
CLDO
VDD_1
VSS_1
nRST
PB9
X32KIN
X32KOUT
RTCOUT
XTALIN
XTALOUT
PB15
PC0
PB10
PB11
PB12
PB13
PB14
AF1
14
AF0
(Default)
13
Figure 7. HT32F53242/HT32F53252 48-pin LQFP Pin Assignment
Rev. 1.00
25 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
HT32F53242/HT32F53252
64 LQFP-A
VDDA
PB8
PB7
PB6
PC3
PC2
PC1
VSS_3
VDD_3
PC15
PC14
PB5
PB4
PB3
PB2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AP
AP
AF0
(Default)
VSSA
AF0
(Default)
AF0
(Default)
AF1
4 Pin Assignment
VDD VDD VDD VDD VDD VDD PVDD PVDD VDD VDD VDD VDD VDD VDD
PA0
1
VDD
VDDIO
48
PD3
PA1
2
VDD
VDDIO
47
PD2
PA2
3
VDD
VDDIO
46
PD1
PA3
4
VDD
VDDIO
45
PB1
PA4
5
VDD
VDDIO
44
PB0
PA5
6
VDD
PVDD
43
VSS_2
PIO
42
VDDIO
VDDIO
41
PA15
VDDIO
40
PA14
VDDIO
39
SWDIO
PA13
VDDIO
38
SWCLK
PA12
VDDIO
37
PA11
PA6
PA7
7
8
PVDD
VDD
VDD
PD4
9
VDD
PD5
10
VDD
PC4
11
VDD
PC5
12
VDD
VDD Power Pad
AP
Analog Power Pad
P15
1.5 V Power Pad
VDD
VDD Digital & Analog I/O Pad
VDD
VDD Digital I/O Pad
VDD
VDD Domain Pad
PIO
VDDIO Power Pad
VDDIO
VDDIO Digital I/O Pad
PC8
13
VDD
VDDIO
36
PA10
PC9
14
VDD
VDDIO
35
PA9_BOOT
PC6
15
VDD
VDDIO
34
PA8
PC7
16
VDD
VDD
33
PC13
P15 PVDD PVDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
PB9
X32KIN
X32KOUT
RTCOUT
PB10
PB11
PB12
29
30
31
32
AF1
nRST
28
AF0
(Default)
VSS_1
27
PC12
VDD_1
26
PC11
CLDO
25
PC10
24
PC0
23
PB15
22
PB14
21
XTALOUT
20
PB13
19
XTALIN
18
PD0
17
Figure 8. HT32F53242/HT32F53252 64-pin LQFP Pin Assignment
Rev. 1.00
26 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
HT32F53231/HT32F53241
32 QFN-A
PB4
PB3
PB2
31
30
29
28
27
26
25
AP
AP
VDD
AF1
VDD VDD VDD VDD VDD VDD
VDD
PVDD
AF0
(Default)
4 Pin Assignment
PB5
32
AF0
(Default)
PB7
2
PB8
PA1
1
VDDA
PA0
VSSA
AF0
(Default)
VDD Digital Power Pad
AP
Analog Power Pad
VDD
24
PB1
VDD
23
PB0
VDD
22
PA15
PA2
3
VDD
PA3
4
VDD
P15
1.5 V Power Pad
VDD
21
PA14
PA4
5
VDD
VDD
VDD Digital & Analog I/O Pad
VDD
20
SWDIO
PA13
PA5
6
VDD
VDD
VDD Digital I/O Pad
VDD
19
SWCLK
PA12
PC4
7
VDD
VDD
VDD Domain Pad
VDD
18
PA9_BOOT
PC5
8
VDD
VDD
17
XTALOUT
PB14
P15 PVDD PVDD VDD VDD VDD VDD VDD
9
10
11
12
13
14
15
16
CLDO
VDD_1
VSS_1
nRST
X32KIN
X32KOUT
RTCOUT
XTALIN
AF0
(Default)
PB12
PB13
AF1
Figure 9. HT32F53231/HT32F53241 32-pin QFN Pin Assignment
Rev. 1.00
27 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
HT32F53231/HT32F53241
46 QFN-A
PC4
6
VDD
PC5
7
VDD
PC6
8
VDD
PC7
9
VDD
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
AP
AP
AF1
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD PVDD
VDD Power Pad
PIO
VDDIO Power Pad
AP
Analog Power Pad
VDDIO
VDDIO Digital I/O Pad
P15
1.5 V Power Pad
VDD
VDD Digital & Analog I/O Pad
PVDD
AF0
(Default)
4 Pin Assignment
VDD
46
AF0
(Default)
5
VSS_2
PA5
PB2
VDD
PB3
4
PB4
PA4
PB5
VDD
PC1
3
PC2
PA3
PC3
VDD
PB6
2
PB7
PA2
PB8
VDD
VDDA
1
VSSA
PA1
PA0
AF0
(Default)
VDD
VDD Digital I/O Pad
VDD
VDD Domain Pad
P15 PVDD PVDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
VDDIO
VDDIO
12
13
14
15
16
17
18
19
20
21
22
23
VDDIO
VDDIO
31
PB1
VDDIO
30
PB0
VDDIO
29
PA15
VDDIO
28
PA14
VDDIO
27
SWDIO
PA13
VDDIO
26
SWCLK
PA12
VDDIO
25
PA11
VDDIO
24
PA10
CLDO
VDD_1
VSS_1
nRST
PB9
X32KIN
X32KOUT
RTCOUT
XTALIN
XTALOUT
PB15
PC0
PA8
PA9_BOOT
PB10
PB11
PB12
PB13
PB14
AF1
11
32
AF0
(Default)
10
PIO
Figure 10. HT32F53231/HT32F53241 46-pin QFN Pin Assignment
Rev. 1.00
28 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
HT32F53231/HT32F53241
48 LQFP-A
47
46
45
44
43
42
41
40
39
38
37
AP
AP
VDD Power Pad
AP
Analog Power Pad
P15
1.5 V Power Pad
PA4
5
VDD
PA5
6
VDD
VDD
VDD Digital & Analog IO Pad
PA6
7
VDD
VDD
VDD Digital I/O Pad
PA7
8
VDD
VDD
VDD Domain Pad
PC4
9
VDD
PIO
VDDIO Power Pad
VDDIO
VDDIO Digital I/O Pad
PC5
10
VDD
PC6
11
VDD
PC7
12
VDD
AF1
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
PVDD
VDD
AF0
(Default)
4 Pin Assignment
48
AF0
(Default)
PB2
4
PB3
PA3
PB4
VDD
PB5
3
PC1
PA2
PC2
VDD
PC3
2
PB6
PA1
PB7
VDD
PB8
1
VDDA
PA0
VSSA
AF0
(Default)
PVDD
36
VSS_2
PIO
35
VDDIO
VDDIO
34
PB1
VDDIO
33
PB0
VDDIO
32
PA15
VDDIO
31
PA14
VDDIO
30
SWDIO
PA13
VDDIO
29
SWCLK
PA12
VDDIO
28
PA11
VDDIO
27
PA10
VDDIO
26
PA9_BOOT
VDDIO
25
PA8
P15 PVDD PVDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
15
16
17
18
19
20
21
22
23
24
CLDO
VDD_1
VSS_1
nRST
PB9
X32KIN
X32KOUT
RTCOUT
XTALIN
XTALOUT
PB15
PC0
PB10
PB11
PB12
PB13
PB14
AF1
14
AF0
(Default)
13
Figure 11. HT32F53231/HT32F53241 48-pin LQFP Pin Assignment
Rev. 1.00
29 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Table 3. HT32F53242/HT32F53252 Pin Assignment
Alternate Function Mapping
Packages
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
64
LQFP
48
LQFP
46
QFN
32
QFN
System
Default
GPIO
ADC
CMP
MCTM
/GPTM
SPI
USART
/UART
I2C
N/A
EBI
N/A
N/A
CAN
PWM
LEDC
System
Other
1
1
46
1
PA0
ADC_
IN0
GT_
CH0
SPI1_
SCK
USR0_
RTS
I2C1_
SCL
LED_
SEG0
VREF
GT_
CH1
SPI1_
MOSI
USR0_
CTS
I2C1_
SDA
LED_
SEG1
2
1
2
PA1
3
3
2
3
PA2
ADC_
IN2
GT_
CH2
SPI1_
MISO
USR0_
TX
LED_
SEG2
4
4
3
4
PA3
ADC_
IN3
GT_
CH3
SPI1_
SEL
USR0_
RX
LED_
SEG3
5
5
4
5
PA4
ADC_
IN4
GT_
CH0
SPI0_
SCK
USR1_
TX
I2C0_
SCL
LED_
SEG4
6
6
5
6
PA5
ADC_
IN5
GT_
CH1
SPI0_
MOSI
USR1_
RX
I2C0_
SDA
LED_
SEG5
7
7
PA6
ADC_
IN6
GT_
CH2
SPI0_
MISO
USR1_
RTS
CAN_
TX
LED_
SEG6
8
8
PA7
ADC_
IN7
GT_
CH3
SPI0_
SEL
USR1_
CTS
CAN_
RX
LED_
SEG7
9
PD4
ADC_
IN8
USR1_
TX
EBI_
A2
LED_
SEG4
10
PD5
ADC_
IN9
USR1_
RX
EBI_
A3
LED_
SEG5
11
9
6
7
PC4
ADC_
IN10
GT_
CH0
SPI1_
SEL
USR0_
TX
I2C1_
SCL
EBI_
A19
CAN_
TX
PWM1_
CH0
LED_
COM4
12
10
7
8
PC5
ADC_
IN11
GT_
CH1
SPI1_
SCK
USR0_
RX
I2C1_
SDA
EBI_
A20
CAN_
RX
PWM1_
CH1
LED_
COM5
13
PC8
MT_
CH2
SPI1_
MOSI
UR0_
TX
EBI_
A0
LED_
COM6
14
PC9
MT_
CH2N
SPI1_
MISO
UR0_
RX
EBI_
A1
LED_
COM7
15
11
8
PC6
GT_
CH2
SPI1_
MOSI
UR1_
TX
I2C0_
SCL
CAN_
TX
PWM1_
CH2
LED_
COM10
16
12
9
PC7
GT_
CH3
SPI1_
MISO
UR1_
RX
I2C0_
SDA
CAN_
RX
PWM1_
CH3
LED_
COM11
17
13
10
9
CLDO
18
14
11
10
VDD_1
19
15
12
11
VSS_1
20
16
13
12
nRST
21
17
14
22
18
15
13
X32KIN
PB10
GT_
CH0
SPI1_
SEL
USR1_
TX
LED_
SEG4
23
19
16
14
X32KOUT
PB11
GT_
CH1
SPI1_
SCK
USR1_
RX
LED_
SEG5
24
20
17
15
RTCOUT
PB12
SPI0_
MISO
UR0_
RX
MT_
CH3
PB9
25
UR0_
TX
WAKEUP1
WAKEUP0
I2C0_
SDA
PD0
EBI_
A18
26
21
18
16
XTALIN
PB13
PWM1_
CH1
LED_
SEG6
27
22
19
17
XTALOUT
PB14
PWM1_
CH2
LED_
SEG7
28
23
20
PB15
MT_
CH0
SPI0_
SEL
USR1_
TX
I2C1_
SCL
EBI_
A16
PWM0_
CH2
29
24
21
PC0
MT_
CH0N
SPI0_
SCK
USR1_
RX
I2C1_
SDA
EBI_
A17
PWM0_
CH3
30
PC10
GT_
CH0
SPI1_
SEL
EBI_
AD13
CAN_
TX
LED_
SEG0
31
PC11
GT_
CH1
SPI1_
SCK
EBI_
AD14
CAN_
RX
LED_
SEG1
32
PC12
GT_
CH2
SPI1_
MOSI
UR1_
TX
I2C0_
SCL
EBI_
AD15
PWM0_
CH2
LED_
SEG2
33
PC13
GT_
CH3
SPI1_
MISO
UR1_
RX
I2C0_
SDA
EBI_
CS3
PWM0_
CH3
LED_
SEG3
PWM1_
CH3
LED_
COM1
34
25
Rev. 1.00
22
PA8
USR0_
TX
30 of 56
4 Pin Assignment
2
ADC_
IN1
LED_
COM0
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Alternate Function Mapping
Packages
AF0
64
LQFP
48
LQFP
46
QFN
32
QFN
System
Default
35
26
23
18
PA9_
BOOT
AF1
GPIO
AF2
ADC
AF3
AF4
CMP
MCTM
/GPTM
AF5
AF6
SPI
USART
/UART
AF7
I2C
SPI0_
MOSI
N/A
AF9
EBI
AF10
N/A
AF11
N/A
AF12
CAN
EBI_
A1
PWM
AF14
AF15
LEDC
System
Other
PWM1_
CH0
27
24
PA10
37
28
25
PA11
MT_
CH1N
SPI0_
MISO
38
29
26
19
SWCLK
PA12
39
30
27
20
SWDIO
PA13
40
31
28
21
PA14
MT_
CH0
SPI1_
SEL
USR0_
RTS
I2C1_
SCL
EBI_
AD0
PWM0_
CH0
LED_
COM0
41
32
29
22
PA15
MT_
CH0N
SPI1_
SCK
USR0_
CTS
I2C1_
SDA
EBI_
AD1
PWM0_
CH1
LED_
COM1
42
35
32
43
36
33
44
33
30
23
PB0
MT_
CH1
SPI1_
MOSI
USR0_
TX
I2C0_
SCL
EBI_
AD2
CAN_
TX
45
34
31
24
PB1
MT_
CH1N
SPI1_
MISO
USR0_
RX
I2C0_
SDA
EBI_
AD3
CAN_
RX
46
PD1
MT_
CH2
USR1_
RTS
EBI_
AD10
CAN_
TX
47
PD2
MT_
CH2N
USR1_
CTS
EBI_
AD11
CAN_
RX
48
PD3
MT_
CH3
EBI_
A0
PWM0_
CH1
CAN_
RX
LED_
COM2
LED_
COM3
4 Pin Assignment
34
CAN_
TX
CKOUT
36
37
USR0_
RX
AF13
MT_
CH1
49
SPI0_
MOSI
AF8
VDDIO
VSS_2
25
PB2
LED_
SEG0
PWM1_
CH2
LED_
SEG1
LED_
SEG6
EBI_
AD12
LED_
SEG7
COUT0
MT_
CH2
SPI0_
SEL
UR0_
TX
EBI_
AD4
CAN_
TX
PWM0_
CH2
LED_
SEG2
COUT1
MT_
CH2N
SPI0_
SCK
UR0_
RX
EBI_
AD5
CAN_
RX
PWM0_
CH0
LED_
SEG3
PWM0_
CH1
LED_
COM2
50
38
35
26
PB3
51
39
36
27
PB4
MT_
BRK
SPI0_
MOSI
UR1_
TX
EBI_
AD6
52
40
37
28
PB5
GT_
CH2
SPI0_
MISO
UR1_
RX
EBI_
AD7
LED_
COM3
I2C0_
SCL
EBI_
AD8
LED_
COM8
I2C0_
SDA
EBI_
AD9
LED_
COM9
53
PC14
COUT0
54
PC15
COUT1
55
VDD_3
56
MT_
CH3
CKIN
VSS_3
57
41
38
PC1
CN0
MT_
CH0
SPI1_
SEL
58
42
39
PC2
CP0
MT_
CH0N
SPI1_
SCK
59
43
40
PC3
COUT0
MT_
BRK
SPI1_
MOSI
60
44
41
PB6
CN1
GT_
CH3
SPI1_
MISO
61
45
42
29
PB7
CP1
MT_
CH1
SPI0_
MISO
UR0_
TX
I2C1_
SCL
EBI_
CS1
PWM0_
CH3
LED_
SEG4
62
46
43
30
PB8
COUT1
MT_
CH1N
SPI0_
SEL
UR0_
RX
I2C1_
SDA
EBI_
CS2
PWM1_
CH3
LED_
SEG5
63
47
44
31
VDDA
64
48
45
32
VSSA
Rev. 1.00
UR1_
TX
UR1_
RX
EBI_
OE
PWM0_
CH0
LED_
COM4
EBI_
CS0
PWM1_
CH0
LED_
COM5
EBI_
WE
PWM1_
CH1
LED_
COM6
EBI_
ALE
31 of 56
LED_
COM7
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Table 4. HT32F53231/HT32F53241 Pin Assignment
Alternate Function Mapping
Packages
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
GPIO
ADC
N/A
MCTM
/GPTM
SPI
USART
/UART
I2C
N/A
N/A
N/A
N/A
CAN
PWM
LEDC
System
Other
VREF
46
QFN
32
QFN
System
Default
1
46
1
PA0
ADC_
IN0
GT_
CH0
SPI1_
SCK
USR_
RTS
I2C1_
SCL
LED_
SEG0
2
1
2
PA1
ADC_
IN1
GT_
CH1
SPI1_
MOSI
USR_
CTS
I2C1_
SDA
LED_
SEG1
3
2
3
PA2
ADC_
IN2
GT_
CH2
SPI1_
MISO
USR_
TX
LED_
SEG2
4
3
4
PA3
ADC_
IN3
GT_
CH3
SPI1_
SEL
USR_
RX
LED_
SEG3
5
4
5
PA4
ADC_
IN4
GT_
CH0
SPI0_
SCK
USR_
TX
I2C0_
SCL
LED_
SEG4
6
5
6
PA5
ADC_
IN5
GT_
CH1
SPI0_
MOSI
USR_
RX
I2C0_
SDA
LED_
SEG5
7
PA6
ADC_
IN6
GT_
CH2
SPI0_
MISO
USR_
RTS
CAN_
TX
LED_
SEG6
8
PA7
ADC_
IN7
GT_
CH3
SPI0_
SEL
USR_
CTS
CAN_
RX
LED_
SEG7
9
6
7
PC4
ADC_
IN8
GT_
CH0
SPI1_
SEL
USR_
TX
I2C1_
SCL
CAN_
TX
PWM_
CH0
LED_
COM4
10
7
8
PC5
ADC_
IN9
GT_
CH1
SPI1_
SCK
USR_
RX
I2C1_
SDA
CAN_
RX
PWM_
CH1
LED_
COM5
11
8
PC6
ADC_
IN10
GT_
CH2
SPI1_
MOSI
UR1_
TX
I2C0_
SCL
CAN_
TX
PWM_
CH2
LED_
COM6
12
9
PC7
ADC_
IN11
GT_
CH3
SPI1_
MISO
UR1_
RX
I2C0_
SDA
CAN_
RX
PWM_
CH3
LED_
COM7
13
10
9
CLDO
14
11
10
VDD_1
15
12
11
VSS_1
16
13
12
nRST
17
14
PB9
MT_
CH3
UR0_
TX
SPI1_
SEL
USR_
TX
LED_
SEG4
SPI1_
SCK
USR_
RX
LED_
SEG5
SPI0_
MISO
UR0_
RX
WAKEUP1
18
15
13
X32KIN
PB10
GT_
CH0
19
16
14
X32KOUT
PB11
GT_
CH1
20
17
15
RTCOUT
PB12
21
18
16
XTALIN
PB13
PWM_
CH1
LED_
SEG6
22
19
17
XTALOUT
PB14
PWM_
CH2
LED_
SEG7
23
20
PB15
MT_
CH0
SPI0_
SEL
USR_
TX
I2C1_
SCL
PWM_
CH2
24
21
PC0
MT_
CH0N
SPI0_
SCK
USR_
RX
I2C1_
SDA
PWM_
CH3
LED_
COM0
25
22
PA8
PWM_
CH3
LED_
COM1
26
23
27
24
PA10
MT_
CH1
SPI0_
MOSI
28
25
PA11
MT_
CH1N
SPI0_
MISO
29
26
19
SWCLK
PA12
30
27
20
SWDIO
PA13
31
28
21
PA14
MT_
CH0
SPI1_
SEL
USR_
RTS
I2C1_
SCL
PWM_
CH0
LED_
COM0
32
29
22
PA15
MT_
CH0N
SPI1_
SCK
USR_
CTS
I2C1_
SDA
PWM_
CH1
LED_
COM1
33
30
23
PB0
MT_
CH1
SPI1_
MOSI
USR_
TX
I2C0_
SCL
Rev. 1.00
18
WAKEUP0
USR_
TX
PA9_
BOOT
4 Pin Assignment
48
LQFP
SPI0_
MOSI
PWM_
CH0
USR_
RX
CAN_
TX
PWM_
CH1
CAN_
RX
32 of 56
CAN_
TX
CKOUT
LED_
COM2
LED_
COM3
LED_
SEG0
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Alternate Function Mapping
Packages
AF0
AF1
AF2
AF3
AF4
AF5
AF6
MCTM
/GPTM
SPI
USART
/UART
N/A
I2C
MT_
CH1N
SPI1_
MISO
USR_
RX
I2C0_
SDA
46
QFN
32
QFN
System
Default
34
31
24
PB1
35
32
VDDIO
36
33
VSS_2
37
34
25
PB2
MT_
CH2
SPI0_
SEL
38
35
26
PB3
MT_
CH2N
39
36
27
PB4
40
37
28
41
GPIO
ADC
AF7
AF8
N/A
AF9
N/A
AF10
N/A
AF11
N/A
AF12
AF13
AF14
AF15
System
Other
CAN
PWM
LEDC
CAN_
RX
PWM_
CH2
LED_
SEG1
UR0_
TX
CAN_
TX
PWM_
CH2
LED_
SEG2
SPI0_
SCK
UR0_
RX
CAN_
RX
PWM_
CH0
LED_
SEG3
MT_
BRK
SPI0_
MOSI
UR1_
TX
PWM_
CH1
LED_
COM2
PB5
GT_
CH2
SPI0_
MISO
UR1_
RX
38
PC1
MT_
CH0
SPI1_
SEL
UR1_
TX
42
39
PC2
MT_
CH0N
SPI1_
SCK
43
40
PC3
MT_
BRK
SPI1_
MOSI
44
41
PB6
GT_
CH3
SPI1_
MISO
45
42
29
PB7
MT_
CH1
SPI0_
MISO
UR0_
TX
I2C1_
SCL
PWM_
CH3
LED_
SEG4
46
43
30
PB8
MT_
CH1N
SPI0_
SEL
UR0_
RX
I2C1_
SDA
PWM_
CH3
LED_
SEG5
47
44
31
VDDA
48
45
32
VSSA
CKIN
LED_
COM3
UR1_
RX
PWM_
CH0
LED_
COM4
PWM_
CH0
LED_
COM5
PWM_
CH1
LED_
COM6
LED_
COM7
Table 5. HT32F53242/HT32F53252 Pin Description
Pin Number
64
48
46
32
LQFP LQFP QFN QFN
Pin
Name
Type(1)
I/O
Structure(2)
Description
Output
Driving
Default Function (AF0)
1
1
46
1
PA0
AI/O
5V
4/8/12/16 mA PA0
2
2
1
2
PA1
AI/O
5V
4/8/12/16 mA PA1
3
3
2
3
PA2
AI/O
5V
4/8/12/16 mA PA2
4
4
3
4
PA3
AI/O
5V
4/8/12/16 mA PA3
5
5
4
5
PA4
AI/O
5V
4/8/12/16 mA
PA4, this pin provides a USART_TX
function in the Boot loader mode.
6
6
5
6
PA5
AI/O
5V
4/8/12/16 mA
PA5, this pin provides a USART_RX
function in the Boot loader mode.
7
7
PA6
AI/O
5V
4/8/12/16 mA PA6
8
8
PA7
AI/O
5V
4/8/12/16 mA PA7
9
PD4
AI/O
5V
4/8/12/16 mA PD4
10
PD5
AI/O
5V
4/8/12/16 mA PD5
11
9
6
7
PC4
I/O
5V
4/8/12/16 mA PC4
12
10
7
8
PC5
I/O
5V
4/8/12/16 mA PC5
PC8
I/O
5V
4/8/12/16 mA PC8
13
14
PC9
I/O
5V
4/8/12/16 mA PC9
15
11
8
PC6
I/O
5V
4/8/12/16 mA PC6
16
12
9
PC7
I/O
5V
4/8/12/16 mA PC7
Rev. 1.00
33 of 56
March 06, 2024
4 Pin Assignment
48
LQFP
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Pin Number
64
48
46
32
LQFP LQFP QFN QFN
Pin
Name
Type(1)
I/O
Structure(2)
Description
Output
Driving
Default Function (AF0)
13
10
9
CLDO
P
—
—
18
14
11
10
VDD_1
P
—
—
Voltage for VDD domain digital I/O
19
15
12
11
VSS_1
P
—
—
Ground reference for digital I/O
20
16
13
12
nRST(3)
I
5V_PU
—
External reset pin
21
17
14
PB9(3)
I/O
(VDD)
5V
4/8/12/16 mA PB9
22
18
15
13
PB10(3)
AI/O
(VDD)
5V
4/8/12/16 mA X32KIN
23
19
16
14
PB11(3)
AI/O
(VDD)
5V
4/8/12/16 mA X32KOUT
24
20
17
15
PB12(3)
I/O
(VDD)
5V
4/8/12/16 mA RTCOUT
PD0
I/O
5V
4/8/12/16 mA PD0
25
26
21
18
16
PB13
AI/O
5V
4/8/12/16 mA XTALIN
27
22
19
17
PB14
AI/O
5V
4/8/12/16 mA XTALOUT
28
23
20
PB15
I/O
5V
4/8/12/16 mA PB15
29
24
21
PC0
I/O
5V
4/8/12/16 mA PC0
30
PC10
I/O
5V
4/8/12/16 mA PC10
31
PC11
I/O
5V
4/8/12/16 mA PC11
32
PC12
I/O
5V
4/8/12/16 mA PC12
33
PC13
I/O
5V
4/8/12/16 mA PC13
PA8
I/O
(VDDIO)
5V
4/8/12/16 mA PA8
PA9
I/O
(VDDIO)
5V_PU
34
25
22
35
26
23
36
27
24
PA10
I/O
(VDDIO)
5V
4/8/12/16 mA PA10
37
28
25
PA11
I/O
(VDDIO)
5V
4/8/12/16 mA PA11
38
29
26
19(5)
PA12
I/O
(VDDIO)
5V_PU
4/8/12/16 mA SWCLK
39
30
27
20(5)
PA13
I/O
(VDDIO)
5V_PU
4/8/12/16 mA SWDIO
40
31
28
21(5)
PA14
I/O
(VDDIO)
5V
4/8/12/16 mA PA14
41
32
29
22(5)
PA15
I/O
(VDDIO)
5V
4/8/12/16 mA PA15
42
35
32
VDDIO
P
—
—
Voltage for digital VDDIO domain I/O
43
36
33
VSS_2
P
—
—
Ground reference for digital I/O
44
33
30
PB0
I/O
(VDDIO)
5V
Rev. 1.00
18(5)
23(5)
34 of 56
4/8/12/16 mA PA9_BOOT
4/8/12/16 mA PB0
March 06, 2024
4 Pin Assignment
17
Core power LDO output
It must be connected a 2.2 μF
capacitor as close as possible
between this pin and VSS_1.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Pin Number
Description
Pin
Name
Type(1)
I/O
Structure(2)
PB1
I/O
(VDDIO)
5V
4/8/12/16 mA PB1
46
PD1
I/O
(VDDIO)
5V
4/8/12/16 mA PD1
47
PD2
I/O
(VDDIO)
5V
4/8/12/16 mA PD2
48
PD3
I/O
(VDDIO)
5V
4/8/12/16 mA PD3
64
48
46
32
LQFP LQFP QFN QFN
45
34
31
24(5)
Output
Driving
Default Function (AF0)
37
34
25
PB2
I/O
5V
4/8/12/16 mA PB2
50
38
35
26
PB3
I/O
5V
4/8/12/16 mA PB3
51
39
36
27
PB4
I/O
5V
4/8/12/16 mA PB4
52
40
37
28
4 Pin Assignment
49
PB5
I/O
5V
4/8/12/16 mA PB5
53
PC14
I/O
5V
4/8/12/16 mA PC14
54
PC15
I/O
5V
4/8/12/16 mA PC15
55
VDD_3
P
—
—
Voltage for VDD domain digital I/O
56
VSS_3
P
—
—
Ground reference for digital I/O
57
41
38
PC1
I/O
5V
4/8/12/16 mA PC1
58
42
39
PC2
I/O
5V
4/8/12/16 mA PC2
59
43
40
PC3
I/O
5V
4/8/12/16 mA PC3
60
44
41
PB6
I/O
5V
4/8/12/16 mA PB6
61
45
42
29
PB7
AI/O
5V
4/8/12/16 mA PB7
62
46
43
30
PB8
AI/O
5V
4/8/12/16 mA PB8
63
47
44
31
VDDA
P
—
—
Analog voltage for ADC and
comparators
64
48
45
32
VSSA
P
—
—
Ground reference for ADC and
comparators
Note: 1. I = input, O = output, A = Analog port, P = Power Supply, VDD = VDD Power, VDDIO = VDDIO Power.
2. 5V = 5 V operation I/O type, PU = Pull-up.
3. These pins are located at the VDD power domain.
4. In the Boot loader mode, the USART interface can be used for communication.
5. These pins are supplied by the VDD power for the 32-pin QFN package.
Rev. 1.00
35 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Table 6. HT32F53231/HT32F53241 Pin Description
Pin Number
I/O
(1)
48
46
32 Pin Name Type
Structure(2)
LQFP QFN QFN
Description
Output
Driving
Default Function (AF0)
46
1
PA0
AI/O
5V
4/8/12/16 mA PA0
2
1
2
PA1
AI/O
5V
4/8/12/16 mA PA1
3
2
3
PA2
AI/O
5V
4/8/12/16 mA PA2
4
3
4
PA3
AI/O
5V
4/8/12/16 mA PA3
5
4
5
PA4
AI/O
5V
4/8/12/16 mA
PA4, this pin provides a USART_TX
function in the Boot loader mode.
6
5
6
PA5
AI/O
5V
4/8/12/16 mA
PA5, this pin provides a USART_RX
function in the Boot loader mode.
PA6
AI/O
5V
4/8/12/16 mA PA6
7
8
PA7
AI/O
5V
4/8/12/16 mA PA7
9
6
7
PC4
I/O
5V
4/8/12/16 mA PC4
10
7
8
PC5
I/O
5V
4/8/12/16 mA PC5
11
8
PC6
I/O
5V
4/8/12/16 mA PC6
12
9
PC7
I/O
5V
4/8/12/16 mA PC7
13
10
9
CLDO
P
—
—
Core power LDO output
It must be connected a 2.2 μF capacitor
as close as possible between this pin
and VSS_1.
14
11
10
VDD_1
P
—
—
Voltage for VDD domain digital I/O
15
12
11
VSS_1
P
—
—
Ground reference for digital I/O
16
13
12
nRST(3)
I
5V_PU
—
External reset pin
17
14
PB9(3)
I/O
(VDD)
5V
4/8/12/16 mA PB9
18
15
13
PB10(3)
AI/O
(VDD)
5V
4/8/12/16 mA X32KIN
19
16
14
PB11(3)
AI/O
(VDD)
5V
4/8/12/16 mA X32KOUT
20
17
15
PB12(3)
I/O
(VDD)
5V
4/8/12/16 mA RTCOUT
21
18
16
PB13
AI/O
5V
4/8/12/16 mA XTALIN
22
19
17
PB14
AI/O
5V
4/8/12/16 mA XTALOUT
23
20
PB15
I/O
5V
4/8/12/16 mA PB15
24
21
PC0
I/O
5V
4/8/12/16 mA PC0
25
22
PA8
I/O
(VDDIO)
5V
4/8/12/16 mA PA8
26
23
PA9
I/O
(VDDIO)
5V_PU
27
24
PA10
I/O
(VDDIO)
5V
4/8/12/16 mA PA10
28
25
PA11
I/O
(VDDIO)
5V
4/8/12/16 mA PA11
Rev. 1.00
18(5)
4/8/12/16 mA PA9_BOOT
36 of 56
March 06, 2024
4 Pin Assignment
1
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Pin Number
48
46
32
LQFP QFN QFN
Pin Name Type(1)
I/O
Structure(2)
Description
Output
Driving
Default Function (AF0)
26
19(5)
PA12
I/O
(VDDIO)
5V_PU
4/8/12/16 mA SWCLK
30
27
20(5)
PA13
I/O
(VDDIO)
5V_PU
4/8/12/16 mA SWDIO
31
28
21(5)
PA14
I/O
(VDDIO)
5V
4/8/12/16 mA PA14
32
29
22(5)
PA15
I/O
(VDDIO)
5V
4/8/12/16 mA PA15
33
30
23(5)
PB0
I/O
(VDDIO)
5V
4/8/12/16 mA PB0
34
31
24(5)
PB1
I/O
(VDDIO)
5V
4/8/12/16 mA PB1
35
32
VDDIO
P
—
—
Voltage for digital VDDIO domain I/O
36
33
VSS_2
P
—
—
Ground reference for digital I/O
37
34
25
PB2
I/O
5V
4/8/12/16 mA PB2
38
35
26
PB3
I/O
5V
4/8/12/16 mA PB3
39
36
27
PB4
I/O
5V
4/8/12/16 mA PB4
40
37
28
PB5
I/O
5V
4/8/12/16 mA PB5
41
38
PC1
I/O
5V
4/8/12/16 mA PC1
42
39
PC2
I/O
5V
4/8/12/16 mA PC2
43
40
PC3
I/O
5V
4/8/12/16 mA PC3
44
41
PB6
I/O
5V
4/8/12/16 mA PB6
45
42
29
PB7
AI/O
5V
4/8/12/16 mA PB7
46
43
30
PB8
AI/O
5V
4/8/12/16 mA PB8
47
44
31
VDDA
P
—
—
Analog voltage for ADC
48
45
32
VSSA
P
—
—
Ground reference for ADC
4 Pin Assignment
29
Note: 1. I = input, O = output, A = Analog port, P = Power Supply, VDDIO = VDDIO Power, VDD = VDD Power.
2. 5V = 5 V operation I/O type, PU = Pull-up.
3. These pins are located at the VDD power domain.
4. In the Boot loader mode, the USART interface can be used for communication.
5. These pins are supplied by the VDD power for the 32-pin QFN package.
Rev. 1.00
37 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
5
Electrical Characteristics
Absolute Maximum Ratings
Table 7. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
VSS - 0.3
VSS + 5.5
V
VDD
External Main Supply Voltage
VDDIO
External I/O Supply Voltage
VSS - 0.3
VSS + 5.5
V
VDDA
External Analog Supply Voltage
VSSA - 0.3
VSSA + 5.5
V
VIN
Input Voltage on I/O
VSS - 0.3
VDD + 0.3
V
TA
Ambient Operating Temperature Range
-40
105
°C
TSTG
Storage Temperature Range
-60
150
°C
TJ
Maximum Junction Temperature
—
125
°C
PD
Total Power Dissipation
—
500
mW
VESD
Electrostatic Discharge Voltage - Human Body Mode
-4000
+4000
V
Recommended DC Operating Conditions
Table 8. Recommended DC Operating Conditions
Symbol
Parameter
TA = 25 °C, unless otherwise specified.
Conditions
Min.
Typ.
Max.
Unit
VDD
Operating Voltage
—
2.5
5.0
5.5
V
VDDIO
I/O Operating Voltage
—
1.8
5.0
5.5
V
VDDA
Analog Operating Voltage
—
2.5
5.0
5.5
V
On-Chip LDO Voltage Regulator Characteristics
Table 9. LDO Characteristics
Symbol
Parameter
TA = 25 °C, unless otherwise specified.
Conditions
VLDO
Internal Regulator Output
Voltage
VDD ≥ 2.5 V Regulator input @
ILDO = 25 mA and voltage variant =
±5 % after trimming
ILDO
Output Current
VDD = 2.5 V Regulator input @
VLDO = 1.5 V
CLDO
External Filter Capacitor Value The capacitor value is dependent on
for Internal Core Power Supply the core power current consumption
Rev. 1.00
38 of 56
Min.
Typ.
Max.
Unit
1.425
1.5
1.57
V
—
30
35
mA
1
2.2
—
μF
March 06, 2024
5 Electrical Characteristics
The following table shows the absolute maximum ratings of the device. These are stress ratings only.
Stresses beyond absolute maximum ratings may cause permanent damage to the device. Note that
the device is not guaranteed to operate properly at the maximum ratings. Exposure to the absolute
maximum rating conditions for extended periods may affect device reliability.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Power Consumption
Table 10. HT32F53242/HT32F53252 Power Consumption Characteristics
TA = 25 °C, unless otherwise specified.
Symbol
Parameter
Operating Current
(Sleep Mode)
Max. @ TA
25 °C 105 °C
VDD = 5 V
fHCLK =
HSI = 8 MHz
60 MHz
PLL = 60 MHz
All peripherals enabled 13.6
17.5
—
All peripherals disabled
6.6
7.6
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
40 MHz
PLL = 40 MHz
All peripherals enabled 11.3
14.0
—
All peripherals disabled
6.5
7.4
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
20 MHz
PLL = 40 MHz
All peripherals enabled
5.6
6.4
—
All peripherals disabled
3.0
3.3
—
All peripherals enabled
2.3
2.5
—
All peripherals disabled
1.3
1.3
—
fHCLK =
8 MHz
IDD
Typ.
VDD = 5 V
HSI = 8 MHz
PLL = off
VDD = 5 V
All peripherals enabled 38.00 47.44
fHCLK =
LSI = 32 kHz
32 kHz
LDO off, DMOS on All peripherals disabled 33.42 42.65
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
60 MHz
PLL = 60 MHz
All peripherals enabled
—
8.7
10.4
—
All peripherals disabled 0.79
0.88
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
40 MHz
PLL = 40 MHz
All peripherals enabled
6.0
6.9
—
All peripherals disabled 0.64
0.72
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
20 MHz
PLL = 40 MHz
All peripherals enabled 3.38
3.71
—
All peripherals disabled 0.55
0.62
—
All peripherals enabled 1.37
1.47
—
All peripherals disabled 0.22
0.25
—
VDD = 5 V
All peripherals enabled 33.96 43.23
fHCLK =
LSI = 32 kHz
32 kHz
LDO off, DMOS on All peripherals disabled 29.08 38.09
—
fHCLK =
8 MHz
VDD = 5 V
HSI = 8 MHz
PLL = off
—
Unit
mA
μA
mA
μA
Operating Current
(Deep-Sleep1 Mode)
—
VDD = 5 V, HSI/HSE/PLL clock off, LDO off,
28.93 37.94
DMOS on, LSE off, LSI on, RTC on
—
μA
Operating Current
(Deep-Sleep2 Mode)
—
VDD = 5 V, HSI/HSE/PLL clock off, LDO off
DMOS on, LSE off, LSI on, RTC on
—
μA
5.14
9.90
Note: 1. HSE means high speed external oscillator. HSI means 8 MHz high speed internal oscillator.
2. LSE means 32.768 kHz low speed external oscillator. LSI means 32 kHz low speed internal oscillator.
3. RTC means Real-Time clock.
4. Code = while (1) {208 NOP} executed in Flash.
Rev. 1.00
39 of 56
March 06, 2024
5 Electrical Characteristics
Operating Current
(Run Mode)
Conditions
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Table 11. HT32F53231/HT32F53241 Power Consumption Characteristics
TA = 25 °C, unless otherwise specified.
Symbol
Parameter
Operating Current
(Sleep Mode)
Max. @ TA
25 °C 105 °C
VDD = 5 V
fHCLK =
HSI = 8 MHz
60 MHz
PLL = 60 MHz
All peripherals enabled 11.8 12.91
—
All peripherals disabled 5.60
6.06
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
40 MHz
PLL = 40 MHz
All peripherals enabled 9.79 10.67
—
All peripherals disabled 5.60
6.07
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
20 MHz
PLL = 40 MHz
All peripherals enabled 4.85
5.23
—
All peripherals disabled 2.69
2.90
—
All peripherals enabled 1.95
2.10
—
All peripherals disabled 1.08
1.16
—
VDD = 5 V
All peripherals enabled 35.06 43.6
fHCLK =
LSI = 32 kHz
32 kHz
LDO off, DMOS on All peripherals disabled 31.4 39.7
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
60 MHz
PLL = 60 MHz
All peripherals enabled 7.41
8.05
—
All peripherals disabled 0.76
0.85
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
40 MHz
PLL = 40 MHz
All peripherals enabled 5.10
5.53
—
All peripherals disabled 0.62
0.70
—
VDD = 5 V
fHCLK =
HSI = 8 MHz
20 MHz
PLL = 40 MHz
All peripherals enabled 2.87
3.10
—
All peripherals disabled 0.55
0.62
—
All peripherals enabled 1.14
1.24
—
All peripherals disabled 0.22
0.24
—
VDD = 5 V
All peripherals enabled 31.72 40.02
fHCLK =
LSI = 32 kHz
32 kHz
LDO off, DMOS on All peripherals disabled 27.84 35.91
—
fHCLK =
8 MHz
IDD
Typ.
fHCLK =
8 MHz
VDD = 5 V
HSI = 8 MHz
PLL = off
VDD = 5 V
HSI = 8 MHz
PLL = off
—
—
Unit
mA
μA
mA
μA
Operating Current
(Deep-Sleep1 Mode)
—
VDD = 5 V, HSI/HSE/PLL clock off, LDO off,
DMOS on, LSE off, LSI on, RTC on
27.7 35.75
—
μA
Operating Current
(Deep-Sleep2 Mode)
—
VDD = 5 V, HSI/HSE/PLL clock off, LDO off
DMOS on, LSE off, LSI on, RTC on
3.99
—
μA
6.84
Note: 1. HSE means high speed external oscillator. HSI means 8 MHz high speed internal oscillator.
2. LSE means 32.768 kHz low speed external oscillator. LSI means 32 kHz low speed internal oscillator.
3. RTC means Real-Time clock.
4. Code = while (1) {208 NOP} executed in Flash.
Rev. 1.00
40 of 56
March 06, 2024
5 Electrical Characteristics
Operating Current
(Run Mode)
Conditions
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Reset and Supply Monitor Characteristics
Table 12. VDD Power Reset Characteristics
Symbol
Parameter
Conditions
Power On Reset Threshold
(Rising Voltage on VDD)
VPOR
TA = 25 °C, unless otherwise specified.
Power Down Reset Threshold
(Falling Voltage on VDD)
VPORHYST
POR Hysteresis
tPOR
Reset Delay Time
Typ.
Max.
Unit
2.22
2.35
2.48
V
2.12
2.2
2.33
V
—
150
—
mV
—
0.1
0.2
ms
TA = -40 °C ~ 105 °C
—
VDD = 5.0 V
Note: 1. Data based on characterization results only, not tested in production.
2. If the LDO is turned on, the VDD POR has to be in the de-assertion condition. When the VDD POR is in the
assertion state then the LDO will be turned off.
Table 13. LVD / BOD Characteristics
Symbol
Parameter
Voltage of Brown Out
Detection
VBOD
TA = 25 °C, unless otherwise specified.
Conditions
Min.
Typ.
Max.
Unit
After factory-trimmed, VDD Falling
edge
2.37
2.45
2.53
V
LVDS = 000
2.57
2.65
2.73
V
LVDS = 001
2.77
2.85
2.93
V
LVDS = 010
2.97
3.05
3.13
V
LVDS = 011
3.17
3.25
3.33
V
LVDS = 100
3.37
3.45
3,53
V
LVDS = 101
4.15
4.25
4.35
V
LVDS = 110
4.35
4.45
4.55
V
Voltage of Low Voltage
VDD Falling edge
Detection
VLVD
LVDS = 111
4.55
4.65
4.75
V
VLVDHTST
LVD Hysteresis
VDD = 5.0 V
—
—
100
—
mV
tsuLVD
LVD Setup Time
VDD = 5.0 V
—
—
—
5
μs
tatLVD
LVD Active Delay Time VDD = 5.0 V
—
—
—
—
ms
IDDLVD
Operation Current (2)
—
—
10
20
μA
VDD = 5.0 V
Note: 1. Data based on characterization results only, not tested in production.
2. Bandgap current is not included.
3. LVDS field is in the PWRCU LVDCSR register
External Clock Characteristics
Table 14. High Speed External Clock (HSE) Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
2.5
—
5.5
V
VDD = 2.5 V ~ 5.0 V
4
—
16
MHz
VDD = 5.0 V, RESR = 100 Ω
@ 16 MHz
—
—
12
pF
—
0.5
—
MΩ
VDD
Operation Voltage Range
TA = -40 °C ~ 105 °C
fHSE
HSE Frequency
CL
Load Capacitance
RFHSE
Internal Feedback Resistor between
VDD = 5.0 V
XTALIN and XTALOUT Pins
Rev. 1.00
TA = 25 °C, unless otherwise specified.
41 of 56
March 06, 2024
5 Electrical Characteristics
VPDR
Min.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Symbol
Parameter
RESR
Equivalent Series Resistance
DHSE
HSE Oscillator Duty Cycle
Min.
Typ.
Max.
Unit
—
—
110
Ω
%
VDD = 5.0 V, CL = 12 pF
@ 16 MHz, HSEGAIN = 0
VDD = 2.5 V, CL = 12 pF
@ 16 MHz, HSEGAIN = 1
—
40
—
60
VDD = 5.0 V, RESR = 100 Ω,
CL = 12 pF @ 8 MHz,
HSEGAIN = 0
—
0.85
—
VDD = 5.0 V, RESR = 25 Ω,
CL = 12 pF @ 16 MHz,
HSEGAIN = 1
—
3.0
—
mA
IPWDHSE
HSE Oscillator Power Down Current VDD = 5.0 V
—
—
0.01
μA
tSUHSE
HSE Oscillator Startup Time
—
—
4
ms
VDD = 5.0 V
Table 15. Low Speed External Clock (LSE) Characteristics
Symbol
Parameter
Conditions
TA = 25 °C, unless otherwise specified.
Min.
Typ.
Max.
Unit
VDD
Operation Voltage Range
TA = -40 °C ~ 105 °C
2.5
—
5.5
V
fLSE
LSE Frequency
VDD = 2.5 V ~ 5.5 V
—
32.768
—
kHz
RF
Internal Feedback Resistor
—
10
—
MΩ
RESR
Equivalent Series Resistance
VDD = 5.0 V
30
—
TBD
kΩ
CL
Recommended Load Capacitances VDD = 5.0 V
6
—
TBD
pF
IDDLSE
Oscillator Supply Current
(High Current Mode)
fCK_LSE = 32.768 kHz,
RESR = 50 kΩ, CL ≥ 7 pF
VDD = 2.5 V ~ 5.5 V
TA = -40 °C ~ +105 °C
—
3.3
6.3
μA
Oscillator Supply Current
(Low Current Mode)
fCK_LSE = 32.768 kHz,
RESR = 50 kΩ, CL < 7 pF
VDD = 2.5 V ~ 5.5 V
TA = -40 °C ~ +105 °C
—
1.8
3.3
μA
—
—
—
0.01
μA
500
—
—
ms
Power Down Current
LSE Oscillator Startup Time
(Low Current Mode)
tSULSE
—
fCK_LSE = 32.768 kHz,
VDD = 2.5 V ~ 5.5 V
Note: The following guidelines are recommended to increase the stability of the crystal circuit of the HSE / LSE
clock in the PCB layout.
1. The crystal oscillator should be located as close as possible to the MCU to keep the trace length as short
as possible to reduce any parasitic capacitance.
2. Shield lines in the vicinity of the crystal by using a ground plane to isolate signals and reduce noise.
3. Keep any high frequency signal lines away from the crystal area to prevent the crosstalk adverse effects.
Rev. 1.00
42 of 56
March 06, 2024
5 Electrical Characteristics
IDDHSE
HSE Oscillator Current Consumption
Conditions
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Internal Clock Characteristics
Table 16. High Speed Internal Clock (HSI) Characteristics
Symbol
Typ.
Max.
Unit
Operation Voltage Range
TA = -40 °C ~ 105 °C
2.5
—
5.5
V
fHSI
HSI Frequency
VDD = 5 V @ 25 °C
—
8
—
MHz
VDD = 5.0 V
TA = 25 °C
-1
—
1
%
VDD = 2.5 V ~ 5.5 V
TA = -20 °C ~ 60 °C
-1.5
—
2
%
VDD = 2.5 V ~ 5.5 V
TA = -40 °C ~ 105 °C
-3
—
3
%
fHSI = 8 MHz
35
—
65
%
fHSI = 8 MHz @
HSI Oscillator Power Down Current VDD = 2.5 V ~ 5.5 V
—
—
140
μA
—
—
0.01
μA
HSI Oscillator Startup Time
—
—
20
μs
Duty
IDDHSI
TSUHSI
Conditions
Factory Calibrated HSI Oscillator
Frequency Accuracy
HSI Oscillator Duty Cycle
HSI Oscillator Operating Current
fHSI = 8 MHz
Note: Data based on characterization results only, not tested in production.
Table 17. Low Speed Internal Clock (LSI) Characteristics
Symbol
Parameter
TA = 25 °C, unless otherwise specified.
Min.
Typ.
Max.
Unit
VDD
Operation Voltage Range
TA = -40 °C ~105 °C
Conditions
2.5
—
5.5
V
fLSI
LSI Frequency
VDD = 5.0 V,
TA = -40 °C ~ 105 °C
21
32
43
kHz
ACCLSI
LSI Frequency Accuracy
VDD = 5.0 V, with factory-trimmed
-10
—
+10
%
IDDLSI
LSI Oscillator Operating Current VDD = 5.0 V
—
0.5
0.8
μA
tSULSI
LSI Oscillator Startup Time
—
—
100
μs
VDD = 5.0 V
Note: Data based on characterization results only, not tested in production.
System PLL Characteristics
Table 18. System PLL Characteristics
Symbol
Parameter
TA = 25 °C, unless otherwise specified.
Conditions
Min.
Typ.
Max.
Unit
fPLLIN
System PLL Input Clock
—
4
—
16
MHz
fCK_PLL
System PLL Output Clock
—
4
—
60
MHz
tLOCK
System PLL Lock Time
—
—
200
—
μs
Memory Characteristics
Table 19. Flash Memory Characteristics
Symbol
Min.
Typ.
Max.
Unit
NENDU
Number of Guaranteed Program/Erase
TA = -40 °C ~ 105 °C
Cycles before failure (Endurance)
20
—
—
K cycles
tRET
Data Retention Time
TA = -40 °C ~ 105 °C
10
—
—
Years
tPROG
Word Programming Time
TA = -40 °C ~ 105 °C
20
—
—
μs
Rev. 1.00
Parameter
TA = 25 °C, unless otherwise specified.
Conditions
43 of 56
March 06, 2024
5 Electrical Characteristics
Min.
VDD
ACCHSI
Parameter
TA = 25 °C, unless otherwise specified.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
tERASE
Page Erase Time
TA = -40 °C ~ 105 °C
2
—
—
ms
tMERASE
Mass Erase Time
TA = -40 °C ~ 105 °C
10
—
—
ms
I/O Port Characteristics
Table 20. I/O Port Characteristics
Parameter
IIL
Low Level Input Current
IIH
High Level Input Current
VIL
VIH
VHYS
IOL
IOH
VOL
Conditions
Min.
Typ.
Max.
Unit
VI = VSS, On-chip pull-up
resister disabled
—
—
3
μA
—
—
3
μA
VI = VDD, On-chip pull-down
resister disabled
—
—
3
μA
—
—
3
μA
5.0 V I/O
- 0.5
—
VDD ×
0.35
V
Reset pin
- 0.5
—
VDD ×
0.35
V
5.0 V I/O
VDD ×
0.65
—
VDD +
0.5
V
Reset pin
VDD ×
0.65
—
VDD +
0.5
V
5.0 V I/O
—
0.12 ×
VDD
—
mV
Reset pin
—
0.12 ×
VDD
—
mV
5.0 V I/O 4 mA drive, VOL = 0.6 V
4
—
—
mA
5.0 V I/O
Reset pin
5.0 V I/O
Reset pin
Low Level Input Voltage
High Level Input Voltage
Schmitt Trigger Input
Voltage Hysteresis
Low Level Output Current 5.0 V I/O 8 mA drive, VOL = 0.6 V
(GPIO Sink Current)
5.0 V I/O 12 mA drive, VOL = 0.6 V
8
—
—
mA
12
—
—
mA
5.0 V I/O 16 mA drive, VOL = 0.6 V
16
—
—
mA
5.0 V I/O 4 mA drive, VOH = VDD - 0.6 V
—
4
—
mA
High Level Output Current 5.0 V I/O 8 mA drive, VOH = VDD - 0.6 V
(GPIO Source Current)
5.0 V I/O 12 mA drive, VOH = VDD - 0.6 V
—
8
—
mA
—
12
—
mA
5.0 V I/O 16 mA drive, VOH = VDD - 0.6 V
—
16
—
mA
5.0 V 4 mA drive I/O, IOL = 4 mA
—
—
0.6
V
5.0 V 8 mA drive I/O, IOL = 8 mA
—
—
0.6
V
5.0 V 12 mA drive I/O, IOL = 12 mA
—
—
0.6
V
Low Level Output Voltage
5.0 V 16 mA drive I/O, IOL = 16 mA
VOH
High Level Output Voltage
RPU
Internal Pull-up Resistor
RPD
Internal Pull-down Resistor
Rev. 1.00
—
—
0.6
V
5.0 V 4 mA drive I/O, IOH = 4 mA
VDD - 0.6
—
—
V
5.0 V 8 mA drive I/O, IOH = 8 mA
VDD - 0.6
—
—
V
5.0 V 12 mA drive I/O, IOH = 12 mA
VDD - 0.6
—
—
V
5.0 V 16 mA drive I/O, IOH = 16 mA
VDD - 0.6
—
—
V
VDD = 5.0 V
—
50
—
VDD = 3.3 V
—
76
—
VDD = 5.0 V
—
50
—
VDD = 3.3 V
—
76
—
44 of 56
kΩ
kΩ
March 06, 2024
5 Electrical Characteristics
Symbol
TA = 25 °C, unless otherwise specified.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
ADC Characteristics
Table 21. ADC Characteristics
Symbol
TA = 25 °C, unless otherwise specified.
Min.
Typ.
Max.
Unit
A/D Converter Operating Voltage
Parameter
—
2.5
5.0
5.5
V
VADCIN
A/D Converter Input Voltage Range
—
0
—
VREF+
V
VREF+
A/D Converter Reference Voltage
—
—
VDDA
VDDA
V
IADC
A/D Converter Current Consumption VDDA = 5.0 V
—
1.4
1.5
mA
IADC_DN
A/D Converter Power Down Current
VDDA = 5.0 V
Consumption
—
—
0.1
μA
fADC
A/D Converter Clock Frequency
—
0.7
—
32
MHz
fS
Sampling Rate
—
0.05
—
2
Msps
tDL
Data Latency
—
—
12.5
—
1/fADC
Cycles
tS&H
Sampling & Hold Time
—
—
3.5
—
1/fADC
Cycles
tADCCONV
A/D Converter Conversion Time
—
16
—
1/fADC
Cycles
ADST[7:0] = 2
RI
Input Sampling Switch Resistance
CI
Input Sampling Capacitance
—
—
—
1
kΩ
No pin/pad capacitance included
—
4
—
pF
tSU
Startup Time
—
—
—
1
μs
N
Resolution
INL
Integral Non-linearity Error
fS = 1.875 Msps, VDDA = 5.0 V
—
—
12
—
bits
—
±2
±5
LSB
DNL
Differential Non-linearity Error
fS = 1.875 Msps, VDDA = 5.0 V
—
±1
—
LSB
EO
Offset Error
EG
Gain Error
—
—
—
±10
LSB
—
—
—
±10
LSB
Note: 1. Data based on characterization results only, not tested in production.
2. The figure below shows the equivalent circuit of the A/D Converter Sample-and-Hold input stage where CI
is the storage capacitor, RI is the resistance of the sampling switch and RS is the output impedance of the
signal source VS. Normally the sampling phase duration is approximately, 3.5/fADC. The capacitance, CI,
must be charged within this time frame and it must be ensured that the voltage at its terminals becomes
sufficiently close to VS for accuracy. To guarantee this, RS is not allowed to have an arbitrarily large value.
SAR ADC
sample
RS
CI
VS
RI
Figure 12. ADC Sampling Network Model
Rev. 1.00
45 of 56
March 06, 2024
5 Electrical Characteristics
Conditions
VDDA
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
The worst case occurs when the extremities of the input range (0 V and V REF) are sampled
consecutively. In this situation a sampling error below 1/4 LSB is ensured by using the following
equation:
RS <
3.5
− RI
fADCCIln(2N+2)
If, in a system where the A/D Converter is used, there are no rail-to-rail input voltage variations
between consecutive sampling phases, RS may be larger than the value indicated by the equation
above.
Internal Reference Voltage Characteristics
Table 22. Internal Reference Voltage Characteristics
Symbol
Parameter
VDDA
Conditions
Min.
Typ.
Max.
Unit
—
2.8
—
5.5
V
VDDA ≥ 2.8 V VREFSEL[1:0] = 00
2.47
2.5
2.53
VDDA ≥ 3.3 V VREFSEL[1:0] = 01
2.97
3.0
3.03
VDDA ≥ 4.3 V VREFSEL[1:0] = 10
3.96
4.0
4.04
VDDA ≥ 4.8 V VREFSEL[1:0] = 11
4.45
4.5
4.54
VDDA = 2.8 V ~ 5.5 V, VREF = 2.5 V,
TA = -40 °C ~ 85 °C
-3.0
—
2.5
VDDA = 2.8 V ~ 5.5 V, VREF = 2.5 V,
TA = -40 °C ~ 105 °C
-4.5
—
2.5
Operating Voltage
Internal Reference Voltage after
Factory Trimming @ TA = 25 °C
VREF
Reference Voltage Accuracy
after Trimming
ACCVREF
TA = 25 °C, unless otherwise specified.
V
%
tSTABLE
Reference Voltage Stable Time
—
—
—
100
ms
tSREFV
ADC Sampling Time when
Reading Reference Voltage
—
10
—
—
µs
IDD
Operating Current
—
—
50
70
µA
IDDPWD
Power Down Current
—
—
—
0.01
µA
Note: 1. Data based on characterization results only, not tested in production.
2. The trimming bits of the internal reference voltage are 7-bit resolution.
Comparator Characteristics
Table 23. Comparator Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
2.5
—
5.5
V
VSSA
—
VDDA
V
TA = 25 °C
-5
—
5
mV
No hysteresis, CMPHM [1:0] = 00
—
0
—
mV
Low hysteresis, CMPHM [1:0] = 01
—
50
—
mV
Middle hysteresis, CMPHM [1:0] = 10
—
100
—
mV
High hysteresis, CMPHM [1:0] = 11
—
150
—
mV
VDDA
Operating Voltage
VIN
Input Common Mode VoltCP or CN
age Range
VIOS
Input Offset Voltage(1)
VHYS
Input Hysteresis
VDDA = 5.0 V
Rev. 1.00
TA = 25 °C, unless otherwise specified.
Comparator mode
46 of 56
March 06, 2024
5 Electrical Characteristics
Where fADC is the ADC clock frequency and N is the ADC resolution (N = 12 in this case). A safe
margin should be considered due to the pin/pad parasitic capacitances, which are not accounted for
in this simple model.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Symbol
Parameter
Conditions
High Speed Mode
Response Time
Input Overdrive = ±100 mV
Low Speed Mode
tRT
Min.
Typ.
Max.
Unit
VDDA ≥ 3.6 V
—
50
100
VDDA < 3.6 V
—
100
250
—
2
5
µs
ns
Current Consumption
VDDA = 5.0 V
High Speed Mode
—
100
—
µA
Low Speed Mode
—
15
—
µA
tCMPST
Comparator Startup Time
Comparator enabled to output valid
—
—
50
µs
ICMP_DN
Comparator Power Down
Supply Current
CMPEN = 0
CVREN = 0
CVROE = 0
—
—
0.1
µA
Comparator Voltage Reference (CVR)
VCVR
Output Voltage Range
—
VSSA
—
VDDA
V
NBits
CVR Scaler Resolution
—
—
8
—
bits
VDDA = 5 V, CVROE = 1,
CLOAD ≤ 100 pF, RLOAD ≥ 50 kΩ,
CVR Scaler Setting Time from
CVRVAL = “00000000” to “11111111”
—
—
250
µs
CVREN = 1, CVROE = 0
—
100
—
µA
CVREN = 1, CVROE = 1
—
125
150
µA
tCVRST
Setting Time
ICVR
Current Consumption
VDDA = 5.0 V
Note: Data based on characterization results only, not tested in production.
GPTM / MCTM / PWM Characteristics
Table 24. GPTM / MCTM / PWM Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
fTM
Timer Clock Source for GPTM, MCTM, PWM
—
—
—
fPCLK
MHz
tRES
Timer Resolution Time
—
1
—
—
1/fTM
fEXT
External Signal Frequency on Channel 0 ~ 3
—
—
—
1/2
fTM
RES
Timer Resolution
—
—
—
16
bits
I2C Characteristics
Table 25. I2C Characteristics
Symbol
Standard Mode
Parameter
Min.
Max.
Fast Mode
Min.
Max.
Fast Plus Mode
Min.
Max.
Unit
fSCL
SCL Clock Frequency
—
100
—
400
—
1000
kHz
tSCL(H)
SCL Clock High Time
4.5
—
1.125
—
0.45
—
μs
tSCL(L)
SCL Clock Low Time
4.5
—
1.125
—
0.45
—
μs
tFALL
SCL and SDA Fall Time
—
1.3
—
0.34
—
0.135
μs
tRISE
SCL and SDA Rise Time
—
1.3
—
0.34
—
0.135
μs
tSU(SDA)
SDA Data Setup Time
500
—
125
—
50
—
ns
0
—
0
—
0
—
ns
SDA Data Hold Time (6)
—
1.6
—
0.475
—
0.25
μs
tVD(SDA)
SDA Data Valid Time
—
1.6
—
0.475
—
0.25
μs
tSU(STA)
START Condition Setup Time
500
—
125
—
50
—
ns
tH(SDA)
Rev. 1.00
SDA Data Hold Time
(5)
47 of 56
March 06, 2024
5 Electrical Characteristics
ICMP
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Symbol
Standard Mode
Parameter
Fast Mode
Fast Plus Mode
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tH(STA)
START Condition Hold Time
0
—
0
—
0
—
ns
tSU(STO)
STOP Condition Setup Time
500
—
125
—
50
—
ns
Note: 1. Data based on design, not tested in production.
2. To achieve 100 kHz standard mode, the peripheral clock frequency must be higher than 2 MHz.
4. To achieve 1 MHz fast plus mode, the peripheral clock frequency must be higher than 20 MHz.
5. The above characteristic parameters of the I2C bus timing are based on: COMBFILTEREN = 0 and SEQFILTER = 00.
6. The above characteristic parameters of the I2C bus timing are based on: COMBFILTEREN = 1 and SEQFILTER = 00.
tFALL
tRISE
SCL
tSCL(L)
tH(STA)
SDA
tSCL(H)
tVD(SDA)
tH(SDA)
tSU(STO)
tSU(SDA)
tSU(STA)
Figure 13. I2C Timing Diagram
SPI Characteristics
Table 26. SPI Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Master mode
SPI peripheral clock frequency fPCLK
—
—
fPCLK/2
MHz
SPI Master Mode
fSCK
SPI Master Output SCK
Clock Frequency
tSCK(H)
tSCK(L)
SCK Clock High and Low
Time
—
tSCK/2
-2
—
tSCK/2
+1
ns
tV(MO)
Data Output Valid Time
—
—
—
5
ns
tH(MO)
Data Output Hold Time
—
2
—
—
ns
tSU(MI)
Data Input Setup Time
—
5
—
—
ns
tH(MI)
Data Input Hold Time
—
5
—
—
ns
SPI Slave Mode
fSCK
SPI Slave Input SCK Clock Slave mode
Frequency
SPI peripheral clock frequency fPCLK
—
—
fPCLK/3
MHz
DutySCK
SPI Slave Input SCK Clock
Duty Cycle
—
30
—
70
%
tSU(SEL)
SEL Enable Setup Time
—
3 tPCLK
—
—
ns
tH(SEL)
SEL Enable Hold Time
—
2 tPCLK
—
—
ns
tA(SO)
Data Output Access Time
—
—
—
3 tPCLK
ns
Rev. 1.00
48 of 56
March 06, 2024
5 Electrical Characteristics
3. To achieve 400 kHz fast mode, the peripheral clock frequency must be higher than 8 MHz.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
tDIS(SO)
Data Output Disable Time
—
—
—
10
ns
tV(SO)
Data Output Valid Time
—
—
—
25
ns
tH(SO)
Data Output Hold Time
—
15
—
—
ns
tSU(SI)
Data Input Setup Time
—
5
—
—
ns
tH(SI)
Data Input Hold Time
—
4
—
—
ns
5 Electrical Characteristics
Note: 1. fSCK is SPI output/input clock frequency and tSCK = 1/fSCK.
2. fPCLK is SPI peripheral clock frequency and tPCLK = 1/fPCLK.
tSCK
SCK
(CPOL=0)
tSCK(H)
tSCK(L)
SCK
(CPOL=1)
tH(MO)
tV(MO)
DATA VALID
MOSI
tSU(MI)
DATA VALID
CPHA=1
tH(MI)
DATA VALID
MISO
DATA VALID
DATA VALID
tSU(MI)
MISO
DATA VALID
tH(MO)
tV(MO)
MOSI
DATA VALID
DATA VALID
DATA VALID
tH(MI)
DATA VALID
CPHA=0
DATA VALID
DATA VALID
Figure 14. SPI Timing Diagram – SPI Master Mode
Rev. 1.00
49 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
SEL
tSU(SEL)
tH(SEL)
tSCK
SCK
(CPOL=0)
tSCK(L)
SCK
(CPOL=1)
tSU(SI)
MSB/LSB IN
MOSI
tA(SO)
MISO
tH(SI)
tV(SO)
LSB/MSB IN
tH(SO)
MSB/LSB OUT
tDIS(SO)
LSB/MSB OUT
Figure 15. SPI Timing Diagram – SPI Slave Mode with CPHA = 1
Rev. 1.00
50 of 56
March 06, 2024
5 Electrical Characteristics
tSCK(H)
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
6
Package Information
Note that the package information provided here is for consultation purposes only. As this
information may be updated at regular intervals users are reminded to consult the Holtek website for
the latest version of the Package/Carton Information.
● Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
● The Operation Instruction of Packing Materials
● Carton information
Rev. 1.00
51 of 56
March 06, 2024
6 Package Information
Additional supplementary information with regard to packaging is listed below. Click on the
relevant section to be transferred to the relevant website page.
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
SAW Type 32-pin QFN (4mm × 4mm × 0.75mm) Outline Dimensions
D2
32
b
25
17
8
e
E
E2
1
16
A1
A3
D
L
9
K
A
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.028
0.030
0.031
A1
0.000
0.001
0.002
A3
b
0.008 REF
0.006
0.008
D
0.157 BSC
E
0.157 BSC
e
0.016 BSC
D2
0.100
—
0.108
E2
0.100
—
0.108
L
0.014
0.016
0.018
K
0.008
—
—
Symbol
Dimensions in mm
Min.
Nom.
Max.
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
b
Rev. 1.00
0.010
0.203 REF
0.15
0.20
D
4.00 BSC
E
4.00 BSC
e
0.40 BSC
0.25
D2
2.55
—
2.75
E2
2.55
—
2.75
L
0.35
0.40
0.45
K
0.20
—
—
52 of 56
March 06, 2024
6 Package Information
24
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
SAW Type 46-pin QFN (6.5mm × 4.5mm × 0.75mm) Outline Dimensions
D2
33
b
46
24
9
e
E
E2
1
23
A1
A3
D
L
10
K
A
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
0.028
0.030
0.031
A1
0.000
0.001
0.002
A3
b
0.008 REF
0.006
0.008
D
0.256 BSC
E
0.177 BSC
e
0.016 BSC
D2
0.197
—
0.205
E2
0.118
—
0.126
L
0.014
0.016
0.018
K
0.008
—
—
Symbol
Dimensions in mm
Min.
Nom.
Max.
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
b
0.203 REF
0.15
0.20
D
6.50 BSC
E
4.50 BSC
e
Rev. 1.00
0.010
0.25
0.40 BSC
D2
5.00
—
5.20
E2
3.00
—
3.20
L
0.35
0.40
0.45
K
0.20
—
—
53 of 56
March 06, 2024
6 Package Information
32
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
48-pin LQFP (7mm × 7mm) Outline Dimensions
6 Package Information
Symbol
Dimensions in inch
Min.
Nom.
A
0.354 BSC
B
0.276 BSC
C
0.354 BSC
D
0.276 BSC
E
0.020 BSC
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Rev. 1.00
Max.
Dimensions in mm
Min.
Nom.
A
9.00 BSC
B
7.00 BSC
C
9.00 BSC
D
7.00 BSC
E
0.50 BSC
Max.
F
0.17
0.22
0.27
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
54 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
64-pin LQFP (7mm × 7mm) Outline Dimensions
6 Package Information
Symbol
Dimensions in inch
Min.
Nom.
A
0.354 BSC
B
0.276 BSC
C
0.354 BSC
D
0.276 BSC
E
0.016 BSC
F
0.005
0.007
0.009
G
0.053
0.055
0.057
H
—
—
0.063
I
0.002
—
0.006
J
0.018
0.024
0.030
K
0.004
—
0.008
α
0°
—
7°
Symbol
Dimensions in mm
Min.
Nom.
A
9.00 BSC
B
7.00 BSC
C
9.00 BSC
D
7.00 BSC
E
Rev. 1.00
Max.
Max.
0.40 BSC
F
0.13
0.18
0.23
G
1.35
1.40
1.45
H
—
—
1.60
I
0.05
—
0.15
J
0.45
0.60
0.75
K
0.09
—
0.20
α
0°
—
7°
55 of 56
March 06, 2024
32-Bit Arm® Cortex®-M0+ 5V CAN MCU
HT32F53231/HT32F53241/HT32F53242/HT32F53252
6 Package Information
Copyright© 2024 by HOLTEK SEMICONDUCTOR INC. All Rights Reserved.
The information provided in this document has been produced with reasonable care and attention
before publication, however, HOLTEK does not guarantee that the information is completely
accurate. The information contained in this publication is provided for reference only and may
be superseded by updates. HOLTEK disclaims any expressed, implied or statutory warranties,
including but not limited to suitability for commercialization, satisfactory quality, specifications,
characteristics, functions, fitness for a particular purpose, and non-infringement of any thirdparty’s rights. HOLTEK disclaims all liability arising from the information and its application. In
addition, HOLTEK does not recommend the use of HOLTEK’s products where there is a risk of
personal hazard due to malfunction or other reasons. HOLTEK hereby declares that it does not
authorise the use of these products in life-saving, life-sustaining or safety critical components.
Any use of HOLTEK’s products in life-saving/sustaining or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and hold HOLTEK harmless from
any damages, claims, suits, or expenses resulting from such use. The information provided in
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trademarks, is the intellectual property of HOLTEK (and its licensors, where applicable) and is
protected by copyright law and other intellectual property laws. No license, express or implied,
to any intellectual property right, is granted by HOLTEK herein. HOLTEK reserves the right to
revise the information described in the document at any time without prior notice. For the latest
information, please contact us.
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March 06, 2024
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