HT9170D-18SOPLF

HT9170B/HT9170D DTMF Receiver Features · Operating voltage: 2.5V~5.5V · Tristate data output for MCU interface · Minimal external components · 3.58MHz crystal or ceramic resonator · No external filter is required · 1633Hz can be inhibited by the INH pin · Low standby current (on power down mode) · HT9170B: 18-pin DIP package HT9170D: 18-pin SOP package · Excellent performance General Description The HT9170B/D are Dual Tone Multi Frequency (DTMF) receivers integrated with digital decoder and bandsplit filter functions as well as power-down mode and inhibit mode operations. Such devices use digital counting techniques to detect and decode all the 16 DTMF tone pairs into a 4-bit code output. Highly accurate switched capacitor filters are implemented to divide tone signals into low and high group signals. A built-in dial tone rejection circuit is provided to eliminate the need for pre-filtering. Selection Table Function Operating Voltage OSC Frequency Tristate Data Output Power Down 1633Hz Inhibit DV DVB Part No. HT9170B 2.5V~5.5V 3.58MHz Ö Ö Ö Ö ¾ 18 DIP HT9170D 2.5V~5.5V 3.58MHz Ö Ö Ö Ö ¾ 18 SOP Package Block Diagram P W D N V R E F B ia s C ir c u it V re f G e n e ra to r R T /G T E S T D V D V B X 2 X 1 V P V N G S 3 .5 8 M H z C ry s ta l O s c illa to r S te e r in g C o n tr o l C ir c u it L o w G ro u p F ilte r O P A F re q u e n c y P r e - F ilte r D e te c to r H ig h G r o u p F ilte r C o d e D e te c to r D 0 D 1 D 2 D 3 IN H Rev. 1.11 L a tc h & O u tp u t B u ffe r 1 O E February 23, 2009 HT9170B/HT9170D Pin Assignment V P 1 1 8 V D D V P 1 1 8 V D D V N 2 1 7 R T /G T V N 2 1 7 R T /G T G S 3 1 6 E S T G S 3 1 6 E S T V R E F 4 1 5 D V V R E F 4 1 5 D V IN H 5 1 4 D 3 IN H 5 1 4 D 3 P W D N 6 1 3 D 2 P W D N 6 1 3 D 2 X 1 7 1 2 D 1 X 1 7 1 2 D 1 X 2 8 1 1 D 0 X 2 8 1 1 D 0 V S S 9 1 0 O E V S S 9 1 0 O E H T 9 1 7 0 B 1 8 D IP -A H T 9 1 7 0 D 1 8 S O P -A Pin Description Pin Name VP I/O Internal Connection I Operational Amplifier Description Operational amplifier non-inverting input VN I Operational amplifier inverting input GS O Operational amplifier output terminal VREEF O X1 I X2 O PWDN VREF Reference voltage output, normally VDD/2 oscillator The system oscillator consists of an inverter, a bias resistor and the necessary load capacitor on chip. A standard 3.579545MHz crystal connected to X1 and X2 terminals implements the oscillator function. I CMOS IN Pull-low Active high. This enables the device to go into power down mode and inhibits the oscillator. This pin input is internally pulled down. INH I CMOS IN Pull-low Logic high. This inhibits the detection of tones representing characters A, B, C and D. This pin input is internally pulled down. VSS ¾ ¾ OE I CMOS IN Pull-high D0~D3 O CMOS OUT Tristate Receiving data output terminals OE=²H²: Output enable OE=²L²: High impedance DV O CMOS OUT Data valid output When the chip receives a valid tone (DTMF) signal, the DV goes high; otherwise it remains low. EST O CMOS OUT Early steering output (see Functional Description) RT/GT I/O CMOS IN/OUT VDD ¾ ¾ Rev. 1.11 Negative power supply, ground D0~D3 output enable, high active Tone acquisition time and release time can be set through connection with external resistor and capacitor. Positive power supply, 2.5V~5.5V for normal operation 2 February 23, 2009 HT9170B/HT9170D Approximate internal connection circuits O P E R A T IO N A L A M P L IF IE R V R E F C M O S IN P u ll- h ig h O S C IL L A T O R X 1 V O P A V + V N V P C M O S O U T T r is ta te X 2 E N O P A G S 1 0 M 2 0 p F C M O S IN P u ll- lo w C M O S IN /O U T C M O S O U T 1 0 p F Absolute Maximum Ratings Supply Voltage ............................................-0.3V to 6V Storage Temperature ............................-50°C to 125°C Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-20°C to 75°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25°C Test Conditions VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage ¾ ¾ 2.5 5 5.5 V IDD Operating Current 5V ¾ ¾ 3.0 7 mA ISTB Standby Current 5V PWDN=5V ¾ 10 25 mA VIL ²Low² Input Voltage 5V ¾ ¾ ¾ 1.0 V VIH ²High² Input Voltage 5V ¾ 4.0 ¾ ¾ V IIL ²Low² Input Current 5V VVP=VVN=0V ¾ ¾ 0.1 mA IIH ²High² Input Current 5V VVP=VVN=5V ¾ ¾ 0.1 mA ROE Pull-high Resistance (OE) 5V VOE=0V 60 100 150 kW RIN Input Impedance (VN, VP) 5V ¾ ¾ 10 ¾ MW IOH Source Current (D0~D3, EST, DV) 5V VOUT =4.5V -0.4 -0.8 ¾ mA IOL Sink Current (D0~D3, EST, DV) 5V VOUT =0.5V fOSC System Frequency 5V Crystal=3.5795MHz Rev. 1.11 3 1.0 2.5 ¾ mA 3.5759 3.5795 3.5831 MHz February 23, 2009 HT9170B/HT9170D A.C. Characteristics Symbol Parameter fOSC=3.5795MHz, Ta=25°C Test Conditions Min. Typ. Max. 3V -36 ¾ -6 5V -29 ¾ 1 Twist Accept Limit (Positive) 5V ¾ 10 ¾ dB Twist Accept Limit (Negative) 5V ¾ 10 ¾ dB Dial Tone Tolerance 5V ¾ 18 ¾ dB Noise Tolerance 5V ¾ -12 ¾ dB Third Tone Tolerance 5V ¾ -16 ¾ dB Frequency Deviation Acceptance 5V ¾ ¾ ±1.5 % Frequency Deviation Rejection 5V ±3.5 ¾ ¾ % Power Up Time (See Figure 4.) 5V ¾ 30 ¾ ms ¾ 10 ¾ MW ¾ 0.1 ¾ mA ¾ ±25 ¾ mV ¾ 60 ¾ dB ¾ 60 ¾ dB ¾ 65 ¾ dB ¾ 1.5 ¾ MHz ¾ 4.5 ¾ VPP Conditions VDD Unit DTMF Signal Input Signal Level tPU dBm Gain Setting Amplifier RIN Input Resistance 5V IIN Input Leakage Current 5V VOS Offset Voltage 5V PSRR Power Supply Rejection 5V ¾ VSS