HI-1568CDM

HI-1567, HI-1568 March 2001 DESCRIPTION The HI-1567 and HI-1568 are low power CMOS dual transceivers designed to meet the requirements of MIL-STD-1553 /1760 specifications. PIN CONFIGURATIONS VDDA 1 20 TXA 19 TXA 18 TXINHA 17 RXA 16 RXA 15 TXB 14 TXB 13 TXINHB 12 RXB 11 RXB The transmitter section of each channel takes complimentary CMOS / TTL digital input data and converts it to bi-phase Manchester encoded 1553 signals suitable for driving the bus isolation transformer. Separate transmitter inhibit control signals are provided for each transmitter. The receiver section of the each channel converts the 1553 bus bi-phase data to complimentary CMOS / TTL data suitable for inputting to a Manchester decoder. Each receiver has a separate enable input which can be used to force the output of the receiver to a logic 0 (HI-1567) or logic 1 (HI-1568). To minimize the package size for this function, the transmitter outputs are internally connected to the receiver inputs, so that only two pins are required for connection to each coupling transformer. For designs requiring independent access to transmitter and receiver 1553 signals, please contact your Holt Sales representative. BUSA 2 BUSA 3 RXENA 4 GNDA 5 VDDB 6 BUSB 7 BUSB 8 RXENB 9 GNDB 10 20 Pin Ceramic DIP package FEATURES VDDA BUSA BUSA RXENA GNDA VDDB BUSB BUSB RXENB GNDB 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 TXA TXA TXINHA RXA RXA TXB TXB TXINHB RXB RXB ! Compliant to MIL-STD-1553A & B, MIL-STD-1760 ! CMOS technology for low standby power ! Smallest footprint available in 20 pin plastic ESOIC (thermally enhanced SOIC) package ! Less than 1.0W maximum power dissipation ! Available in DIP, Flatpack and small outline (ESOIC) package options 20 Pin Plastic ESOIC - WB package ! Military processing options ! Industry standard pin configurations (DS1567 Rev. B) HOLT INTEGRATED CIRCUITS 1 03/01 HI-1567, HI-1568 PIN DESCRIPTIONS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 15 SYMBOL VDDA BUSA BUSA RXENA GNDA VDDB BUSB BUSB RXENB GNDB RXB RXB TXINHB TXB TXB RXA RXA TXINHA TXA TXA FUNCTION power supply analog output analog output digital input power supply power supply analog output analog output digital input power supply digital output digital output digital input digital input digital input digital output digital output digital input digital input digital input +5 volt power for channel A DESCRIPTION MIL-STD-1533 bus driver A, positive signal MIL-STD-1553 bus driver A, negative signal Receiver A enable. If low, forces RXA and RXA low (HI-1567) or High (HI-1568) Ground for channel A +5 volt power for channel B MIL-STD-1533 bus driver B, positive signal MIL-STD-1553 bus driver B, negative signal Receiver B enable. If low, forces RXB and RXB low (HI-1567) or High (HI-1568) Ground for channel B Receiver B output, inverted Receiver B outpot, non-invertedl Transmit inhibit, channel B. If high BUSB, BUSB disabled Transmitter B digital data input, non-inverted Transmitter B digital data input, inverted Receiver A output, inverted Receiver A output, non-inverted Transmit inhibit, channel A. If high BUSA, BUSA disabled Transmitter A digital data input, non-inverted Transmitter A digital data input, inverted FUNCTIONAL DESCRIPTION The HI-1567 family of data bus transceivers contain differential voltage source drivers and differential receivers. They are intended for applications using a MIL-STD-1553 A/B data bus. The device produces a trapezoidal output waveform during transmission. TRANSMITTER RECEIVER Data input to the transmitter section of these devices is from the complimentary CMOS /TTL inputs TXA/B and TXA/B. This produces a nominal 30V peak to peak signal across a 140 ohm load. The transmitter is connected to the bus via a 1:2.5 transformer whose secondary is connected to two 52 ohm isolation resisters which feed the terminated 70 ohm bus. This will produce a nominal voltage on the bus of 7.5 volts peak to peak. The receiver is transformer coupled to the bus by a 1:1 transformer. Its differential input stage drives a filter and threshold comparator. CMOS/TTL data is outputted at the RXA/B and RXA/B pins. The receiver outputs can both be forced to a logic "0" (HI-1567) or logic “1” (HI-1568) by setting RXENA or RXENB low. The transmitter is automatically inhibited and placed in the high impedance state when both TXA/B and TXA/B are either at a logic “1” or logic “0” simultaneously. A logic “1:” applied to the TXINHA/B input will force the transmitter to the high impedance state, regardless of the state of TXA/B and TXA/B HOLT INTEGRATED CIRCUITS 2 HI-1567, HI-1568 Each Channel TRANSMITTER Data Bus Isolation Transformer Coupler Network Direct or Transformer BUSA/B TXA/B Transmit Logic TXA/B TXINHA/B RECEIVER RXA/B Receive Logic RXA/B RXENA/B BUSA/B Slope Control Input Filter Comparator Figure 1. Block Diagram TXA/B TXA/B BUSA/B - BUSA/B Vin (Line to Line) RXA/B RXA/B HOLT INTEGRATED CIRCUITS 3 HI-1567, HI-1568 ABSOLUTE MAXIMUM RATINGS Supply voltage (VDD) Logic input voltage range Receiver differential voltage Driver peak output current Power dissipation at 25°C ceramic DIL, derate Solder Temperature Storage Temperature -0.3 V to +7 V -0.3 V dc to +5.5 V 10 Vp-p Temperature Range +1.0 A 0.5 W 7mW/°C 275°C for 10 sec -65°C to +150°C Industrial Screening.........-40°C to +85°C Hi-Temp Screening........-55°C to +125°C Military Screening..........-55°C to +125°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. RECOMMENDED OPERATING CONDITIONS Supply Voltage VDD....................................... 5V... ±5% VDD = 5.0V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER Operating Voltage Total Supply Current SYMBOL VDD ICC1 ICC2 ICC3 CONDITION Not Transmitting Transmit one channel @ 50% duty cycle Transmit one channel @ 100% duty cycle Not Transmitting Transmit one channel @ 100% duty cycle Digital inputs Digital inputs VIH = 4.9V, Digital inputs VIL = 0.1V, Digital inputs IOUT = -0.4mA, Digital outputs IOUT = 4.0mA, Digital outputs MIN 4.75 TYP 5 MAX 5.25 22 UNITS V mA mA mA W W V 320 570 340 615 0.4 0.95 Power Dissipation PD1 PD2 Min. Input Voltage Max. Input Voltage Min. Input Current Max. Input Current Min. Output Voltage Max. Output Voltage RECEIVER Input resistance Input capacitance (HI) (LO) (HI) (LO) (HI) (LO) VIH VIL IIH IIL VOH VIH 2.0 1.4 1.4 0.8 20 V µA µA V -20 2.7 0.4 V (Measured at Point “VIN” in Figure 2) Rin Cin CMRR Vin VICM VTH (Measured at Point “A” in Figure 2) Vout VON Vdyn Rout Cout 35 ohm load 140 ohm load Differential, inhibited Across 35 ohm load Across 140 ohm load Differential, not transmitting 1 MHz sine wave -90 -360 10 15 7.0 28.0 9.0 36.0 10.0 90 360 Vp-p Vp-p mVp-p mV mV kohm pF 1 MHz Sine Wave Differential -5.0 0.56 Differential Differential 40 8 5.0 1.2 20 5 kohm pF dB Vp-p V-pk Vp-p Common mode rejection ratio Input Level Input common mode voltage Threshold Voltage TRANSMITTER Output Voltage Output Noise Output Dynamic Offset Voltage Output resistance Output Capacitance HOLT INTEGRATED CIRCUITS 4 HI-1567, HI-1568 VCC = 5.0V, VSS = 0V, TA =Operating Temperature Range (unless otherwise specified). PARAMETER RECEIVER Receiver Delay Receiver Enable Delay TRANSMITTER Driver Delay Rise time Fall Time Inhibit Delay SYMBOL tDR tREN TEST CONDITIONS From input zero crossing to RXA/B or RXA/B From RXENA/B rising or falling edge to RXA/B or RXA/B MIN TYP MAX 450 40 UNITS ns ns (Measured at Point “VIN” in Figure 2) (Measured at Point “A” in Figure 2) tDT tr tf tDI-H tDI-L TXA/B, TXA/B to BUSA/B, BUSA/B 35 ohm load 35 ohm load Inhibited output Active output 100 100 150 300 300 100 150 ns ns ns ns ns TRANSMITTER TXA/B TXA/B TXINHA/B BUSA/B 1:2.5 55 Ω 35 Ω A BUSA/B 55 Ω 55 Ω VIN 35 Ω 55 Ω 2.5:1 RECEIVER RXA/B RXA/B RXENA/B Figure 2. Test circuit HOLT INTEGRATED CIRCUITS 5 HI-1567, HI-1568 ORDERING INFORMATION HI-1567PSI HI-1567PST HI-1567CD HI-1567CDT HI-1567CDM HI-1567CDM-03 HI-1568PSI HI-1568PST HI-1568CDI HI-1568CDT HI-1568CDM HI-1568CDM-03 0 0 0 0 0 0 1 1 1 1 1 1 20 PIN PLASTIC ESOIC - WB 20 PIN PLASTIC ESOIC - WB 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN PLASTIC ESOIC - WB 20 PIN PLASTIC ESOIC - WB 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP 20 PIN CERAMIC SIDE BRAZED DIP -40°C TO +85°C -55°C TO +125°C -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C -55°C TO +125°C -40°C TO +85°C -55°C TO +125°C -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C -55°C TO +125°C I T I T M M I T I T M M NO NO NO NO YES YES NO NO NO NO YES YES SOLDER SOLDER GOLD GOLD SOLDER SOLDER SOLDER SOLDER GOLD GOLD SOLDER SOLDER Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC w/built-in heat sink) WB - Wide Body HOLT INTEGRATED CIRCUITS 6 PACKAGE DIMENSIONS inches (millimeters) 20-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced) .0105 ± .0015 (.2667 ± .0381) Heat sink stud on bottom of package. Package Type: 24HEW .5035 ± .0075 (12.789 ± .191) .300 TYP. (7.620) .025 Min.. (.635) .4065 ± .0125 (10.325 ± .318) Top View .296 ± .003 (7.518 ± .076) .215 TYP. (5.461) Bottom View .018 TYP. (.457) SEE DETAIL A .025 Min.. (.635) .090 ± .010 (2.286 ± .254) 0° to 8° .050 TYP (1.27) .033 ± .017 (.838 ± .432) DETAIL A .0075 ± .0035 (.191 ± .889) 20-PIN CERAMIC SIDE-BRAZED DIP PACKAGE TYPE: 20C 1.000 ± .010 (25.400 ± .254) .310 ± .010 (7.874 ± .254) .050 TYP. (1.270 TYP.) .200 MAX. (5.080 MAX.) .085 ± .009 (2.159 ± .229) .300 ± .010 (7.620 ± .254) .125 MIN. (3.175 MIN.) .017 ± .002 (.432 ± .051) .100 ± .005 (2.540 ± .127) .010 + .002/− .001 (.254 ± .051/−.025) HOLT INTEGRATED CIRCUITS 7