HI-3189CLT

HI-3189 August 2008 ARINC 429 Differential Line Driver PIN CONFIGURATION VREF 1 RATE SELECT 2 SYNC 3 DATA(A) 4 CAPA 5 OUTA 6 -VS 7 GND 8 GENERAL DESCRIPTION The HI-3189 bus interface product is a silicon gate CMOS device designed as a line driver in accordance with the ARINC 429 bus specifications. It is a drop-in alternate source for the RM3182A (Fairchild /Raytheon) and DEI3182A. Inputs are provided for clocking and synchronization. These signals are AND'd with the DATA inputs to enhance system performance and allow the HI-3189 to be used in a variety of applications. Both logic and synchronization inputs feature built-in 2,000V minimum ESD input protection as well as TTL and CMOS compatibility. The HI-3189 has a digitally controlled data-rate input, allowing ARINC 429 line driver rise and fall times to be generated without changing the value of external timing components. The output voltage swing is adjustable by the application of an external voltage to the VREF input. The OUTA and OUTB outputs have internal 37.5 Ohm series resistors to meet ARINC 429 line driver impedance requirements, voltage clamp diodes to improve robustness to over-voltage conditions and are shortcircuit tolerant. Alternately, the AMPA and AMPB outputs have no internal resistors for applications that require additional clamping circuits to protect the HI-3189 from voltages that exceed the Maximum Ratings. The HI-3189 line driver is intended for use where logic signals must be converted to ARINC 429 levels such as when using an ASIC, for example the HI-3584 429 Serial Transmitter/Dual Receiver, the HI-6010 ARINC 429 Transmitter/Receiver or similar ARINC Interface Device. Holt products are readily available for both industrial and military applications. Please contact the Holt Sales Department for additional information. (Top View) 16 VLOGIC 15 AMPB 14 CLOCK 13 DATA(B) HI-3189 CD 12 CAPB 11 OUTB 10 AMPA 9 +VS 16 - Pin Ceramic Side Brazed DIP (See ordering information for additional pin configurations) +5V +15V AMPA INPUTS DATA (A) DATA (B) RATE SELECT VREF VLOGIC SYNC CLOCK +VS OUTA TO ARINC BUS -VS GND CAPB CAPA OUTB AMPB FEATURES ! Direct replacement for Fairchild/Raytheon RM3182A and DEI3182A ! TTL and CMOS compatible inputs ! Programmable output voltage swing ! Programmable ARINC rise and fall times ! Plastic 16-pin ceramic DIP and 28-lead ceramic LCC package options ! Operates at data rates up to 100 Kbits/s ! Overvoltage and short-circuit tolerance ! Industrial and Military temperature ranges -15V Figure 1. ARINC 429 Bus Application TRUTH TABLE SYNC CLOCK DATA(A) DATA(B) AOUT X L H H H H L X H H H H X X L L H H X X L H L H 0V 0V 0V -VREF +VREF 0V BOUT COMMENTS 0V 0V 0V +VREF -VREF 0V NULL NULL NULL LOW HIGH NULL Table 1. Truth Table (Ds3189 Rev.New ) HOLT INTEGRATED CIRCUITS www.holtic.com 08/08 HI-3189 PIN DESCRIPTIONS SYMBOL VREF RATE SELECT SYNC DATA (A) CAPA OUTA -VS GND +VS AMPA OUTB CAPB DATA (B) CLOCK AMPB VLOGIC FUNCTION ANALOG INPUT INPUT INPUT INPUT OUTPUT POWER POWER POWER OUTPUT OUTPUT INPUT INPUT INPUT OUTPUT POWER DESCRIPTION Ref. voltage used to determine output voltage swing. Pin sources current to allow use of a zener reference. Selects ARINC 429 data rate. See Table 2 for operation. Synchronizes data inputs Data input terminal A Connection for DATA (A) slew-rate capacitor ARINC output terminal A with 37.5 Ohms internal series resistance -15V ± 10% 0.0V +15V ± 10% ARINC output terminal A with 0 Ohms internal series resistance ARINC output terminal B with 37.5 Ohms internal series resistance Connection for DATA (B) slew-rate capacitor Data input terminal B Synchronizes data inputs ARINC output terminal B with 0 Ohms internal series resistance +5V ±10% Rate Select Logic “0” Logic “1” Logic “0” Logic “1” CAPA, CAPB Value (pF) 68 68 470 470 Rise / Fall Time 10% - 90% (us) 1.0 - 2.0 5.0 - 15.0 5.0 - 15.0 N/A Data Rate (Kbits/sec) 100 12.0 - 14.5 12.0 - 14.5 N/A Comments ARINC 429 High-Speed ARINC 429 Low-Speed ARINC 429 Low-Speed Not Used Table 2. Rate Select Pin Truth Table VREF +VS CAPA OUTPUT DRIVER (A) DATA (A) LEVEL SHIFTER AND SLOPE CONTROL (A) +VS 37.5 W AMPA OUTA CLOCK RATE SELECT SYNC LEVEL SHIFTER AND SLOPE CONTROL (B) OUTPUT DRIVER (B) -VS +VS 37.5 W OUTB CL RL DATA (B) -VS AMPB GND -VS CAPB Figure 2. Functional Block Diagram HOLT INTEGRATED CIRCUITS 2 HI-3189 FUNCTIONAL DESCRIPTION The HI-3189 is a complete differential line driver IC. When DATA (A) = DATA (B) or SYNC or CLOCK signal is low, the driver forces the output to a voltage Null level (0V +/- 250 mV). Designed to address the ARINC 429 standard, the HI-3189 has output rise and fall times that can be adjusted by the selection of an external capacitor (CAPA or CAPB) and an output voltage range adjustable through an externally applied VREF signal. All logic inputs and sync control inputs are TTL/CMOS compatible. The HI-3189 is available in 16-lead ceramic side-brazed DIP, 16-pin Cerdip and 28-pin ceramic LCC packages. See ordering information for available screening options. The device contains three main functional blocks. The first block is a digital section used to decode the ARINC Clock, Synchronization, and Data inputs as shown in the Functional Block Diagram (Figure 2). This block takes these inputs and channels the data to the Level Shifter and Slope control Circuit. The logical relationship for these pins is presented in Table 1. The second functional block is a charge pump circuit used to control the output waveform and its timing characteristics. This is achieved through charging and discharging a capacitor with a known current. The capacitor is user-selectable, and is connected between the CAPA or CAPB pins and ground. A Rate Select pin (digital input) is used to set the rise and fall time. If this pin is tied to ground, the device functions in the high-speed data rate. This mode is recommended if the user does not have an application requiring data rate switching. Table 2 gives recommended capacitor values for each possible data combination. The last functional block of the device consists of a voltage follower and high power output differential amplifier. The voltage follower buffers the signals presented at the charge capacitors and presents the mirrored signal to the difference amplifier to drive the ARINC line. Two different outputs are available from the differential amplifiers: AMPA, AMPB, and OUTA, OUTB. The outputs AMPA and AMPB are the direct outputs of the power amplifier. The outputs OUTA and OUTB include 37.5 Ohm series resistors added to minimize bus reflections by matching the power amplifier’s output impedance to the cable’s impedance of 75 Ohms. AMPA and AMPB may be used to customize the output impedance of the device. These outputs can also be used to enhance the device’s drive capability, for example, when driving the standard 10 nF // 400 Ohm load defined in the ARINC 429 specification (see output drive capability and capacitive loads for more details). All outputs are protected from voltage spikes with diodes connected between the output pins and the supply lines. APPLICATIONS Heat Sinking / Air Flow and Short Circuit Protection The user application will determine if and how much heat sinking / air flow will be required for the HI-3189. Consideration must be given to ambient temperature, load conditions and output voltage swing. In addition, power increases with increased operating frequency. Use the thermal conductivity numbers given in the Ordering Information section to determine that the maximum allowable junction temperature of 175°C is not exceeded. Outputs OUTA and OUTB will survive a short circuit to ground or to each other. During a short circuit of the output to either power supply or ground, the device must be able to dissipate the generated heat. For example, if the output is shorted to ground and +VS = +15V, the device must dissipate 15V x 0.165A = 2.5W. An appropriate heat sink is required in this situation. Note that AMPA and AMPB outputs have no internal series resistance. Shorting these pins to either power supply or ground may cause failure of the device. An added external resistor will protect the circuit by limiting the current. Power Supply Considerations Three power supplies are required to operate the HI-3189 in a typical ARINC 429 bus application: +15V for +VS, -15V for -VS and +5V for both VREF and VLOGIC. The differential output swing of the HI-3189 is equal to 2 x VREF. Using +5V gives a differential output swing of 10V. If a different output voltage swing is required, an additional power supply is needed to set VREF. Each power supply pin should be decoupled to ground using a high quality 10 uF tantalum capacitor. This is especially true when driving a large capacitive or resistive load. The decoupling capacitors should be located as close to the device pins as possible to eliminate the wiring inductance. HOLT INTEGRATED CIRCUITS 3 HI-3189 ABSOLUTE MAXIMUM RATINGS All Voltages referenced to GND, TA = Operating Temperature Range (unless otherwise specified) PARAMETER Differential Voltage Supply Voltage SYMBOL VDIF +VS -VS VLOGIC VREF VIN TA VPULSE TSTG CONDITIONS Voltage between +VS and -VS terminals OPERATING RANGE MAXIMUM 40 UNIT V V V V V V V °C °C +13.5 to +16.5 -13.5 to -16.5 +5 ±10% For ARINC 429 +5 ±10% 20 -20 +7 6 > GND -0.5 < VLOGIC +0.5 Voltage Reference Input Voltage Range Operating Temperature Range AMPA/B Transient pulse Storage Temperature Range Lead Temperature Junction Temperature High-temp & Military Industrial 150 us pulse applied through an external 37.5 Ohm resistor -55 to +125 -40 to +85 ±70 -65 to +150 V °C °C °C Soldering, 60 seconds TJ +300 -55 +175 NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TIMING DIAGRAMS DATA (A) DATA (B) VREF OUTA 0V ADJUST BY CA ADJUST BY CA 2.0V 0.5V 2.0V 0.5V +4.75V to +5.25V -VREF +VREF ADJUST BY CB ADJUST BY CB -4.75V to -5.25V +4.75V to +5.25V -4.75V to -5.25V HIGH NULL OUTB 0V -VREF tR DIFFERENTIAL OUTPUT 0V (OUTA - OUTB) NOTE: OUTPUTS UNLOADED 2VREF +9.5V to +10.5V tF -2VREF LOW -9.5V to -10.5V Figure 3. SWITCHING WAVEFORMS AC ELECTRICAL CHARACTERISTICS +V = +15V, -V = -15V, VLOGIC = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER Rise Time ( A OUT , B OUT ) - High Speed Fall Time ( A OUT , B OUT ) - High Speed Rise Time ( A OUT , B OUT ) - Low Speed Fall Time ( A OUT , B OUT ) - Low Speed SYMBOL tR tF tR tF CONDITION Rate Select = VIL, C A = C B = 68pF Rate Select = VIL, C A = C B = 68pF Rate Select = VIH, C A = C B = 68pF Rate Select = VIH, C A = C B = 68pF MIN 1.0 1.0 5.0 5.0 TYP MAX UNITS 2.0 2.0 15.0 15.0 µs µs µs µs HOLT INTEGRATED CIRCUITS 4 HI-3189 DC ELECTRICAL CHARACTERISTICS +V = +15V, -V = -15V, VLOGIC = VREF = +5.0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETER Supply Current +VS SYMBOL ICC CONDITION +VS = 16.5V, -VS=-16.5V VLOGIC = VREF = 5.5V DATA(A) = CLOCK = SYNC = “1” DATA(B) = RATE SELECT = “0” Data Rate = 0 to 100 KHz, no load +VS = 16.5V, -VS=-16.5V VLOGIC = VREF = 5.5V DATA(A) = CLOCK = SYNC = “1” DATA(B) = RATE SELECT = “0” Data Rate = 0 to 100 KHz, no load +VS = 16.5V, -VS=-16.5V VLOGIC = VREF = 5.5V DATA(A) = CLOCK = SYNC = “1” DATA(B) = RATE SELECT = “0” Data Rate = 0 to 100 KHz, no load +VS = 16.5V, -VS=-16.5V VLOGIC = VREF = 5.5V DATA(A) = CLOCK = SYNC = “1” Data Rate = 0 to 100 KHz, no load MIN TYP MAX UNITS 18 mA Supply Current -VS IEE 18 mA Supply Current +VLOGIC ILOGIC 300 µA Supply Current +VREF IREF -800 -100 µA Input Voltage High Input Voltage Low Input Current (Input High) VIH VIL IIH IIL CIN VOH VOL VNULL Zo VIN = 2.0V VLOGIC = VREF = 4.5V VIN = 0.5V VLOGIC = VREF = 5.5V See Note 1 No Load (0 -100KBPS) VREF = 5.0V Supplies min to max No Load (0 -100KBPS) VREF = 5.0V Supplies min to max No Load (0-100KBPS) 2.0 0.5 1.0 V V µA Input Current (Input Low) -645 nA Input Capacitance Output Voltage High (Output to Ground) Output Voltage Low (Output to Ground) 15 +VREF -.25 -VREF -.25 -250 67.5 +VREF +.25 -VREF +.25 +250 82.5 pF V V Output Voltage Null Output Impedance mV W mA Combined output impedance of OUTA and OUTB (See Note: 2) OUTA and/or OUTB shorted line-to-line or to GND. Outputs High or Low OUTA and/or OUTB shorted line-to-line or to GND. Outputs High or Low OUTA and/or OUTB shorted line-to-line or to GND. Outputs High or Low Output Short Circuit Current ISC ISC+VS ISC-VS 100 156 +VS Short Circuit Current 165 mA -VS Short Circuit Current Note 1. Guaranteed by design, but not tested. Note 2. Tested at DC only. -165 mA HOLT INTEGRATED CIRCUITS 5 HI-3189 ADDITIONAL PIN CONFIGURATIONS (See page 1 for 16-Pin Ceramic Side-Brazed DIP)) SYNC RATE SELECT N/C VREF VLOGIC N/C AMPB VREF 25 24 23 1 3 16 VLOGIC 15 AMPB 14 CLOCK 4 3 2 1 28 27 26 N/C DATA (A) N/C N/C CAPA N/C N/C 5 6 7 8 9 10 11 HI-3189CL 22 21 20 19 12 13 14 15 16 17 18 CLOCK N/C DATA (B) CAPB N/C AMPA N/C RATE SELECT 2 SYNC DATA(A) CAPA OUTA 4 HI-3189 13 DATA(B) CR 5 12 CAPB 6 8 11 OUTB 10 AMPA 9 +VS -VS 7 GND 28 - Pin Ceramic LCC (See page 1 for additional pin configurations) N/C OUTA -VS GND +VS OUTB N/C 16 - Pin Cerdip package (See page 1 for additional pin configurations) ORDERING INFORMATION HI - 3189 xx x PART NUMBER I T M TEMPERATURE RANGE -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C BURN IN No No Yes LEAD FINISH Theta JA Theta JC FLOW I T M PART PACKAGE NUMBER DESCRIPTION CD CL CR 16 PIN CERAMIC SIDE BRAZED DIP (16C) 16 PIN CERDIP (16D) not available with ‘M’ flow Gold (’M’ Flow: Solder) 70°C/W 28°C/W Solder 70°C/W 28°C/W 28 PIN CERAMIC LEADLESS CHIP CARRIER (LCC) (28S) Gold (’M’ Flow: Solder) 60°C/W 25°C/W HOLT INTEGRATED CIRCUITS 6 HI-3189 REVISION HISTORY Revision Date Description of Change Initial Release DS-3189, Rev. New 08/22/08 HOLT INTEGRATED CIRCUITS 7 HI-3189 PACKAGE DIMENSIONS 16-PIN CERDIP .790 max (20.006 max) .050 max (1.27 max) inches (millimeters) Package Type: 16D .005 min (.127 min) .288 ±.005 (7.315 ±.125) .056 typ (1.422 typ) .100 BSC (2.54) .310 ±.010 (7.874 ±.254) .180 max (4.572 max) .200 max (5.080 max) .015 min (.381 min) .125 min (3.175 min) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .018 ±.003 (.457 ±.760) 0° to 15° .010 ±.002 (.254 ±.051) 16-PIN CERAMIC SIDE-BRAZED DIP inches (millimeters) Package Type: 16C .810 max (20.574) .295 ±.010 (7.493 ±.254) .050 ±.005 (1.270 ±.127) .035 ± .010 (.889 ±.254) BASE PLANE SEATING PLANE .100 BSC (2.54) .300 ± .010 (7.620 ±.254) PIN 1 .200 max (5.080) .125 min (3.175) .010 ±.002 (.254 ±.051) .018 ± .002 (.457 ±.051) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 8 HI-3189 PACKAGE DIMENSIONS 28-PIN CERAMIC LEADLESS CHIP CARRIER inches (millimeters) Package Type: 28S .020 INDEX (.508) PIN 1 .080 ±.020 (2.032 ±.508) PIN 1 .050 ±.005 (1.270 ±.127) .451 ±.009 (11.455 ±.229) SQ. .050 BSC (1.270) .008R ± .006 (.203R ±.152) .040 x 45° 3PLS (1.016 x 45° 3PLS) .025 ±.003 (.635 ±.076) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 9