HI-3585PCT

HI-3585 May 2009 ARINC 429 Terminal IC with SPI Interface PIN CONFIGURATIONS (Top View) N/C RINA RINA-40 N/C VDD N/C V+ N/C AOUT27 AOUT37 N/C 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GENERAL DESCRIPTION The HI-3585 from Holt Integrated Circuits is a silicon gate CMOS device for interfacing a Serial Peripheral Interface (SPI) enabled microcontroller to the ARINC 429 serial bus. The device provides one receiver with user-programmable label recognition for any combination of 256 possible labels, 32 x 32 Receive FIFO and analog line receiver. The independent transmitter has a 32 x 32 Transmit FIFO and built-in line driver. The status of the transmit and receive FIFOs can be monitored using the programmable external interrupt pin, or by polling the HI-3585 Status Register. Other features include a programmable option of data or parity in the 32nd bit, and the ability to switch the bit-signifiance of ARINC 429 labels. Pins are available with different input resistance and output resistance values which provides flexibility when using external lightning protection circuitry. The Serial Peripheral Interface minimizes the number of host interface signals resulting in a small footprint device that can be interfaced to a wide range of industry-standard microcontrollers supporting SPI. Alternatively, the SPI signals may be controlled using just four general purpose I/O port pins from a microcontroller or custom FPGA. The SPI and all control signals are CMOS and TTL compatible and support 3.3V or 5V operation. The HI-3585 applies the ARINC 429 protocol to the receiver and transmitter. ARINC 429 databus timing comes from a 1 MHz clock input, or an internal counter can derive it from higher clock frequencies having certain fixed values, possibly the external host processor clock. - N/C RINB-40 RINB N/C N/C N/C MR SI CS N/C N/C -1 -2 -3 -4 -5 -6 -7 -8 -9 - 10 - 11 HI-3585PCI HI-3585PCT - BOUT27 BOUT37 N/C VN/C TFLAG N/C N/C RFLAG N/C N/C 44 - Pin Plastic 7mm x 7mm Chip-Scale Package (QFN) FEATURES · · · · · · · · · · · · ARINC specification 429 compliant 3.3V or 5.0V logic supply operation On-chip analog line driver and receiver connect directly to ARINC 429 bus Programmable label recognition for 256 labels 32 x 32 Receive FIFO and 32 x 32 Transmit FIFO Independent data rates for Transmit and Receive High-speed, four-wire Serial Peripheral Interface Label bit-order control 32nd transmit bit can be data or parity Self test mode Low power Industrial & extended temperature ranges N/C - 1 RINB-40 - 2 RINB - 3 N/C - 4 N/C - 5 N/C - 6 MR - 7 SI - 8 CS - 9 N/C - 10 N/C - 11 44 43 42 41 40 39 38 37 36 35 34 - N/C - RINA - RINA-40 - N/C - VDD - N/C - V+ - N/C - AOUT27 - AOUT37 - N/C N/C N/C N/C SCK N/C GND N/C ACLK SO N/C N/C - 12 13 14 15 16 17 18 19 20 21 22 HI-3585PQI HI-3585PQT 33 - BOUT27 32 - BOUT37 31 - N/C 30 - V29 - N/C 28 - TFLAG 27 - N/C 26 - N/C 25 - RFLAG 24 - N/C 23 - N/C 44 - Pin Plastic Quad Flat Pack (PQFP) (DS3585 Rev. B) HOLT INTEGRATED CIRCUITS www.holtic.com N/C - 12 N/C - 13 N/C - 14 SCK - 15 N/C - 16 GND - 17 N/C - 18 ACLK - 19 SO - 20 N/C - 21 N/C - 22 05/09 HI-3585 BLOCK DIAGRAM VDD ARINC 429 Line Driver V+ 10 Ohm ACLK ARINC Clock Divider ARINC 429 Transmit Data FIFO ARINC 429 Transmit Formatter AOUT37 AOUT27 BOUT27 27 Ohm 27 Ohm 10 Ohm BOUT37 V- SCK CS SI SO Control Register Status Register Label Filter Bit Map Memory SPI Interface TFLAG RINA-40 RINB-40 RINA RINB 40 Kohm 40 Kohm ARINC 429 Line Receiver ARINC 429 Valid word Checker Label Filter ARINC 429 Received Data FIFO RFLAG GND PIN DESCRIPTIONS SIGNAL FUNCTION RINB RINB-40 MR SI CS SCK GND ACLK SO RFLAG TFLAG VBOUT37 BOUT27 AOUT27 AOUT37 V+ VDD RINA-40 RINA INPUT INPUT INPUT INPUT INPUT INPUT POWER INPUT OUTPUT OUTPUT OUTPUT POWER OUTPUT OUTPUT OUTPUT OUTPUT POWER POWER INPUT INPUT DESCRIPTION ARINC receiver negative input. Direct connection to ARINC 429 bus Alternate ARINC receiver negative input. Requires external 40K ohm resistor Master Reset. A positive pulse clears Receive and Transmit data FIFOs and flags SPI interface serial data input Chip select. Data is shifted into SI and out of SO when CS is low. SPI Clock. Data is shifted into or out of the SPI interface using SCK Chip 0V supply Master timing source for the ARINC 429 receiver and transmitter SPI interface serial data output Goes high when ARINC 429 Receive FIFO is empty (CR15=0), or full (CR15=1) Goes high when ARINC 429 Transmit FIFO is empty (CR14=0), or full (CR14=1) Minus 5V power supply to ARINC 429 Line Driver ARINC line driver negative output. Direct connection to ARINC 429 bus Alternate ARINC line driver negative output. Requires external 10 ohm resistor Alternate ARINC line driver positive output. Requires external 10 ohm resistor ARINC line driver positive output. Direct connection to ARINC 429 bus Positive 5V power supply to ARINC 429 Line Driver 3.3V or 5.0V logic power Alternate ARINC receiver positive input. Requires external 40K ohm resistor ARINC receiver positive input. Direct connection to ARINC 429 bus PULL UP / DOWN 10K ohm pull-down 10K ohm pull-down 10K ohm pull-up 10K ohm pull-down 10K ohm pull-down HOLT INTEGRATED CIRCUITS 2 HI-3585 INSTRUCTIONS Instruction op codes are used to read, write and configure the HI3585. When CS goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the first positive edge. The op code is fed into the SI pin most significant bit first. For write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising SCK edge. Data word length varies depending on word type written: 16-bit writes to Control Register, 32-bit ARINC word writes to transmit FIFO or 256-bit writes to the label-matching enable/disable table. Table 1 lists all instructions. Instructions that perform a reset or set, or enable transmission are executed after the last SI bit is received while CS is still low. Example: CS SCK SI op code 07hex MSB one SPI Instruction For read instructions, the most significant bit of the requested data word appears at the SO pin after the last op code bit is clocked into the decoder, at the next falling SCK edge. As with write instructions, data field bit-length varies with read instruction type. data field 02hex LSB MSB LSB TABLE 1. DEFINED INSTRUCTION OP CODES OP CODE Hex DATA FIELD DESCRIPTION 00 01 02 03 04 05 06 None None None None 8 bits 8 bits 256 bits No instruction implemented After the 8th op code bit is received, perform Master Reset (MR) After the 8th op code bit is received, reset all label selections After the 8th op code bit is received, set all the label selections Reset the label at the address specified in the data field Set the label at the address specified in the data field Starting with label FF hex, consecutively set or reset each label in descending order For example, a Data Field pattern starting with 1011 will set labels FF, FD, and FC hex and reset label FE hex Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control Register bit CR1 is set, the ARINC receiver and transmitter operate from the divided ACLK clock. Allowable values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in no clock. Note: ACLK input frequency and division ratio must yield 1 MHz clock. Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros Dump the Receive FIFO. No framing. If CS held low after last word, the data will be zeros. Read the Status Register Read the Control Register Read the ACLK divide value programmed previously using op code 07 hex Read the Label look-up memory table consecutively starting with address FF hex. Write up to 32 words into the next empty positions of the Transmit FIFO No instruction implemented Write the Control Register Reset the Transmit FIFO. After the 8th op code bit is received, the transmit FIFO will be empty Transmission enabled by this instruction only if Control Register bit 13 is zero 07 8 bits 08 09 0A 0B 0C 0D 0E 0F 10 11 12 32 bits variable 8 bits 16 bits 8 bits 256 bits N x 32 Bits None 16 bits None None HOLT INTEGRATED CIRCUITS 3 HI-3585 FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3585 contains a 16-bit Control Register which is used to configure the device. Control Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction 10 hex. The Control Register contents may be read using SPI instruction 0B hex. Each bit of the Control Register has the following function: STATUS REGISTER The HI-3585 contains an 8-bit Status Register which can be interrogated to determine the status of the ARINC receiver, data FIFOs and transmitter. The contents of the Status Register are output using SPI instruction 0A hex. Unused bits are output as Zeros. The following table defines the Status Register bits. CR Bit Cr0 (LSB) CR1 FUNCTION STATE Receiver Data Rate Select ARINC Clock Source Select 0 1 0 1 DESCRIPTION Data rate = CLK/10 (ARINC 429 High-Speed) Data rate = CLK/80 (ARINC 429 Low-Speed) ARINC CLK = ACLK input frequency SR Bit SR0 (LSB) FUNCTION Receive FIFO Empty STATE 0 DESCRIPTION Receiver FIFO contains valid data Sets to One when all data has been read. RFLAG pin reflects the state of this bit when CR15=0 Receiver FIFO is empty Receiver FIFO holds less than 16 words Receiver FIFO holds at least 16 words Receiver FIFO not full. RFLAG pin reflects the state of this bit when CR15=1 Receiver FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period Transmit FIFO not empty. Sets to One when all data has been sent. TFLAG pin reflects the state of this bit when CR14=0 Transmit FIFO is empty. Transmit FIFO contains less than 16 words Transmit FIFO contains at least 16 words Transmit FIFO not full. TFLAG pin reflects the state of this bit when CR14=1 Transmit FIFO full. Always “0” Always “0” 1 ARINC CLK = ACLK divided by the value programmed with SPI Instruction 07 hex Label recognition disabled 1 1 Label recognition enabled Transmitter 32nd bit is data Transmitter 32nd bit is parity Receiver parity check disabled Receiver odd parity check enabled The transmitter’s digital outputs are internally connected to the receiver logic inputs Normal operation Receiver decoder disabled ARINC bits 10 and 9 must match CR7 and CR8 If receiver decoder is enabled, the ARINC bit 10 must match this bit If receiver decoder is enabled, the ARINC bit 9 must match this bit Transmitter 32nd bit is Odd parity Transmitter 32nd bit is Even parity Data rate = CLK/10, O/P slope = 1.5us Data rate = CLK/80, O/P slope = 10us Label bit order reversed (See Table 2) Label bit order same as transmitted / received (See Table 2) Line Driver enabled Line Driver disabled (force outputs to Null state) Start transmission by SPI instruction12 hex Transmit whenever data is available in the Transmit FIFO TFLAG goes high when transmit FIFO is empty TFLAG goes high when transmit FIFO is full RFLAG goes high when receive FIFO is empty RFLAG goes high when receive FIFO is full SR6 SR7 (MSB) Not used Not used 1 0 0 SR5 Transmit FIFO Full SR4 Transmit FIFO Half Full 1 0 1 0 SR3 Transmit FIFO Empty 0 1 SR2 Receive FIFO Full 0 0 1 0 1 0 1 SR1 Receive FIFO Half Full 0 CR2 Enable Label Recognition Transmitter Parity Bit Enable Receiver Parity Check Enable Self Test 0 CR3 CR4 CR5 CR6 Receiver Decoder Transmitter Parity Select Transmitter Data Rate ARINC Label Bit Order 0 1 CR7 CR8 CR9 0 1 0 1 CR10 CR11 0 1 CR12 Disable Line Driver Transmission Enable Mode 0 1 CR13 0 1 CR14 TFLAG Definition RFLAG Definition 0 1 CR15 (MSB) 0 1 HOLT INTEGRATED CIRCUITS 4 HI-3585 FUNCTIONAL DESCRIPTION (cont.) RECEIVER LOGIC OPERATION ARINC 429 DATA FORMAT Control Register bit CR11 controls how individual bits in the received or transmitted ARINC word are mapped to the HI-3585 SPI data word bits during data read or write operations. The following table describes this mapping: Table 2. SPI / ARINC bit-mapping SPI Order 1 2 - 22 31 - 11 23 24 25 26 27 28 29 30 31 32 10 9 1 2 3 4 5 6 7 8 Figure 2 is a block diagram showing receiver logic. BIT TIMING The ARINC 429 specification defines the following timing tolerances for received data: HIGH SPEED 100K BPS ± 1% 1.5 ± 0.5 µsec 1.5 ± 0.5 µsec 5 µsec ± 5% LOW SPEED 12K -14.5K BPS 10 ± 5 µsec 10 ± 5 µsec 34.5 to 41.7 µsec . ARINC bit 32 Label (MSB) CR11=0 Data Label (LSB) BIT RATE PULSE RISE TIME PULSE FALL TIME PULSE WIDTH Parity Label Label Label Label Label Label SDI SDI ARINC bit 32 31 - 11 10 9 8 7 6 5 4 3 2 1 The HI-3585 accepts signals within these tolerances and rejects signals outside these tolerances. Receiver logic achieves this as described below: 1. An accurate 1MHz clock source is required to validate the receive signal timing. Less than 0.1% error is recommended. 2. The receiver uses three separate 10-bit sampling shift registers for Ones detection, Zeros detection and Null detection. When the input signal is within the differential voltage range for any shift register’s state (One Zero or Null) sampling clocks a high bit into that register. When the receive signal is outside the differential voltage range defined for any shift register, a low bit is clocked. Only one shift register can clock a high bit for any given sample. All three registers clock low bits if the differential input voltage is between defined state voltage bands. Valid data bits require at least three consecutive One or Zero samples (three high bits) in the upper half of the Ones or Zeros sampling shift register, and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift register within the data bit interval. A word gap Null requires at least three consecutive Null samples (three high bits) in the upper half of the Null sampling shift register and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift register. This guarantees the minimum pulse width. CR11=1 Data ARINC 429 RECEIVER ARINC BUS INTERFACE Figure 1 shows the input circuit for the on-chip ARINC 429 line receiver. The ARINC 429 specification requires the following detection levels: STATE ONE NULL ZERO DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts RINA-40 VDD DIFFERENTIAL AMPLIFIERS COMPARATORS RINA ONE GND VDD NULL Label (MSB) Label (LSB) Label Label Label Label Label Parity Label SDI SDI ZERO RINB RINB-40 GND 3. To validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. With exactly 1MHz input clock frequency, the acceptable data bit rates are: HIGH SPEED DATA BIT RATE MIN DATA BIT RATE MAX 83K BPS 125K BPS LOW SPEED 10.4K BPS 15.6K BPS FIGURE 1. ARINC RECEIVER INPUT The HI-3585 guarantees recognition of these levels with a common mode voltage with respect to GND less than ±30V for the worst case condition (3.15V supply and 13V signal level). Design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal (including nulls) is outside the differential voltage ranges, the HI3585 receiver rejects the data. 4. Following the last data bit of a valid reception, the Word Gap timer samples the Null shift register every 10 input clocks (every 80 clocks for low speed). If a Null is present, the Word Gap counter is incremented. A Word Gap count of 3 enables the next reception. HOLT INTEGRATED CIRCUITS 5 HI-3585 FUNCTIONAL DESCRIPTION (cont.) TABLE 3. FIFO LOADING CONTROL RECEIVER PARITY The receiver parity circuit counts Ones received, including the parity bit. If the result is odd, a "0" appears in the 32nd bit. CR2 ARINC word matches Enabled label X No Yes X X Yes No No Yes CR6 ARINC word bits 10, 9 match CR7, 8 X X X No Yes No Yes No Yes FIFO RETRIEVING DATA Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). Depending on the state of Control Register bits CR2, CR6, CR7 and CR8, the received 32-bit ARINC word is then checked for correct decoding and label match before it is loaded into the 32 x 32 Receive FIFO. ARINC words that do not match required 9th and 10th ARINC bit and do not have a label match are ignored and are not loaded into the Receive FIFO. The adjacent table describes this operation. 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 Load FIFO Ignore data Load FIFO Ignore data Load FIFO Ignore data Ignore data Ignore data Load FIFO SCK CS SI SO SPI INTERFACE RFLAG FIFO LOAD CONTROL 32 X 32 FIFO CONTROL BITS CR2, CR6-8 / 256-BIT LABEL LOOK-UP TABLE LABEL / DECODE COMPARE CONTROLBITS CR0, CR1 CLOCK OPTION CLOCK ACLK 32 BIT SHIFT REGISTER DATA BIT CLOCK PARITY CHECK 32ND BIT BIT COUNTER AND END OF SEQUENCE EOS ONES SHIFT REGISTER WORD GAP WORD GAP TIMER BIT CLOCK START NULL SHIFT REGISTER SEQUENCE CONTROL END ZEROS SHIFT REGISTER ERROR ERROR DETECTION CLOCK FIGURE 2. RECEIVER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 6 HI-3585 FUNCTIONAL DESCRIPTION (cont.) Once a valid ARINC word is loaded into the FIFO, the EOS signal clocks the Data Ready flip-flop to a "1" and Status Register bit 0 (SR0) to a “0”. The SR0 bit remains low until the Receive FIFO is empty. Each received ARINC word is retrieved via the SPI interface using SPI instruction 08 hex to read a single word, or 09 hex to empty the entire Receive FIFO. Up to 32 ARINC words may be held in the Receive FIFO. Status register bit 2 (SR2) goes high when the Receive FIFO is full. Failure to unload the Receive FIFO when full causes additional received valid ARINC words to overwrite Receive FIFO location 32. A FIFO half-full flag (SR1) is high when the Receive FIFO contains 16 or more ARINC words. SR1 may be interrogated by the system’s external microprocessor, allowing a 16 word data retrieval routine to be performed. READING THE LABEL LOOK-UP TABLE The contents of the Label Look-up table may be read via the SPI interface using instruction 0D hex as described in Table 1. TRANSMITTER FIFO OPERATION The Transmit FIFO is loaded with ARINC 429 words awaiting transmission. SPI op code 0E hex writes up to 32 ARINC words into the FIFO, starting at the next available FIFO location. If Status Register bit SR3 equals “1” (FIFO empty), then up to 32 words (32 bits each) may be loaded. If Status Register bit SR3 equals “0” then only the available positions may be loaded. If all 32 positions are full, Status Register bit SR5 is asserted. Further attempts to load the Transmit FIFO are ignored until at least one ARINC word is transmitted. The Transmit FIFO half-full flag (Status Register bit SR4) equals “0” when the Transmit FIFO contains less than 16 words. When SR4 equals “0”, the system microprocessor can safely initiate a 16-word ARINC block-write sequence. In normal operation (Control Register bit CR3 = ”1”), the 32nd bit transmitted is a word parity bit. Odd or even parity is selected by programming Control Register bit CR9 to a “0” or “1” respectively. If Control Register bit CR3 equals “0”, all 32 bits loaded into the Transmit FIFO are treated as data and are transmitted. SPI op code 11 hex asynchronously clears all data in the Transmit FIFO. The Transmit FIFO should be cleared after a self-test before starting normal operation to avoid inadvertent transmission of test data. LABEL RECOGNITION The user loads the 256-bit label look-up table to specify which 8-bit incoming ARINC labels are captured by the receiver, and which are discarded. Setting a “1” in the look-up table enables processing of received ARINC words containing the corresponding label. A “0” in the look-up table causes discard of received ARINC words containing the label. The 256-bit look-up table is loaded using SPI op codes 02 hex, 03 hex or 06 hex, as described in Table 1. After the look-up table is initialized, set Control Register bit CR2 to enable label recognition. If label recognition is enabled, the receiver compares the label in each new ARINC word against the stored look-up table. If a label match is found, the received word is processed. If no match occurs, the new ARINC word is discarded and no indicators of received ARINC data are presented. CR3, CR9 32 BIT PARALLEL LOAD SHIFT REGISTER BIT CLOCK PARITY GENERATOR DATA AND NULL TIMER SEQUENCER LINE DRIVER AOUT BOUT CR12 WORD CLOCK BIT AND WORD GAP COUNTER START SEQUENCE 32 x 32 FIFO ADDRESS SR3 WORD COUNTER AND FIFO CONTROL INCREMENT WORD COUNT SR4 LOAD SR5 SCK CS SI SO SPI INTERFACE FIFO LOADING SEQUENCER SPI COMMANDS SPI COMMANDS DATA CLOCK CR10, CR1 DATA CLOCK DIVIDER ACLK FIGURE 3. TRANSMITTER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 7 HI-3585 FUNCTIONAL DESCRIPTION (cont.) DATA TRANSMISSION If Control Register bit CR13 equals “1”, ARINC 429 data is transmitted immediately following the CS rising edge of the SPI instruction that loaded data into the Transmit FIFO. Loading Control Register bit CR13 to “0” allows the software to control transmission timing; each time an SPI op code 12 hex is executed, all loaded Transmit FIFO words are transmitted. If new words are loaded into the Transmit FIFO before transmission stops, the new words will also be output. Once the Transmit FIFO is empty and transmission of the last word is complete, the FIFO can be loaded with new data which is held until the next SPI 12 hex instruction is executed. Once transmission is enabled, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at AOUT and BOUT. The 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: HIGH SPEED 10 Clocks 5 Clocks 5 Clocks 40 Clocks LOW SPEED 80 Clocks 40 Clocks 40 Clocks 320 Clocks Transmit timing is derived from a 1 MHZ reference clock. Control Register bit CR1 determines the reference clock source. If CR1 equals ”0,” a 50% duty cycle 1 MHZ clock should be applied to the ACLK input pin. If CR1 equals ”1,” the ACLK input is divided to generate the 1 MHZ ARINC clock. SPI op code 07 hex provides the HI-3585 with the correct division ratio to generate a 1 MHZ reference from ACLK. Loading Control Register bit CR10 to “0” causes a 100 Kbit/s data rate and a slope of 1.5 µs on the ARINC outputs. Loading CR10 to “1” causes a 12.5 Kbit/s data rate and a slope of 10 µs. Timing is set by an on-chip resistor and capacitor and tested to be within ARINC 429 requirements. LINE DRIVER OUTPUT PINS The HI-3585 AOUT37 and BOUT37 pins have 37.5 Ohms in series with each line driver output, and may be directly connected to an ARINC 429 bus. The alternate AOUT27 and BOUT27 pins have 27 ohms of internal series resistance and require external 10 ohm resistors at each pin. AOUT27 and BOUT27 are for applications where external series resistance is applied, typically for lightning protection devices. ARINC DATA BIT TIME DATA BIT TIME NULL BIT TIME WORD GAP TIME LINE RECEIVER INPUT PINS The word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, SR3, high. TRANSMITTER PARITY The parity generator counts the Ones in the 31-bit word. If control register bit CR9 is set to a “0”, the 32nd bit transmitted will make parity odd. If the control bit is a “1”, the parity is even. Setting CR3 to “0” bypasses the parity generator, and allows 32 bits of data to be transmitted. The HI-3585 has two sets of Line Receiver input pins, RINA/B and RINA/B-40. Only one pair may be used to connect to the ARINC 429 bus. The unused pair must be left floating. The RINA/B pins may be connected directly to the ARINC 429 bus. The RINA/B-40 pins require external 40K ohm resistors in series with each ARINC input. These do not affect the ARINC receiver thresholds. By keeping excessive voltage outside the device, this option is helpful in applications where lightning protection is required. When using the RINA/B-40 pins, each side of the ARINC bus must be connected through a 40K ohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 Volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 40K ohm resistors, they are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold. Please refer to the Holt AN-300 Application Note for additional information and recommendations on lightning protection of Holt line drivers and line receivers. SELF TEST If Control Register bits CR5 and CR12 equal ”0”, the transmitter serial output data is internally looped-back into the receiver. Data passes unmodified from transmitter to receiver. Setting Control register bit CR12 to ”1” forces AOUT and BOUT to the Null state regardless of CR5 state. SYSTEM OPERATION The receiver is independent of the transmitter. Therefore, control of data exchanges is strictly at the option of the user. The only restrictions are: 1. The received data will be overwritten if the Receive FIFO is full and at least one location is not retrieved before the next complete ARINC word is received. 2. The Transmit FIFO can store 32 words maximum and ignores attempts to load additional data when full. POWER SUPPLY SEQUENCING Power supply sequencing should be controlled to prevent large currents during supply turn-on and turn-off. The recommended sequence is V+ followed by VDD, always ensuring that V+ is the most positive supply. The V- supply is not critical and can be applied at any time. LINE DRIVER OPERATION The line driver in the HI-3585 directly drives the ARINC 429 bus. The two ARINC outputs (AOUT37 and BOUT37) provide a differential voltage to produce a +10V One, a -10V Zero, and a 0 Volt Null. Control Register bit CR10 controls both the transmitter data rate and the slope of the differential output signal. No additional hardware is required to control the slope. MASTER RESET (MR) Application of a Master Reset causes immediate termination of data transmission and data reception. The transmit and receive FIFOs are cleared. Status Register FIFO flags and FIFO status output signals RFLAG and TFLAG are also cleared. The Control Register is not affected by a Master Reset. HOLT INTEGRATED CIRCUITS 8 HI-3585 TIMING DIAGRAMS SERIAL INPUT TIMING DIAGRAM t CPH t CYC CS tCHH SCK t CES t SCKF t CEH t DS SI MSB t DH t SCKR LSB SERIAL OUTPUT TIMING DIAGRAM t CPH CS t CYC t SCKH tSCKL t CHZ MSB LSB Hi Impedance SCK SO Hi Impedance t DV DATA RATE - EXAMPLE PATTERN TXAOUT ARINC BIT TXBOUT DATA NULL DATA NULL DATA NULL BIT 30 BIT 31 BIT 32 WORD GAP BIT 1 NEXT WORD RECEIVER OPERATION ARINC DATA RFLAG BIT 31 BIT 32 tRFLG CS tRXR tSPIF SPI INSTRUCTION 08h, (or 09h) SI ARINC WORD 1 (ARINC WORD 2) (ARINC WORD 3) SO HOLT INTEGRATED CIRCUITS 9 HI-3585 TIMING DIAGRAMS (cont.) TRANSMITTING DATA CS SPI INSTRUCTION 0Eh, (or 12h) SI t TFLG TFLAG (CR14=0) tDATT t SDAT ARINC BIT DATA BIT 1 +5V ARINC BIT DATA BIT 2 ARINC BIT DATA BIT 32 +5V AOUT -5V +5V BOUT -5V -5V tfx +10V V DIFF (AOUT - BOUT) 90% 10% +10V tfx 10% zero level 90% trx null level trx one level -10V HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3585PCI and HI-3585PCT use a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically connected to the die. To enhance thermal dissipation, the heat sink can be soldered to matching circuit board pad. The heat sink may be connected to V+ or left floating. Do not connect heat sink pad to VDD, GND or V-. ABSOLUTE MAXIMUM RATINGS Supply Voltages VDD ......................................... -0.3V to +7.0V V+ ......................................................... +7.0V V- ......................................................... -7.0V Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ..... -29V to +29V Voltage at any other pin ............................... -0.3V to VDD +0.3V Solder temperature (Leads) .................... 280°C for 10 seconds (Package) .......................................... 220°C Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C DC Current Drain per pin .............................................. ±10mA Storage Temperature Range ........................ -65°C to +150°C Operating Temperature Range (Industrial): ..... -40°C to +85°C (Hi-Temp): ..... -55°C to +125°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HOLT INTEGRATED CIRCUITS 10 HI-3585 DC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5.0V , V+ = +5V, V- = -5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LIMITS PARAMETER ARINC INPUTS - SYMBOL CONDITIONS MIN TYP MAX UNIT Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms) ONE ZERO NULL Differential To GND To VDD Input Sink Input Source Differential To GND To VDD VIH VIL VNUL RI RG RH IIH IIL CI CG CH (RINA to RINB) Common mode voltages less than ±30V with respect to GND 6.5 -13.0 -2.5 10.0 -10.0 0 140 140 100 13.0 -6.5 2.5 200 -450 20 20 20 V V V KW KW KW µA µA pF pF pF Differential Input Voltage: (RIN1A to RIN1B, RIN2A to RIN2B) Input Resistance: Input Current: Input Capacitance: (Guaranteed but not tested) LOGIC INPUTS Input Voltage: Input Current: Input Voltage HI Input Voltage LO Input Sink Input Source Pull-down Current (MR, SI, SCK, ACLK pins) Pull-up current (CS pin) VIH VIL IIH IIL IPD IPU 80% VDD 20% VDD V V µA µA µA µA 1.5 -1.5 250 -600 600 -300 ARINC OUTPUTS - Pins AOUT37, BOUT37, (or AOUT27, BOUT27 with external 10 Ohms) ARINC output voltage (Ref. To GND) ARINC output voltage (Differential) ARINC output current LOGIC OUTPUTS Output Voltage: Output Current: Output Capacitance: Operating Voltage Range VDD V+ VOperating Supply Current VDD V+ VIDD1 IDD2 IEE1 2.5 4 4 7 14 12 mA mA mA 3.15 4.75 -4.75 5.25 5.5 -5.5 V V V Logic "1" Output Voltage Logic "0" Output Voltage Output Sink Output Source VOH VOL IOL IOH CO IOH = -100µA IOL = 1.0mA VOUT = 0.4V VOUT = VDD - 0.4V 90%VDD 10% VDD One or zero Null One or zero Null VDOUT VNOUT VDDIF VNDIF IOUT No load and magnitude at pin, No load and magnitude at pin, Momentary current 4.50 -0.25 9.0 -0.5 80 5.00 10.0 5.50 0.25 11.0 0.5 V V V V mA V V mA mA pF 1.6 -1.0 15 HOLT INTEGRATED CIRCUITS 11 HI-3585 AC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5.0V, V+=+5V, V-=-5V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz +0.1% with 60/40 duty cycle LIMITS PARAMETER SPI INTERFACE TIMING SCK clock period CS active after last SCK rising edge CS setup time to first SCK rising edge CS hold time after last SCK falling edge CS inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SCK rise time SCK fall ime SCK pulse width high SCK pulse width low SO valid after SCK falling edge SO high-impedance after SCK falling edge RECEIVER TIMING Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Hi Speed Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Lo Speed Received data available to SPI interface. RFLAG to CS active SPI receiver read or clear FIFO instruction to RFLAG TRANSMITTER TIMING SPI transmit data write or FIFO clear instruction to TFLAG (Empty or Full) SPI instruction to ARINC 429 data output - Hi Speed SPI instruction to ARINC 429 data output - Lo Speed Delay TFLAG high after enable transmit - Hi Speed Delay TFLAG high after enable transmit - Lo Speed Line driver transition differential times: high to low (High Speed, control register CR10 = Logic 0) low to high (Low Speed, control register CR10 = Logic 1) high to low low to high tTFLG tSDAT tSDAT tDATT tDATT tfx trx tfx trx 1.0 1.0 5.0 5.0 1.5 1.5 10 10 120 17 118 14 114 2.0 2.0 15 15 ns µs µs µs µs µs µs µs µs tRFLG tRFLG tRXR tSPIF 16 126 0 155 µs µs ns ns tCYC tCHH tCES tCEH tCPH tDS tDH tSCKR tSCKF tSCKH tSCKL tDV tCHZ 200 10 10 40 35 30 30 10 10 90 80 95 100 ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNITS ORDERING INFORMATION HI - 3585 xx x x PART NUMBER LEAD FINISH Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I T PART NUMBER -40°C TO +85°C -55°C TO +125°C PACKAGE DESCRIPTION I T No No PC PQ 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) 44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS) HOLT INTEGRATED CIRCUITS 12 HI-3585 REVISION HISTORY Revision Date Description of Change DS3585,Rev. NEW 05/08/08 Initial Release Rev. A 10/10/08 Revised AC Electrical Characteristics table and description of “T” process. Rev. B 05/22/09 Clarified relationship between SPI bit order and the ARINC 429 bit order. HOLT INTEGRATED CIRCUITS 13 HI-3585 PACKAGE DIMENSIONS 44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) inches (millimeters) Package Type: 44PCS .203 ± .006 (5.15 ± .15) .020 BSC (0.50) .276 BSC (7.00) Top View .203 ± .006 (5.15 ± .15) Bottom View .010 (0.25) typ .039 max (1.00) .008 typ (0.2) Heat sink pad on bottom of package. Heat sink must be left floating or connected to V+ DO NOT connect to GND, VDD or V-. .016 ± .002 (0.40 ± .05) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: .006 MAX. (.15) 44PTQS .0315 BSC (.80) .547 ± .010 (13.90 ± .25) SQ. .394 ± .004 (10.0 ± .10) SQ. .014 ± ..002 (.35 ± .05) .035 ± .006 (.88 ± .15) See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .055 ± .002 (1.4 ± .05) .012 R MAX. (.30) .005 R MIN. Detail A (.13) 0° £ Q £ 7° HOLT INTEGRATED CIRCUITS 14