HI-3587PCT

HI-3587 June 2009 ARINC 429 Transmitter with SPI Interface PIN CONFIGURATIONS (Top View) N/C N/C N/C N/C VDD N/C V+ N/C AOUT27 AOUT37 N/C N/C N/C N/C N/C N/C N/C MR SI CS N/C N/C -1 -2 -3 -4 -5 -6 -7 -8 -9 - 10 - 11 GENERAL DESCRIPTION The HI-3587 from Holt Integrated Circuits is a silicon gate CMOS device for interfacing a Serial Peripheral Interface (SPI) enabled microcontroller to an ARINC 429 serial bus. The device provides one ARINC 429 transmitter with 32 X 32 Transmit FIFO and built-in line driver. Transmit FIFO status can be monitored using the programmable external interrupt pin, or by polling the HI-3587 Status Register. Other features include a programmable option of data or parity in the 32nd bit, and the ability to switch the bitsignifiance of ARINC 429 labels. Line driver output pins are available with different values of output resistance to provide flexibility when using external lightning protection circuitry. The Serial Peripheral Interface minimizes the number of host interface signals and provides a small footprint device that can be interfaced to a wide variety of industrystandard microcontrollers supporting SPI. Alternatively, the SPI signals may be controlled using four general purpose I/O port pins from a microcontroller or custom FPGA. The SPI and all control signals are CMOS and TTL compatible and support 3.3V or 5V operation. The HI-3587 applies the ARINC 429 protocol to the transmitter. ARINC 429 databus timing comes from a 1 MHz clock input, or an internal counter can derive it from higher clock frequencies having certain fixed values, possibly the external host processor clock. 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 - HI-3587PCI HI-3587PCT - BOUT27 BOUT37 N/C VN/C TFLAG N/C N/C N/C N/C N/C 44 - Pin Plastic 7mm x 7mm Chip-Scale Package (QFN) FEATURES · · · · · · · · · · ARINC specification 429 compliant 3.3V or 5.0V logic supply operation On-chip analog line driver connects directly to ARINC 429 bus 32 x 32 Transmit Data FIFO Programmable data rate selection High-speed, four-wire Serial Peripheral Interface Label bit-order control 32nd transmit bit can be data or parity Low power Industrial & extended temperature ranges N/C - 1 N/C - 2 N/C - 3 N/C - 4 N/C - 5 N/C - 6 MR - 7 SI - 8 CS - 9 N/C - 10 N/C - 11 44 43 42 41 40 39 38 37 36 35 34 - N/C - N/C - N/C - N/C - VDD - N/C - V+ - N/C - AOUT27 - AOUT37 - N/C N/C N/C N/C SCK N/C GND N/C ACLK SO N/C N/C - 12 13 14 15 16 17 18 19 20 21 22 HI-3587PQI HI-3587PQT 33 - BOUT27 32 - BOUT37 31 - N/C 30 - V29 - N/C 28 - TFLAG 27 - N/C 26 - N/C 25 - N/C 24 - N/C 23 - N/C 44 - Pin Plastic Quad Flat Pack (PQFP) ( DS3587 Rev. D) HOLT INTEGRATED CIRCUITS www.holtic.com N/C - 12 N/C - 13 N/C - 14 SCK - 15 N/C - 16 GND - 17 N/C - 18 ACLK - 19 SO - 20 N/C - 21 N/C - 22 06/09 HI-3587 BLOCK DIAGRAM VDD ARINC 429 Line Driver ACLK ARINC Clock Divider ARINC 429 Transmit Data FIFO ARINC 429 Transmit Formatter 27 Ohm 27 Ohm 10 Ohm V+ 10 Ohm AOUT37 AOUT27 BOUT27 BOUT37 V- SCK CS SI SO Control Register Status Register SPI Interface TFLAG GND PIN DESCRIPTIONS SIGNAL MR SI CS SCK GND ACLK SO TFLAG VBOUT37 BOUT27 AOUT27 AOUT37 V+ VDD FUNCTION INPUT INPUT INPUT INPUT POWER INPUT OUTPUT OUTPUT POWER OUTPUT OUTPUT OUTPUT OUTPUT POWER POWER DESCRIPTION Master Reset. A positive pulse clears the Transmit data FIFO and flags SPI interface serial data input Chip select. Data is shifted into SI and out of SO when CS is low. SPI Clock. Data is shifted into or out of the SPI interface using SCK Chip 0V supply Master timing source for the ARINC 429 transmitter SPI interface serial data output Goes high when ARINC 429 transmit FIFO is empty (CR14=0), or full (CR14=1) Minus 5V power supply to ARINC 429 Line Driver ARINC line driver negative output. Direct connection to ARINC 429 bus Alternate ARINC line driver negative output. Requires external 10 ohm resistor Alternate ARINC line driver positive output. Requires external 10 ohm resistor ARINC line driver positive output. Direct connection to ARINC 429 bus Positive 5V power supply to ARINC 429 Line Driver 3.3V or 5.0V logic power PULL UP / DOWN 10K ohm pull-down 10K ohm pull-down 10K ohm pull-up 10K ohm pull-down 10K ohm pull-down HOLT INTEGRATED CIRCUITS 2 HI-3587 INSTRUCTIONS Instruction op codes are used to read, write and configure the HI3587. When CS goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the first rising SCK edge. The op code is fed into the SI pin, most significant bit first. For write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising SCK edge. Data word length varies depending on word type written: 16-bit writes to Control Register or 32-bit ARINC word writes to transmit FIFO. Table 1 lists all instructions. Instructions that perform a reset or set, or enable transmission are executed after the last SI bit is received while CS is still low. Example: CS SCK SI op code 07hex MSB one SPI Instruction For read instructions, the most significant bit of the requested data word appears at the SO pin after the last op code bit is clocked into the decoder, at the next falling SCK edge. As in write instructions, read instruction data field bit-length varies with read instruction type. data field 02hex LSB MSB LSB TABLE 1. DEFINED INSTRUCTION OP CODES OP CODE Hex DATA FIELD DESCRIPTION 00 01 02 03 04 05 06 07 None None None None None None None 8 bits No instruction implemented After the 8th op-code bit is received, perform Master Reset (MR) No instruction implemented No instruction implemented No instruction implemented No instruction implemented No instruction implemented Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control Register bit CR1 is set, the ARINC transmitter operates from the divided ACLK clock. Allowable values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in no clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock." Reserved [Note 1] Reserved [Note 1] Read the Status Register Read the Control Register Read the ACLK divide value programmed previously using op code 07 hex Reserved [Note 1] Write up to 32 words into the next empty position of the Transmitter FIFO No instruction implemented Write the Control Register Reset the Transmitter FIFO. After the 8th op-code bit is received, the Xmit FIFO will be empty Transmission enabled by this instruction only if Control Register bit 13 is zero 08 09 0A 0B 0C 0D 0E 0F 10 11 12 [Note 1] [Note 1] 8 bits 16 bits 8 bits [Note 1] N x 32 Bits None 16 bits None None Note 1: This instruction is reserved for factory test only. If executed, up to 1,024 data bits may be output from the SO pin. HOLT INTEGRATED CIRCUITS 3 HI-3587 FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3587 has a 16-bit Control Register which configures the device. Control Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction 10 hex. The Control Register contents may be read using SPI instruction 0B hex. Each bit of the Control Register has the following function: STATUS REGISTER The HI-3587 contains an 8-bit Status Register which can be interrogated to determine status of the ARINC Transmit FIFO. The Status Register is read using SPI instruction 0A hex. Unused bits are undefined and may be read as either “1” or “0”. The following table defines the Status Register bits. CR Bit FUNCTION STATE CR0 (LSB) CR1 ARINC Clock Source Select X 0 1 CR2 CR3 Transmitter Parity Bit Enable Transmitter Parity Select Transmitter Data Rate X 0 1 X X X X X 0 1 0 1 CR11 ARINC Label Bit Order 0 1 CR12 Disable Line Driver 0 1 CR13 Transmission Enable Mode 0 1 Cr14 TFLAG Definition 0 1 CR15 (MSB) X DESCRIPTION Not used ARINC CLK = ACLK input frequency ARINC CLK = ACLK divided by the value programmed with SPI Instruction 07 hex Not used Transmitter 32nd bit is data Transmitter 32nd bit is parity Not used Not used SR Bit SR0 (LSB) SR1 SR2 SR3 FUNCTION Not used Not used Not used Transmit FIFO Empty STATE X X X 0 DESCRIPTION Undefined Undefined Undefined Transmit FIFO not empty. Sets to One when all data has been sent. TFLAG pin reflects the state of this bit when CR14=0 Transmit FIFO is empty. Transmit FIFO contains less than 16 words Transmit FIFO contains at least 16 words Transmit FIFO not full. TFLAG pin reflects the state of this bit when CR14=1 Transmit FIFO full. Always 0 Always 0 1 SR4 Transmit FIFO Half Full 0 1 CR4 CR5 CR6 CR7 CR8 CR9 Not used Not used Not used Transmitter 32nd bit is Odd parity Transmitter 32nd bit is Even parity Data rate=CLK/10, O/P slope=1.5u Data rate=CLK/80, O/P slope=10us Label bit order reversed (See Table 2) Label bit order same as transmitted (See Table 2) Line Driver enabled Line Driver disabled (force outputs to Null state) Start transmission by SPI instruction12h Transmit whenever data is available in the Transmit FIFO TFLAG goes high when transmit FIFO is empty TFLAG goes high when transmit FIFO is full Not used SR6 SR7 (MSB) Not used Not used 1 0 0 SR5 Transmit FIFO Full 0 CR10 HOLT INTEGRATED CIRCUITS 4 HI-3587 FUNCTIONAL DESCRIPTION (cont.) ARINC 429 DATA FORMAT Control Register bit CR11 controls how individual bits in the transmitted ARINC word are mapped to the HI-3587 SPI data word bits during data read or write operations. The following table describes this mapping: Table 2. SPI / ARINC bit-mapping SPI Order 1 2 - 22 31 - 11 23 24 25 26 27 28 29 30 31 32 10 9 1 2 3 4 5 6 7 8 The Transmit FIFO half-full flag (Status Register bit SR4) equals “0” when the Transmit FIFO contains less than 16 words. When SR4 equals “0”, the system microprocessor can safely initiate a 16-word ARINC block-write sequence. In normal operation (Control Register bit CR3 = ”1”), the 32nd bit transmitted is a word parity bit. Odd or even parity is selected by programming Control Register bit CR9 to a “0” or “1” respectively. If Control Register bit CR3 equals “0”, all 32 bits loaded into the Transmit FIFO are treated as data and are transmitted. SPI op code 11 hex asynchronously clears all data in the Transmit FIFO. . ARINC bit 32 Label (MSB) Label (LSB) 1 Parity Label Label Label Label Label Label SDI SDI CR11=0 Data DATA TRANSMISSION If Control Register bit CR13 equals “1”, ARINC 429 data is transmitted immediately following the CS rising edge of the SPI instruction that loaded data into the Transmit FIFO. Loading Control Register bit CR13 to “0” allows the software to control transmission timing; each time a 12 hex SPI op code is executed, all loaded Transmit FIFO words are transmitted. If new words are loaded into the Transmit FIFO before transmission stops, the new words will also be output. Once the Transmit FIFO is empty and transmission of the last word is complete, the FIFO can be loaded with new data which is held until the next SPI 12 hex instruction is executed. Once transmission is enabled, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at AOUT and BOUT. The 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: ARINC bit 32 31 - 11 10 9 8 7 6 5 4 3 2 CR11=1 Data TRANSMITTER FIFO OPERATION The Transmit FIFO is loaded with ARINC 429 words awaiting transmission. SPI op code 0E hex writes up to 32 ARINC words into the FIFO, starting at the next available FIFO location. If Status Register bit SR3 equals “1” (FIFO empty), then up to 32 words (32 bits each) may be loaded. If Status Register bit SR3 equals “0” then only the available positions may be loaded. If all 32 positions are full, Status Register bit SR5 is asserted. Further attempts to load the Transmit FIFO are ignored until at least one ARINC word is transmitted. CR3, CR9 Label (MSB) Label (LSB) Label Label Label Label Label Parity Label SDI SDI 32 BIT PARALLEL LOAD SHIFT REGISTER BIT CLOCK PARITY GENERATOR DATA AND NULL TIMER SEQUENCER LINE DRIVER AOUT BOUT CR12 WORD CLOCK BIT AND WORD GAP COUNTER START SEQUENCE 32 x 32 FIFO ADDRESS LOAD WORD COUNTER AND FIFO CONTROL INCREMENT WORD COUNT SR3 SR4 SR5 SCK CS SI SO SPI INTERFACE FIFO LOADING SEQUENCER SPI COMMANDS SPI COMMANDS DATA CLOCK CR10, CR1 DATA CLOCK DIVIDER ACLK FIGURE 1. TRANSMITTER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 5 HI-3587 FUNCTIONAL DESCRIPTION (cont.) ARINC DATA BIT TIME DATA BIT TIME NULL BIT TIME WORD GAP TIME HIGH SPEED 10 Clocks 5 Clocks 5 Clocks 40 Clocks LOW SPEED 80 Clocks 40 Clocks 40 Clocks 320 Clocks Loading Control Register bit CR10 to “0” causes a 100 Kbit/s data rate and a slope of 1.5 µs on the ARINC outputs. Loading CR10 to “1” causes a 12.5 Kbit/s data rate and a slope of 10 µs. Timing is set by an on-chip resistor and capacitor and tested to be within ARINC 429 requirements. The word counter detects when all loaded positions have been transmitted and sets the Status Register transmitter ready flag, SR3, high. LINE DRIVER OUTPUT PINS The HI-3587 AOUT37 and BOUT37 pins have 37.5 Ohms in series with each line driver output, and may be directly connected to an ARINC 429 bus. The alternate AOUT27 and BOUT27 pins have 27 ohms of internal series resistance and require external 10 ohm resistors at each pin. AOUT27 and BOUT27 are for applications where external series resistance is applied, usually for lightning protection. TRANSMITTER PARITY The parity generator counts the Ones in the 31-bit word. If control register bit CR9 is set to a “0”, the 32nd bit transmitted will make parity odd. If the control bit is a “1”, the parity is even. Setting CR3 to “0” bypasses the parity generator, and allows 32 bits of data to be transmitted. POWER SUPPLY SEQUENCING Power supply sequencing should be controlled to prevent large currents during supply turn-on and turn-off. The recommended sequence is V+ followed by VDD, always ensuring that V+ is the most positive supply. The V- supply is not critical and can be applied at any time. LINE DRIVER OPERATION The line driver in the HI-3587 directly drives the ARINC 429 bus. The two ARINC outputs (AOUT37 and BOUT37) provide a differential voltage to produce a +10V One, a -10V Zero, and a 0 Volt Null. Control Register bit CR10 controls both the transmitter data rate and the slope of the differential output signal. No additional hardware is required to control the slope. Transmit timing is derived from a 1MHz reference clock. Control register bit CR1 determines the reference clock source. If CR1 equals ”0,” a 50% duty cycle 1MHz clock should be applied to the ACLK input pin. If CR1 equals ”1,” the ACLK input is divided to generate the 1 MHz ARINC clock. SPI op code 07 hex provides the HI-3587 with the correct division ratio to generate a 1 MHZ reference from ACLK. MASTER RESET (MR) Application of a Master Reset causes immediate termination of data transmission. The transmit FIFO is cleared. Status Register FIFO flags and FIFO status output signal TFLAG is also cleared. The Control Register is not affected by a Master Reset. TIMING DIAGRAMS SERIAL INPUT TIMING DIAGRAM t CPH t CYC CS tCHH SCK t CES t SCKF t CEH t DS SI MSB t DH t SCKR LSB SERIAL OUTPUT TIMING DIAGRAM t CPH CS t CYC t SCKH tSCKL t CHZ MSB LSB Hi Impedance SCK t SO Hi Impedance DV HOLT INTEGRATED CIRCUITS 6 HI-3587 TIMING DIAGRAMS (Cont.) DATA RATE - EXAMPLE PATTERN TXAOUT ARINC BIT TXBOUT DATA NULL DATA NULL DATA NULL BIT 30 BIT 31 BIT 32 WORD GAP BIT 1 NEXT WORD TRANSMITTING DATA CS SPI INSTRUCTION 0Eh, (or 12h) SI t TFLG TFLAG (CR14=0) tDATT t SDAT ARINC BIT DATA BIT 1 +5V ARINC BIT DATA BIT 2 ARINC BIT DATA BIT 32 +5V AOUT -5V +5V BOUT -5V -5V tfx +10V V DIFF (AOUT - BOUT) 90% 10% +10V tfx 10% zero level 90% trx null level trx one level -10V HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3587PCI and HI-3587PCT use a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface. This heat sink is electrically connected to the die. To enhance thermal dissipation, the heat sink can be soldered to matching circuit board pad. The heat sink may be connected to V+ or left floating. Do not connect heat sink pad to VDD, GND or V-. HOLT INTEGRATED CIRCUITS 7 HI-3587 ABSOLUTE MAXIMUM RATINGS Supply Voltages VDD ......................................... -0.3V to +7.0V V+ ......................................................... +7.0V V- ......................................................... -7.0V Voltage at any logic pin ................................-0.3V to VDD +0.3V DC Current Drain per pin .............................................. ±10mA Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C Storage Temperature Range ........................ -65°C to +150°C Operating Temperature Range (Industrial): .... -40°C to +85°C (Hi-Temp): .....-55°C to +125°C Solder temperature (Leads) .................... 280°C for 10 seconds (Package) .......................................... 220°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5.0V , V+ = +5V, V- = -5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LIMITS PARAMETER LOGIC INPUTS Input Voltage: Input Current: Input Voltage HI Input Voltage LO Input Sink Input Source Pull-down Current (MR, SI, SCK, ACLK pins) Pull-up Current (CS pin) VIH VIL IIH IIL IPD IPU 80% VDD 20% VDD SYMBOL CONDITIONS MIN TYP MAX UNIT V V µA µA µA µA 1.5 -1.5 250 -600 600 -300 ARINC OUTPUTS - Pins AOUT37, BOUT37, (or AOUT27, BOUT27 with external 10 Ohms) ARINC output voltage (Ref. To GND) ARINC output voltage (Differential) ARINC output current LOGIC OUTPUTS Output Voltage: Output Current: (All Outputs & Bi-directional Pins) Output Capacitance: Operating Voltage Range VDD V+ VOperating Supply Current VDD V+ VIDD1 IDD2 IEE1 2.5 4 4 7 14 12 mA mA mA 3.15 4.75 -4.75 5.25 5.5 -5.5 V V V Logic "1" Output Voltage Logic "0" Output Voltage Output Sink Output Source VOH VOL IOL IOH CO IOH = -100µA IOL = 1.0mA VOUT = 0.4V VOUT = VDD - 0.4V 90%VDD 10% VDD One or zero Null One or zero Null VDOUT VNOUT VDDIF VNDIF IOUT No load and magnitude at pin, No load and magnitude at pin, Momentary current 4.50 -0.25 9.0 -0.5 80 5.00 10.0 5.50 0.25 11.0 0.5 V V V V mA V V mA mA pF 1.6 -1.0 15 HOLT INTEGRATED CIRCUITS 8 HI-3587 AC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5.0V, V+=+5V, V-=-5V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz +0.1% with 60/40 duty cycle LIMITS PARAMETER SPI INTERFACE TIMING SCK clock period CS active after last SCK rising edge CS setup time to first SCK rising edge CS hold time after last SCK falling edge CS inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SCK rise time SCK fall ime SCK pulse width high SCK pulse width low SO valid after SCK falling edge SO high-impedance after SCK falling edge TRANSMITTER TIMING SPI transmit data write or FIFO clear instruction to TFLAG (Empty or Full) SPI instruction to ARINC 429 data output - Hi Speed SPI instruction to ARINC 429 data output - Lo Speed Delay TFLAG high after enable transmit - Hi Speed Delay TFLAG high after enable transmit - Lo Speed Line driver transition differential times: high to low (High Speed, control register CR10 = Logic 0) low to high (Low Speed, control register CR10 = Logic 1) high to low low to high SYMBOL MIN TYP MAX UNITS tCYC tCHH tCES tCEH tCPH tDS tDH tSCKR tSCKF tSCKH tSCKL tDV tCHZ 200 10 10 40 35 30 30 10 10 90 80 95 100 ns ns ns ns ns ns ns ns ns ns ns ns ns tTFLG tSDAT tSDAT tDATT tDATT tfx trx tfx trx 1.0 1.0 5.0 5.0 1.5 1.5 10 10 120 17 118 14 114 2.0 2.0 15 15 ns µs µs µs µs µs µs µs µs ORDERING INFORMATION HI - 3587 xx x x PART NUMBER LEAD FINISH Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE BURN IN FLOW I T PART NUMBER -40°C TO +85°C -55°C TO +125°C PACKAGE DESCRIPTION I T No No PC PQ 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) 44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS) HOLT INTEGRATED CIRCUITS 9 HI-3587 REVISION HISTORY Revision Date Description of Change Initial Release Clarified the FIFO description Revised AC Electrical Characteristics Clarified the relationship between SPI bit order and the ARINC 429 bit order Clarified the written description of CR1 and its relationship with ACLK. DS3587, Rev. NEW 05/08/08 Rev. A 06/09/08 Rev. B 10/10/08 Rev. C 05/22/09 Rev. D 06/09/09 HOLT INTEGRATED CIRCUITS 10 HI-3587 PACKAGE DIMENSIONS 44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) inches (millimeters) Package Type: 44PCS .203 ± .006 (5.15 ± .15) .020 BSC (0.50) .276 BSC (7.00) Top View .203 ± .006 (5.15 ± .15) Bottom View .010 (0.25) typ .039 max (1.00) .008 typ (0.2) Heat sink pad on bottom of package. Heat sink must be left floating or connected to V+ DO NOT connect to GND, VDD or V-. .016 ± .002 (0.40 ± .05) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: .006 MAX. (.15) 44PTQS .0315 BSC (.80) .547 ± .010 (13.90 ± .25) SQ. .394 ± .004 (10.0 ± .10) SQ. .014 ± ..002 (.35 ± .05) .035 ± .006 (.88 ± .15) See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .055 ± .002 (1.4 ± .05) .012 R MAX. (.30) .005 R MIN. Detail A (.13) 0° £ Q £ 7° HOLT INTEGRATED CIRCUITS 11