HI-3588

HI-3588 July 2009 ARINC 429 Receiver with SPI Interface PIN CONFIGURATIONS (Top View) N/C RINA RINA-40 N/C VDD N/C N/C N/C N/C N/C N/C 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 GENERAL DESCRIPTION The HI-3588 from Holt Integrated Circuits is a silicon gate CMOS device for interfacing a Serial Peripheral Interface (SPI) enabled microcontroller to an ARINC 429 serial bus. The device provides one receiver with user-programmable label recognition for any combination of 256 possible labels, a 32 by 32 Receive FIFO and an analog line receiver. Receive FIFO status can be monitored using the programmable external interrupt pin, or by polling the HI-3588 Status Register. Other features include the ability to switch the bit-signifiance of ARINC 429 labels. The ARINC input pins are available with different input resistance values to provide flexibility when adding external lightning protection circuitry. The Serial Peripheral Interface minimizes the number of host interface signals allowing for a small footprint device which can be interfaced to a wide variety of industrystandard microcontrollers supporting SPI. Alternatively, the SPI signals may be controlled using just four general purpose I/O port pins from a microcontroller or custom FPGA. The SPI and all control signals are CMOS and TTL compatible and support 3.3V or 5V operation. The HI-3588 checks received data against ARINC 429 electrical, timing and protocol requirements. ARINC 429 databus timing comes from a 1 MHz clock input, or an internal counter can derive it from higher clock frequencies having certain fixed values, possibly the external host processor clock. - N/C RINB-40 RINB N/C N/C N/C MR SI CS N/C N/C -1 -2 -3 -4 -5 -6 -7 -8 -9 - 10 - 11 HI-3588PCI HI-3588PCT - N/C N/C N/C GND N/C N/C N/C N/C RFLAG N/C N/C 44 - Pin Plastic 7mm x 7mm Chip-Scale Package (QFN) FEATURES · · · · · · · · · · · ARINC specification 429 compliant 3.3V or 5.0V logic supply operation On-chip analog line receiver connects directly to ARINC 429 bus Programmable label recognition for 256 labels 32 x 32 Receive Data FIFO Programmable data rate selection High-speed, four-wire Serial Peripheral Interface Label bit-order control Parity checking may be disabled to allow 32-bit data reception Low power Industrial & extended temperature ranges N/C - 1 RINB-40 - 2 RINB - 3 N/C - 4 N/C - 5 N/C - 6 MR - 7 SI - 8 CS - 9 N/C - 10 N/C - 11 44 43 42 41 40 39 38 37 36 35 34 - N/C - RINA - RINA-40 - N/C - VDD - N/C - N/C - N/C - N/C - N/C - N/C N/C N/C N/C SCK N/C GND N/C ACLK SO N/C N/C - 12 13 14 15 16 17 18 19 20 21 22 HI-3588PQI HI-3588PQT 33 - N/C 32 - N/C 31 - N/C 30 - GND 29 - N/C 28 - N/C 27 - N/C 26 - N/C 25 - RFLAG 24 - N/C 23 - N/C 44 - Pin Plastic Quad Flat Pack (PQFP) (DS3588 Rev. C) HOLT INTEGRATED CIRCUITS www.holtic.com N/C - 12 N/C - 13 N/C - 14 SCK - 15 N/C - 16 GND - 17 N/C - 18 ACLK - 19 SO - 20 N/C - 21 N/C - 22 07/09 HI-3588 BLOCK DIAGRAM VDD ACLK ARINC Clock Divider SCK CS SI SO Control Register Status Register Label Filter Bit Map Memory SPI Interface RINA-40 RINB-40 RINA RINB 40 Kohm 40 Kohm ARINC 429 Line Receiver ARINC 429 Valid word Checker Label Filter ARINC 429 Received Data FIFO RFLAG GND PIN DESCRIPTIONS SIGNAL FUNCTION RINB RINB-40 MR SI CS SCK GND ACLK SO RFLAG VDD RINA-40 RINA INPUT INPUT INPUT INPUT INPUT INPUT POWER INPUT OUTPUT OUTPUT POWER INPUT INPUT DESCRIPTION ARINC receiver negative input. Direct connection to ARINC 429 bus Alternate ARINC receiver negative input. Requires external 40K ohm resistor Master Reset. A positive pulse clears the Receiver data FIFO and flags SPI interface serial data input Chip select. Data is shifted into SI and out of SO when CS is low. SPI Clock. Data is shifted into or out of the SPI interface using SCK Chip 0V supply. Note BOTH GND pins MUST be connected Master timing source for the ARINC 429 receiver SPI interface serial data output Goes high when ARINC 429 receiver FIFO is empty (CR15=0), or full (CR15=1) 3.3V or 5.0V logic power Alternate ARINC receiver positive input. Requires external 40K ohm resistor ARINC receiver positive input. Direct connection to ARINC 429 bus PULL UP / DOWN 10K ohm pull-down 10K ohm pull-down 10K ohm pull-up 10K ohm pull-down 10K ohm pull-down HOLT INTEGRATED CIRCUITS 2 HI-3588 INSTRUCTIONS Instruction op codes are used to read, write and configure the HI3588A. When CS goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the first positive edge. The op code is fed into the SI pin, most significant bit first. For write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising SCK edge. Data word length varies depending on word type written: 16-bit writes to Control Register, 32-bit ARINC word writes to transmit FIFO or 256-bit writes to the label-matching enable/disable table. Table 1 lists all instructions. Instructions that perform a reset or set are executed after the last SI bit is received while CS is still low. Example: CS SCK SI op code 07hex MSB one SPI Instruction data field 02hex LSB MSB LSB For read instructions, the most significant bit of the requested data word appears at the SO pin after the last op code bit is clocked into the decoder, at the next falling SCK edge. As in write instructions, data field bit-length varies with read instruction type. TABLE 1. DEFINED INSTRUCTION OP CODES OP CODE Hex DATA FIELD DESCRIPTION 00 01 02 03 04 05 06 None None None None 8 bits 8 bits 256 bits No instruction implemented After the 8th op-code bit is received, perform Master Reset (MR) After the 8th op-code bit is received, reset all label selections After the 8th op-code bit is received, set all the label selections Reset label at address specified in data field Set label at address specified in data field Starting with label FF hex, consecutively set or reset each label in descending order For example, a Data Field pattern starting with 1011 will set labels FF, FD, and FC hex and reset label FE hex. Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control Register bit CR1 is set, the ARINC receiver operates from the divided ACLK clock. Allowable values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in no clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock. Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros Dump the Receive FIFO. No framing. If CS held low after last word, the data will be zeros. Read the Status Register Read the Control Register Read the ACLK divide value programmed previously using op code 07 hex Read the Label look-up memory table consecutively starting with address FF hex No instruction implemented No instruction implemented Write the Control Register 07 8 bits 08 09 0A 0B 0C 0D 0E 0F 10 32 bits variable 8 bits 16 bits 8 bits 256 bits None None 16 bits HOLT INTEGRATED CIRCUITS 3 HI-3588 FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3588 contains a 16-bit Control Register which is used to configure the device. Control Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction 10 hex. The Control Register contents may be read using SPI instruction 0B hex. Each bit of the Control Register has the following function: STATUS REGISTER The HI-3588 contains an 8-bit Status Register which can be interrogated to determine status of the ARINC Receive FIFO. The Status Register is read using SPI instruction 0A hex. Unused bits are undefined and may be read as either “1” or “0”. The following table defines the Status Register bits. CR Bit FUNCTION STATE CR0 (LSB) Receiver Data Rate Select 0 1 0 1 CR2 Enable Label Recognition CR3 CR4 Receiver Parity Check Enable Receiver Enable 0 1 X 0 1 0 1 CR6 Receiver Decoder 0 1 CR7 CR8 CR9 CR10 X X 0 1 CR12 CR13 CR14 CR15 (MSB) RFLAG Definition X X X 0 1 DESCRIPTION Data rate = CLK/10 (ARINC 429 High-Speed) Data rate = CLK/80 (ARINC 429 Low-Speed) ARINC CLK = ACLK input frequency SR Bit SR0 (LSB) FUNCTION Receive FIFO Empty STATE 0 DESCRIPTION Receiver FIFO contains valid data Sets to One when all data has been read. RFLAG pin reflects the state of this bit when CR15=”0” Receiver FIFO is empty Receiver FIFO holds less than 16 words Receiver FIFO holds at least 16 words Receiver FIFO not full. RFLAG pin reflects the state of this bit when CR15=”1” Receiver FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period Undefined Undefined Undefined Always “0” Always “0” CR1 ARINC Clock Source Select 1 ARINC CLK = ACLK divided by the value programmed with SPI Instruction 07 hex Label recognition disabled 1 Label recognition enabled Not used Receiver parity check disabled Receiver odd parity check enabled Disable receiver. The HI-3588 ignores all ARINC 429 data bus traffic SR3 Normal operation SR4 Receiver decoder disabled SR5 ARINC bits 10 and 9 must match CR7 and CR8 SR6 If receiver decoder is enabled, the ARINC bit 10 must match this bit If receiver decoder is enabled, the ARINC bit 9 must match this bit Not used Not used Label bit order reversed (SeeTable 2) Label bit order same as received (See Table 2) Not used Not used Not used FLAG goes high when receive FIFO is empty RFLAG goes high when receive FIFO is full CR11=0 SPI Order SR7 (MSB) Not used Not used 0 0 Not used X Not used X Not used X 1 SR2 Receive FIFO Full 0 SR1 Receive FIFO Half Full 0 CR5 ARINC 429 DATA FORMAT Control Register bit CR11 controls how individual bits in the received ARINC word are mapped to the HI-3588 SPI data word bits during data read or write operations. The following table describes this mapping: Table 2. SPI / ARINC bit-mapping 1 2 - 22 31 - 11 23 24 25 26 27 28 29 30 31 32 10 9 1 2 3 4 5 6 7 8 CR11 ARINC Label Bit Order . ARINC bit 32 Label (MSB) Data ARINC bit 32 31 - 11 10 9 8 7 6 5 4 3 2 CR11=1 Data HOLT INTEGRATED CIRCUITS 4 Label (MSB) Label (LSB) Label Label Label Label Label Parity Label SDI SDI Label (LSB) 1 Parity Label Label Label Label Label Label SDI SDI HI-3588 FUNCTIONAL DESCRIPTION (cont.) ARINC 429 RECEIVER ARINC BUS INTERFACE Figure 1 shows the input circuit for the ARINC 429 line receiver. The ARINC 429 specification requires the following detection levels: STATE ONE NULL ZERO DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts ister, a low bit is clocked. Only one shift register can clock a high bit for any given sample. All three registers clock low bits if the differential input voltage is between defined state voltage bands. Valid data bits require at least three consecutive One or Zero samples (three high bits) in the upper half of the Ones or Zeros sampling shift register, and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift register within the data bit interval. A word gap Null requires at least three consecutive Null samples (three high bits) in the upper half of the Null sampling shift register and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift register. This guarantees the minimum pulse width. RINA-40 VDD DIFFERENTIAL AMPLIFIERS COMPARATORS RINA ONE GND VDD NULL 3. To validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. With exactly 1MHz input clock frequency, the acceptable data bit rates are: HIGH SPEED DATA BIT RATE MIN DATA BIT RATE MAX 83K BPS 125K BPS LOW SPEED 10.4K BPS 15.6K BPS ZERO RINB RINB-40 GND FIGURE 1. ARINC RECEIVER INPUT The HI-3588 guarantees recognition of these levels with a common mode voltage with respect to GND less than ±30V for the worst case condition (3.15V supply and 13V signal level). Design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal (including nulls) is outside the differential voltage ranges, the HI-3588 receiver rejects the data. RECEIVER LOGIC OPERATION Figure 2 is a block diagram showing receiver logic. BIT TIMING The ARINC 429 specification defines the following timing tolerances for received data: HIGH SPEED 100K BPS ± 1% 1.5 ± 0.5 µsec 1.5 ± 0.5 µsec 5 µsec ± 5% LOW SPEED 12K -14.5K BPS 10 ± 5 µsec 10 ± 5 µsec 34.5 to 41.7 µsec 4. Following the last data bit of a valid reception, the Word Gap timer samples the Null shift register every 10 input clocks (every 80 clocks for low speed). If a Null is present, the Word Gap counter is incremented. A Word Gap count of 3 enables the next reception. RECEIVER PARITY The receiver parity circuit counts Ones received, including the parity bit. If the result is odd, a "0" appears in the 32nd bit. RETRIEVING DATA Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). Depending on the state of Control Register bits CR2, and CR6 through CR8, the received 32-bit ARINC word is then checked for correct decoding and label match before it is loaded into the 32 x 32 Receive FIFO. ARINC words that do not match required 9th and 10th ARINC bit and do not have a label match are ignored and are not loaded into the Receive FIFO. The table below describes this operation. CR2 ARINC word matches Enabled label X No Yes X X Yes No No Yes CR6 ARINC word bits 10, 9 match CR7,8 X X X No Yes No Yes No Yes FIFO BIT RATE PULSE RISE TIME PULSE FALL TIME PULSE WIDTH The HI-3588 accepts signals within these tolerances and rejects signals outside these tolerances. Receiver logic achieves this as described below: 1. An accurate 1MHz clock source is required to validate the receive signal timing. Less than 0.1% error is recommended. 2. The receiver uses three separate 10-bit sampling shift registers for Ones detection, Zeros detection and Null detection. When the input signal is within the differential voltage range for any shift register’s state (One Zero or Null) sampling clocks a high bit into that register. When the receive signal is outside the differential voltage range defined for any shift reg- 0 1 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 1 Load FIFO Ignore data Load FIFO Ignore data Load FIFO Ignore data Ignore data Ignore data Load FIFO HOLT INTEGRATED CIRCUITS 5 HI-3588 FUNCTIONAL DESCRIPTION (cont.) Once a valid ARINC word is loaded into the FIFO, the EOS signal clocks the Data Ready flip-flop to a "1" and Status Register bit 0 (SR0) to a “0”. The SR0 bit remains low until the Receive FIFO is empty. Each received ARINC word is retrieved via the SPI interface using SPI instruction 08 hex to read a single word, or 09 hex to empty the entire Receive FIFO. Up to 32 ARINC words may be held in the Receive FIFO. Status register bit 2 (SR2) goes high when the Receive FIFO is full. Failure to unload the Receive FIFO when full causes additional received valid ARINC words to overwrite Receive FIFO location 32. A FIFO half-full flag (SR1) is high when the Receive FIFO contains 16 or more ARINC words. SR1 may be interrogated by the system’s external microprocessor, allowing a 16 word data retrieval routine to be performed. occurs, the new ARINC word is discarded and no indicators of received ARINC data are presented. READING THE LABEL LOOK-UP TABLE The contents of the Label Look-up table may be read via the SPI interface using instruction 0D hex as described in Table 1. LINE RECEIVER INPUT PINS The HI-3588 has two sets of Line Receiver input pins, RINA/B and RINA/B-40. Only one pair may be used to connect to the ARINC 429 bus. The unused pair must be left floating. The RINA/B pins may be connected directly to the ARINC 429 bus. The RINA/B-40 pins require external 40K ohm resistors in series with each ARINC input. These do not affect the ARINC receiver thresholds. By keeping excessive voltage outside the device, this option is helpful in applications where lightning protection is required. When using the RINA/B-40 pins, each side of the ARINC bus must be connected through a 40K ohm series resistor in order for the chip to detect the correct ARINC levels. The typical 10 Volt differential signal is translated and input to a window comparator and latch. The comparator levels are set so that with the external 40K ohm resistors, they are just below the standard 6.5 volt minimum ARINC data threshold and just above the standard 2.5 volt maximum ARINC null threshold. Please refer to the Holt AN-300 Application Note for additional information and recommendations on lightning protection of Holt line drivers and line receivers. LABEL RECOGNITION The user loads the 256-bit label look-up table to specify which 8-bit incoming ARINC labels are captured by the receiver, and which are discarded. Setting a “1” in the look-up table enables processing of received ARINC words containing the corresponding label. A “0” in the look-up table causes discard of received ARINC words containing the label. The 256-bit look-up table is loaded using SPI op codes 02 hex, 03 hex or 06 hex, as described in Table 1. After the look-up table is initialized, set Control Register bit CR2 to enable label recognition. If label recognition is enabled, the receiver compares the label in each new ARINC word against the stored look-up table. If a label match is found, the received word is processed. If no match CS RFLAG FIFO LOAD CONTROL 32 X 32 FIFO SPI INTERFACE SI SO SCK CONTROL BITS CR2, CR6-8 / 256-BIT LABEL LOOK-UP TABLE LABEL / DECODE COMPARE CONTROL BITS CR0, CR1 CLOCK OPTION CLOCK ACLK 32 BIT SHIFT REGISTER DATA PARITY CHECK 32ND BIT BIT COUNTER AND END OF SEQUENCE BIT CLOCK EOS ONES WORD GAP SHIFT REGISTER WORD GAP TIMER BIT CLOCK END NULL SHIFT REGISTER START SEQUENCE CONTROL ERROR ZEROS SHIFT REGISTER ERROR DETECTION CLOCK FIGURE 2. RECEIVER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 6 HI-3588 FUNCTIONAL DESCRIPTION (cont.) MASTER RESET (MR) Assertion of Master Reset causes immediate termination of data reception. The receive FIFO, Status Register FIFO flags and the FIFO status RFLAG pin is also cleared. The Control Register is not affected by Master Reset. TIMING DIAGRAMS SERIAL INPUT TIMING DIAGRAM t CPH t CYC CS tCHH SCK t CES t SCKF t CEH t DS SI MSB t DH t SCKR LSB SERIAL OUTPUT TIMING DIAGRAM t CPH CS t CYC t SCKH tSCKL t CHZ MSB LSB Hi Impedance SCK SO Hi Impedance t DV DATA RATE - EXAMPLE PATTERN TXAOUT ARINC BIT TXBOUT DATA NULL DATA NULL DATA NULL BIT 30 BIT 31 BIT 32 WORD GAP BIT 1 NEXT WORD RECEIVER OPERATION ARINC DATA RFLAG BIT 31 BIT 32 tRFLG CS tRXR tSPIF SPI INSTRUCTION 08h, (or 09h) SI ARINC WORD 1 (ARINC WORD 2) (ARINC WORD 3) SO HOLT INTEGRATED CIRCUITS 7 HI-3588 ABSOLUTE MAXIMUM RATINGS Supply Voltages VDD ......................................... -0.3V to +7.0V Power Dissipation at 25°C Plastic Quad Flat Pack ..................1.5 W, derate 10mW/°C DC Current Drain per pin .............................................. ±10mA Storage Temperature Range ........................ -65°C to +150°C Operating Temperature Range (Industrial): .... -40°C to +85°C (Hi-Temp): .....-55°C to +125°C Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ..... -29V to +29V Voltage at any other pin ............................... -0.3V to VDD +0.3V Solder temperature (Leads) .................... 280°C for 10 seconds (Package) .......................................... 220°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5.0V , GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LIMITS PARAMETER ARINC INPUTS - SYMBOL CONDITIONS MIN TYP MAX UNIT Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms) ONE ZERO NULL Differential To GND To VDD Input Sink Input Source Differential To GND To VDD VIH VIL VNUL RI RG RH IIH IIL CI CG CH (RINA to RINB) Common mode voltages less than ±30V with respect to GND 6.5 -13.0 -2.5 10.0 -10.0 0 140 140 100 13.0 -6.5 2.5 200 -450 20 20 20 V V V KW KW KW µA µA pF pF pF Differential Input Voltage: (RIN1A to RIN1B, RIN2A to RIN2B) Input Resistance: Input Current: Input Capacitance: (Guaranteed but not tested) LOGIC INPUTS Input Voltage: Input Current: Input Voltage HI Input Voltage LO Input Sink Input Source Pull-down Current (MR, SI, SCK, ACLK pins) Pull-up Current (CS Pin) VIH VIL IIH IIL IPD IPU 80% VDD 20% VDD V V µA µA µA µA 1.5 -1.5 250 -600 600 -300 LOGIC OUTPUTS Output Voltage: Output Current: (All Outputs & Bi-directional Pins) Output Capacitance: Operating Voltage Range VDD Operating Supply Current VDD IDD 2.5 7 mA 3.15 5.25 V Logic "1" Output Voltage Logic "0" Output Voltage Output Sink Output Source VOH VOL IOL IOH CO IOH = -100µA IOL = 1.0mA VOUT = 0.4V VOUT = VDD - 0.4V 90%VDD 10% VDD V V mA mA pF 1.6 -1.0 15 HOLT INTEGRATED CIRCUITS 8 HI-3588 AC ELECTRICAL CHARACTERISTICS VDD = 3.3V or 5.0V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz +0.1% with 60/40 duty cycle LIMITS PARAMETER SPI INTERFACE TIMING SCK clock period CS active after last SCK rising edge CS setup time to first SCK rising edge CS hold time after last SCK falling edge CS inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SCK rise time SCK fall ime SCK pulse width high SCK pulse width low SO valid after SCK falling edge SO high-impedance after SCK falling edge RECEIVER TIMING Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Hi Speed Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Lo Speed Received data available to SPI interface. RFLAG to CS active SPI receiver read or clear FIFO instruction to RFLAG tRFLG tRFLG tRXR tSPIF 16 126 0 155 µs µs ns ns tCYC tCHH tCES tCEH tCPH tDS tDH tSCKR tSCKF tSCKH tSCKL tDV tCHZ 200 20 10 40 35 30 30 10 10 90 80 130 100 ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNITS HEAT SINK - CHIP-SCALE PACKAGE ONLY The HI-3588PCI and HI-3588PCT use a 44-pin plastic chip-scale package. This package has a metal heat sink pad on its bottom surface that is electrically connected to the die. For the HI-3588, the primary advantage of this package is its small size; heat sinking provides little benefit because HI-3588 dissipation is low. If connected, the heat bottom sink pad should be connected to VDD. Do not connect heat sink pad to GND. ORDERING INFORMATION HI - 3588 xx x x PART NUMBER LEAD FINISH Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I T PART NUMBER -40°C TO +85°C -55°C TO +125°C PACKAGE DESCRIPTION I T No No PC PQ 44 PIN PLASTIC CHIP-SCALE, QFN (44PCS) 44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS) HOLT INTEGRATED CIRCUITS 9 HI-3588 REVISION HISTORY Revision Date Description of Change DS3588, Rev. NEW 05/08/08 Initial Release Rev. A 10/10/08 Revised AC Electrical Characteristics Rev. B 05/22/09 Clarified relationship between SPI bit order and ARINC 429 bit order Rev. C 07/02/09 Removed references to V+, V-, which are not connected on this device HOLT INTEGRATED CIRCUITS 10 HI-3588 PACKAGE DIMENSIONS 44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) .276 BSC (7.00) inches (millimeters) Package Type: 44PCS .203 ± .006 (5.15 ± .15) .020 BSC (0.50) .276 BSC (7.00) Top View .203 ± .006 (5.15 ± .15) Bottom View .010 (0.25) typ .039 max (1.00) .008 typ (0.2) Heat sink pad on bottom of package. Heat sink must be left floating or connected to VDD. DO NOT connect to GND. .016 ± .002 (0.40 ± .05) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: .006 MAX. (.15) 44PTQS .0315 BSC (.80) .547 ± .010 (13.90 ± .25) SQ. .394 ± .004 (10.0 ± .10) SQ. .014 ± ..002 (.35 ± .05) .035 ± .006 (.88 ± .15) See Detail A .063 MAX. (1.6) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .055 ± .002 (1.4 ± .05) .012 R MAX. (.30) .005 R MIN. Detail A (.13) 0° £ Q £ 7° HOLT INTEGRATED CIRCUITS 11