HI-3717

HI-3717 November 2011 Single-Rail ARINC 717 Protocol IC with SPI Interface APPLICATIONS · · · · Digital Flight Data Acquisition Units (DFDAU) Digital Flight Data Recorders (DFDR) Quick Access Recorders (cassette type) Expandable Flight Data Acquisition and Recording Systems GENERAL DESCRIPTION The HI-3717 from Holt Integrated Circuits is a CMOS device designed for interfacing an ARINC 717 compatible bus to a Serial Peripheral Interface (SPI) enabled micro-controller. The part includes a selectable Harvard Bi-Phase (HBP) or Bi-Polar Return-to-Zero (BPRZ) receive channel and transmit channels with HBP and BPRZ encoders and line drivers. The receive channel has integrated analog line receivers and the transmit channels have integrated line drivers for the corresponding encoding method (HBP and BPRZ). The part operates from a single +3.3V supply using only four external capacitors. Each transmit and receive channel has a 32-word by 12-bit FIFO for data buffering. The HI-3717 is available in very small 44-pin 7mm x 7mm Chip-scale (QFN) and 44-pin Quad Flat Pack (PQFP) plastic packages. PIN CONFIGURATIONS (Top View) NOCONV RINB-40 RINB RINA RINA-40 GND TFIFO TEMPTY INSYNC SYNC0 SYNC1 -1 -2 -3 -4 -5 -6 -7 -8 -9 - 10 - 11 44 43 42 41 40 39 38 37 36 35 34 VDD C1C1+ V+ GND C2+ C2VTXHA FEATURES · Compliant with ARINC 717 and ARINC 573 standards · Operates from a single +3.3V supply with on-chip converters to provide proper voltages for both Harvard Bi-Phase (HPB) and Bi-Polar Return-to-Zero (BPRZ) outputs HI-3717PCI HI-3717PCT HI-3717PCM 33 32 31 30 29 28 27 26 25 24 23 - OUTHA TXOUTHA TXOUTHB OUTHB TXHB TXBA OUTBA TXOUTBA TXOUTBB OUTBB TXBB · One selectable receive channel as HBP or BPRZ with integrated analog line receiver · Both HBP and BPRZ transmitters have integrated line drivers as well as digital outputs 44 - Pin Plastic 7mm x 7mm Chip-Scale Package (QFN) VDD C1C1+ V+ GND C2+ C2VTXHA · 32-word by 12-bit FIFOs for both the receive and the transmit channel 7.5μs or 10μs · Digital transmitter outputs available for use with external line drivers 44 43 42 41 40 39 38 37 36 35 34 · Programmable slew rates on transmit channels: 1.5μs, - MATCH RFIFO ROVF MR RSEL GND SI SCK SO CS ACLK - 12 13 14 15 16 17 18 19 20 21 22 · Programmable bit rates: 384, 768, 1536, 3072, 6144, 12288, 24576, 49152 and 98304 bits/sec (32, 64, 128, 256, 512, 1024, 2048, 4096 and 8192 words/sec) · Enhanced Sync detection allows multiple false sync marks in user data while still synchronizing within 8 seconds · Fast SPI transmitter write and receiver read modes · Match pin flags when preprogrammed word count / subframe is received NOCONV RINB-40 RINB RINA RINA-40 GND TFIFO TEMPTY INSYNC SYNC0 SYNC1 -1 -2 -3 -4 -5 -6 -7 -8 -9 - 10 - 11 HI-3717PQI HI-3717PQT HI-3717PQM 33 32 31 30 29 28 27 26 25 24 23 - OUTHA TXOUTHA TXOUTHB OUTHB TXHB TXBA OUTBA TXOUTBA TXOUTBB OUTBB TXBB · Frame / subframe word count indicator · Industrial and Extended temperature ranges · Burn-in available 44 - Pin Plastic Quad Flat Pack (PQFP) ( DS3717 Rev. B) HOLT INTEGRATED CIRCUITS www.holtic.com MATCH RFIFO ROVF MR RSEL GND SI SCK SO CS ACLK - 12 13 14 15 16 17 18 19 20 21 22 11/11 HI-3717 BLOCK DIAGRAM VDD TXHA 5Ω OUTHA TXOUTHA TXOUTHB Transmit 32 x 12-BIT FIFO Transmit Rate Selection HBP Encoder Slew Rate & Loopback Test Control BPRZ Encoder Line Driver 37.5Ω 37.5Ω 5Ω OUTHB TXHB TXBA 5Ω Line Driver 37.5Ω 37.5Ω 5Ω OUTBA TXOUTBA TXOUTBB OUTBB TXBB NOCONV Transmit FIFO Status Register TXFSTAT +3.3V V+ V+ VV47uF MR SCK CS SI SO ARINC 717 Clock Divider Control Register 0 CTRL0 Control Register 1 CTRL1 SPI Interface DC / DC Converter C1+ C1C2+ ACLK C2- 47uF 0.47uF 2.2uF RSEL Receive FIFO Status Register RXFSTAT FIFO Status Pin Assignment Register FSPIN Word Count Utility Register WRDCNT MATCH RFIFO TFIFO HBP Line Receiver RINA RINB RINA-40 RINB-40 40 KΩ 40 KΩ TEMPTY HBP / BPRZ Data Sampler HBP / BPRZ Clock Recovery & Decoder SYNC Detect RECEIVE 32 x 12-BIT FIFO ROVF BPRZ Line Receiver INSYNC SYNC1 SYNC0 GND FIGURE 1. HOLT INTEGRATED CIRCUITS 2 HI-3717 PIN DESCRIPTIONS SIGNAL NOCONV RINB-40 RINB RINA RINA-40 GND TFIFO TEMPTY INSYNC SYNC0 SYNC1 MATCH RFIFO ROVF MR RSEL SI SCK SO CS ACLK TXBB OUTBB TXOUTBB TXOUTBA OUTBA TXBA TXHB OUTHB TXOUTHB TXOUTHA OUTHA TXHA VC2C2+ V+ C1+ C1VDD FUNCTION INPUT INPUT INPUT INPUT INPUT POWER OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT OUTPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CONVERTER CONVERTER CONVERTER CONVERTER CONVERTER CONVERTER POWER DESCRIPTION Disables on-chip DC-DC voltage converter Alternate receiver negative input. Requires external 40K ohm resistor Receiver negative input. Direct connection to ARINC 717 bus (BPRZ or HBP) Receiver positive input. Direct connection to ARINC 717 bus (BPRZ or HBP) Alternate receiver positive input. Requires external 40K ohm resistor Chip 0V Supply (All GND pins on package must be connected) Output is user programmable to indicate the Transmit FIFO Full or Half-full state. See FSPIN, in Table 7, FIFO Status Pin Assignment Register. Output goes high when the transmit FIFO is empty Output goes high when the receiver is synchronized to the incoming data. Synchronization occurs at the next valid sync mark following the detection of the proper number and order of consecutively spaced sync marks. See Table 3. Output in conjunction with SYNC1 output indicates when each of the four ARINC 717 subframe sync words are received. Only valid when the INSYNC pin is high. Output in conjunction with SYNC0 output indicates when each of the four ARINC 717 subframe sync words are received. Only valid when the INSYNC pin is high. Output goes high when the value of the Frame Word Count Register matches the value in the Frame Count Utility Register, WRDCNT. Output is user programmable to indicate the Receive FIFO Full, Half-full or Empty state. See FSPIN in Table 7, FIFO Status Pin Assignment Register. Receive FIFO Overflow. Output goes high when an attempt is made to load a full Receive FIFO Master Reset, active low Selects either HBP or BPRZ Receiver. OR’d with RXSEL bit in Control Register 0 SPI interface serial data input SPI Clock. Data is shifted into SI and out of SO when CS is low. SPI Interface seral data output Chip Select. Data is shifted into SI and out of SO using SCK when CS is low Master timing source for receiver and transmitters. 24 MHZ ±0.1% Bi-Polar Return-to-Zero (BPRZ) digital low output (external line driver required) Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Requires external 32.5 ohm resistor Bi-Polar Return-to-Zero (BPRZ) Line Driver low output. Direct connect to ARINC 717 bus Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Direct connect to ARINC 717 bus Alternate Bi-Polar Return-to-Zero (BPRZ) Line Driver high output. Requires external 32.5 ohm resistor Bi-Polar Return-to-Zero (BPRZ) digital high output (external line driver required) Harvard Bi-Phase (HBP) digital low output (external line driver required) Alternate Harvard Bi-Phase (HBP) Line Driver low output. Requires external 32.5 ohm resistor Harvard Bi-Phase (HBP) Line Driver low output. Direct connect to ARINC 717 bus Harvard Bi-Phase (HBP) Line Driver high output. Direct connect to ARINC 717 bus Alternate Harvard Bi-Phase (HBP) Line Driver high output. Requires external 32.5 ohm resistor Harvard Bi-Phase (HBP) digital high output (external line driver required) DC/DC converter negative voltage DC/DC converter fly capacitor for VDC/DC converter fly capacitor for VDC/DC converter positive voltage DC/DC converter fly capacitor for V+ DC/DC converter fly capacitor for V+ Chip +3.3V Supply Internal Pull-up / Down 50KΩ pull-down 50KΩ pull-up 50KΩ pull-down 50KΩ pull-down 50KΩ pull-down 50KΩ pull-up 50KΩ pull-down TA B L E 1 . H OLT INTEGRATED CIRCUITS 3 HI-3717 SERIAL PERIPHERAL INTERFACE (SPI) SPI BASICS The HI-3717 uses an SPI (Serial Peripheral Interface) for host access to internal registers and data FIFOs. Host serial communication is enabled through the Chip Select (CS) pin, and is accessed via a four-wire interface consisting of Serial Data Input (SI) from the host, Serial Data Output (SO) to the host and Serial Clock (SCK). All read / write cycles are completely self-timed. The SPI protocol specifies master and slave operation; the HI-3717 operates as an SPI slave. The SPI protocol defines two parameters, CPOL (clock polarity) and CPHA (clock phase). The possible CPOL-CPHA combinations define four possible “SPI Modes”. Without describing details of the SPI modes, the HI-3717 operates in Mode 0 where input data for each device (master and slave) is clocked on the rising edge of SCK, and output data for each device changes on the falling edge (CPHA = 0, CPOL = 0). The host SPI logic must be set for Mode 0 for proper communications with the HI-3717 . As seen in Figure 2, SPI Mode 0 holds SCK in the low state when idle. The SPI protocol transfers serial data as 8-bit bytes. Once CS is asserted, the next 8 rising edges on SCK latch input data into the master and slave devices, starting with each byte's most-significant bit. A rising edge on CS terminates the serial transfer and re-initializes the HI-3717 SPI for the next transfer. If CS goes high before a full byte is clocked by SCK, the incomplete byte clocked into the device SI pin is discarded. In the general case, both master and slave simultaneously send and receive serial data (full duplex), per Figure 2 below. However the HI-3717 operates half duplex, maintaining high impedance on the SO output, except when actually transmitting serial data. When the HI-3717 is sending data on SO during read operations, activity on its SI input is ignored. Figure 3 and Figure 4 show actual behavior for the HI-3717 SO output. HI-3717 SPI INSTRUCTIONS Instruction op codes are used to read, write and configure the HI-3717. Each SPI read or write operation begins with an 8-bit instruction. When CS goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the first rising edge. The op code is shifted into the SI pin, most significant bit (MSB) first. The SPI can be clocked up to10 MHz. The SPI instructions are of a common format. The most significant bit (MSB) specifies whether the instruction is a write “0” or read “1” transfer. R /W X MSB 7 6 X 5 X 4 X 3 X 2 X 1 X 0 LSB SPI INSTRUCTION FORMAT For write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising SCK edge. Data word length varies depending on word type written: 8-bit Control & Status Register writes, 16-bit Word Count Utility Register writes and 16-bit Transmit FIFO writes. For read instructions, the most significant bit of the requested data word appears at the SO pin at the next falling SCK edge after the last op code bit is clocked into the decoder. As in write instructions, the data field bit-length varies with read instruction type. Since HI-3717 operates in half-duplex mode, the host discards the dummy byte it receives while serially transmitting the instruction op code to the HI-3717. SCK (SPI Mode 0) SI SO CS High Z MSB MSB LSB LSB High Z FIGURE 2. Generalized Single-Byte Transfer Using SPI Protocol Mode 0 HOLT INTEGRATED CIRCUITS 4 HI-3717 Figure 3 and Figure 4 show read and write timing as it appears for a single-byte and dual-byte register operation. The instruction op code is immediately followed by a data byte comprising the 8-bit data word read or written. For a register read or write, CS is negated after the data byte is transferred. Table 2 summarizes the HI-3717 SPI instruction set. Note: SPI Instruction op-codes not shown in Table 2 are “reserved” and must not be used. Further, these op-codes will not provide meaningful data in response to a read instruction. Two instruction bytes cannot be “chained”; CS must be negated after each instruction, and then reasserted for the following Read or Write instruction. 0 SCK MSB 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LSB SI Op-Code Byte SO High Z Data Byte CS Host may continue to assert CS here to read sequential byte(s) when allowed by the instruction. Each byte needs 8 SCK clocks. MSB LSB MSB High Z FIGURE 3. Single-Byte Read From a Register 0 SCK SPI Mode 0 MSB 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 LSB MSB LSB MSB LSB SI Op-Code Byte SO High Z Data Byte 0 Data Byte 1 CS Host may continue to assert CS here to write sequential byte(s) when allowed by the SPI instruction. Each byte needs 8 SCK clocks. FIGURE 4. 2-Byte SPI Write Example H OLT INTEGRATED CIRCUITS 5 HI-3717 OP Code R/W 0x64 0x62 0x6A 0x72 0x74 0x2* 0xE4 0xE2 0xE6 0xE8 0xEA 0xF2 0xF6 0xFE 0xC* W W W W W W R R R R R R R R R # Data bytes 1 1 1 2 2 1 1 1 1 1 1 2 2 4 1 Write Control Register 0 DESCRIPTION Write Control Register 1 Write Receiver FIFO Status Pin Assignment Register Write Word Count Utility Register Write Transmit FIFO word Fast Write Transmit FIFO Word Read Control Register 0 Read Control Register 1 Read Receive FIFO Status Register Read Transmit FIFO Status Register Read Receive FIFO Status Pin Assignment Register Read Word Count Utility Register Read Receive FIFO Word Read Receive FIFO Word and Word Count Fast Read Receive FIFO * In the case of FAST instructions, the last four bits of the instruction byte are data TABLE 2. SPI Instruction Set REGISTER DESCRIPTIONS 1 BR 0 32 W SL PS E SL W1 E R W0 XS EL CONTROL REGISTER 0: CTRL0 BR Read: SPI Op-code 0xE4 Write: SPI Op-code 0x64 X 76 MSB 5 4 3 2 1 0 LSB Bit 7 6-4 Name BR2:0 R/W Default Description R/W R/W 0 0 Not Used. Always reads a “0” Setting these bits sets the ARINC 717 data rate for both the receive and transmit data. 000 768 Bits/sec. ( 64 words/sec.) 001 1536 Bits/sec. (128 words/sec.) 010 3072 Bits/sec. (256 words/sec.) 011 6144 Bits/sec. (512 words /sec.) 100 12288 Bits/sec. (1024 words/sec.) 101 24576 Bits/sec. (2048 words/sec.) 110 49152 Bits/sec. (4096 words/sec.) 111 98304 Bits/sec. (8192 words/sec.) Setting this bit overrides the state of BR2:0 and sets the data rate at 384 Bits/sec. (32 words/sec.) Setting these bits controls the nominal slew rate on both the HBP & BPRZ transmit channel outputs. 00 7.5 µs 01 10.0 µs ( Same as ARINC 429 Low Speed) 10 10.0 µs ( Same as ARINC 429 Low Speed) 11 1.5 µs ( Same as ARINC 429 High Speed) Selects either the HBP (”0”) or BPRZ (”1”) Receiver. This bit is logically OR’d with the RSEL input pin. 3 2-1 32WPS SLEW1:0 R/W R/W 0 0 0 RXSEL R/W 0 TABLE 3. HOLT INTEGRATED CIRCUITS 6 BR 2 HI-3717 REGISTER DESCRIPTIONS (cont.) CONTROL REGISTER 1: CTRL1 Read: SPI Op-code 0xE2 Write: SPI Op-code 0x62 XXXX 76 MSB 5 4 3 2 1 0 LSB C N NC T SY SY T STO S SR SF N TE Bit 7-4 3 2 1 Name SRST SFTSYNC NOSYNC R/W Default Description R/W R/W R/W R/W 0 0 0 0 Not Used, Always reads a “0” Software Reset - Setting this bit to “1” empties all the FIFO’s, clears the Sync detection logic and sets the analog line drivers to Hi-Z state. All other register bits remain unchanged. Software Synchronization - Setting the bit to “1” will result in the INSYNC output pin going high when the third of three consecutively occurring sync marks is detected. No Synchronization - Setting this bit to “1” will result in all data captured being loaded into the receive FIFO. WARNING: In this mode there is no way the HI-3717 can determine frame or subframe boundaries. This sync mode overrides all the other sync modes when set to “1”. Test Mode - A “1” in this bit position will disable the line receiver and both line drivers and the digital transmitted data will be looped back to the HBP or BPRZ data sampler selected by RXSEL . 0 TEST R/W 0 TABLE 4. LL U 3 RECEIVE FIFO STATUS REGISTER: RXFSTAT Read: SPI Op-code 0xE6 Write: Read Only C N C1 C0 SY YN YN IN S S 76 MSB 5 Y F PT F V AL H FEM FO EST F RRRT 2 1 0 LSB XXXXXXXX 4 Bit 7 Name INSYNC R/W Default Description R 0 Receive channel sync indicator. The bit is set to”1” when synchronization is achieved on the receive channel. Normal synchronization occurs when four consecutive valid sync marks (Octal 1107, 2670, 5107 and 6670 respectively) are received exactly 1 second apart. The bit is set when the next valid and properly spaced subframe sync mark (Octal 1107) is detected. Software Synchronization (CTRL1 = “1”) occurs when two consecutively valid sync marks are received exactly 1 second apart and in the proper order but the first sync mark does not have to be Octal 1107. The bit is set when the next valid and properly spaced subframe sync mark is detected. The bit remains set until synchronization is lost at which time the device automatically attempts to re-synchronize. No data is passed to the receive FIFO until Synchronization is re-established. Existing data in the FIFO remains intact and can be read at any time. 6-5 SYNC0:1 R 0 The two bits are a realtime indicators of when each of the four ARINC 717 subframe sync marks are received. They are updated when the sync mark is detected and passed to the Receive FIFO. The two bits are only valid when INSYNC is “1” 00 Subframe SYNC1 mark received (Octal 1107) 01 Subframe SYNC2 mark received (Octal 2670) 10 Subframe SYNC3 mark received (Octal 5107) 11 Subframe SYNC4 mark received (Octal 6670) Bit is set when the Receive FIFO contains 32 words. Bit is set when the Receive FIFO contains exactly 16 words. Bit is set when the Receive FIFO is empty. It is reset to”0” when the first valid word is passed to the Receive FIFO. FIFO Overflow bit and ROVF pin are set to “1” when devices attempts to load a valid word to a full Receive FIFO. The Receive FIFO will ignore additional words if it is full. Not used, Always reads “0” 4 3 2 1 0 RFFULL RFHALF RFEMPTY RFOVF - R R R R R 0 0 1 0 0 TABLE 5. HOLT INTEGRATED CIRCUITS 7 R FF HI-3717 REGISTER DESCRIPTIONS (cont.) FF F 4 Read: SPI Op-code 0xE8 Write: Read Only Bit 7 6 5 4-0 Name TFFULL TFHALF TFEMPTY R/W Default Description R R R R 0 0 1 0 XXXXXXXX 76 MSB 5 3 2 1 0 LSB Set when the Transmit FIFO contains 32 words Set when the Transmit FIFO contains exactly 16 words Set when the Transmit FIFO is empty. Reset to “0” when at least one word is loaded to the Transmit FIFO. Not used, Always reads “0” TABLE 6. FIFO STATUS PIN ASSIGNMENT REGISTER: FSPIN Read: SPI Op-code 0xEA Write: SPI Op-code 0x6A Bit 7-6 Name RFIFO1:0 R/W Default Description R/W 0 These bits program which Receive FIFO Status Register bit is represented by the RFIFO pin . 00 RFIFO pin is set “1” when Receive FIFO Status Register Bit 2, RFEMPTY, is “1”. 01 RFIFO pin is set “1” when Receive FIFO Status Register Bit 3, RFHALF, is “1”. 10 RFIFO pin is set “1” when Receive FIFO Status Register Bit 3, RFHALF, is “1”. 11 RFIFO pin is set “1” when Receive FIFO Status Register Bit 4, RFFULL, is “1”. The bit programs which Transmit FIFO Status Register bit is represented by the TFIFO pin. 0 TFIFO pin is set “1” when Transmit FIFO Status Register Bit 7, TTFULL, is “1”. 1 TFIFO pin is set “1” when Transmit FIFO Status Register Bit 6, TFHALF, is “1”. Not used, Always reads “0” 0 FO O FI FI FIF RRT FO 76 MSB 5 U XXXXXXXX 4 3 2 1 0 LSB 5 TFIFO R/W 0 4-0 - R 0 TABLE 7. WORD COUNT UTILITY REGISTER: WRDCNT Read: SPI Op-code 0xF2 Write: SPI Op-code 0x72 C C FF F U LL 1 LL TRANSMIT FIFO STATUS REGISTER: TXFSTAT Y TY F PT FW LL LF P AL M OV ST FU HA FEM HE TF TF T FF FF FF TE Y F PT FW AL M OV ST HE FF FF FF TE XXXXXXXX 15 14 13 12 11 10 9 MSB 8 XXXXXXXX 7 6 5 4 3 2 1 0 LSB The Word Count Utility Register can be programmed to generate an interrupt on the MATCH pin when the data for the specified word count of the specified subframe is loaded into the Receive FIFO. The Word Count Utility Register can used with any of the standard ARINC 717 data rate and all of the expanded data rates, except 8192 wps. Bit 15 - 3 Name C12:0 R/W Default Description R/W 0 Subframe Word Count - The value is compared to the current word count in the Receive FIFO and sets the MATCH pin to “1” whenever there is a match. The MATCH pin will stay at “1” for one word time. Not used, Always reads “0” Subframe ID 00 Subframe One 01 Subframe Two 10 Subframe Three 11 Subframe Four 2 1-0 S1:0 R/W R/W 0 0 TABLE 8. H OLT INTEGRATED CIRCUITS 8 C 12 C 11 C10 C 8 C 7 C6 C5 C 4 C 3 C2 Y PT M E 0 O C FF S1 S 9 1 HI-3717 ARINC 717 MESSAGE AND BIT ORDERING ARINC 717 messages consist of 12-bit words sent in a 4 second frame divided into four 1 second subframes. Each subframe consists of 64 (basic rate), 128, 256, 512, 1024, 2048, 4096 or 8192 12 bit words, depending on the data rate of the target system. The first word of each subframe contains a unique Barker Code synchronization pattern that identifies the subframe. The octal synchronization code for subframes 1 through 4 are 1107, 2507, 5107 and 6670 respectively. The first 12- bit word of a subframe that appears on the ARINC 717 bus is the synchronization code with the least significant bit (LSB) first. This is immediately followed by up to 8191 12-bit data words, all within1 second from the start of the synchronization code. The next three subframes immediately follow the first subframe with their synchronization code as the first 12-bit word of the subframe followed by the same number of data words as the first subframe. ARINC 717 data is transmitted between the HI-3717 and host microcontroller using the four-wire Serial Peripheral Interface (SPI). A read or write operation consists of a single-byte op-code followed by 8-bit data words. Figure 5 shows examples of how the SPI data bytes are mapped to the ARINC 717 message. ARINC717 Message as received / transmitted on the ARINC 717 serial bus Frame Subframe 1 LSB MSB LSB Subframe 2 MSB LSB Subframe 3 MSB LSB Subframe 4 MSB 1 Second 1 Second 4 Seconds 1 Second 1 Second ARINC717 Subframe Format 1st Subframe Sync Code (1107) 111000100100 LSB MSB LSB 2nd Data Word 0 1 2 3 4 5 6 7 8 9 10 11 MSB LSB Nth Data Word 0 1 2 3 4 5 6 7 8 9 10 11 MSB 1 Second time ARINC 717 Message as transferred on the SPI bus SPI Op-Code 01110100 MSB LSB Don’t Care Subframe Sync or Data Word Bits 76543210 LSB X X X X 11 10 9 8 MSB Example 1. Write Transmit FIFO Subframe Sync or Data Word (Op-Code 0x74). SPI Op-Code 11100110 MSB LSB Always “0” Subframe Sync or Data Word Bits 76543210 LSB 0 0 0 0 11 10 9 8 MSB Example 2. Read Receive FIFO Subframe Sync or Data Word (Op-Code 0xF6). SPI Op-Code Subframe Sync or Data Word Bits 0 0 1 0 11 10 9 8 MSB 76543210 LSB Example 3. Fast Write Transmit FIFO Subframe Sync or Data Word (Op-Code 0x2-) . SPI Op-Code 01110010 MSB LSB Word Count Bits 12 11 10 9 8 7 6 5 MSB Sync Bits 43210X10 LSB Example 4. Write Word Count Utility Register, WRDCNT (Op-Code 0x72). SPI Op-Code 11111110 MSB LSB Always “0” Subframe Sync or Data Word Bits 76543210 LSB Word Count Bits 12 11 10 9 8 7 6 5 MSB Sync Bits 0 0 0 0 11 10 9 8 MSB 43210010 LSB Always “0” Example 5. Read Receive FIFO Data Word with Word Count (Op-Code 0xFE). FIGURE 5. ARINC 717 & SPI Bit Ordering HOLT INTEGRATED CIRCUITS 9 HI-3717 FUNCTIONAL DESCRIPTION OVERVIEW ARINC 717 is a continuous transmission of 12-bit words in 4 second frames divided into four 1 second subframes. The programmed data rate (32 to 8192 wps) determines the number of words per subframe. The first word of each subframe is reserved for a unique sync mark. Figure 5 illustrates the relationship between ARINC 717 frames, subframes and words. The HI-3717 is comprised of independent ARINC 717 receive and transmit sections easily accessible via a four wire SPI communications bus. It supports the ARINC 717 Harvard Bi-Phase (HBP) protocol as well as the Bi-Polar Return to Zero (BPRZ) auxiliary protocol. The receiver accepts data from either a Harvard Bi-Phase (HBP) or a Bi-Polar Return to Zero (BPRZ) bus, recovers the clock, decodes the data, synchronizes the ARINC 717 data frames using the unique subframe sync marks and stores the recovered data in a 32 word x 12 bit Receive FIFO. The ARINC 717 Transmitter accesses data from a 32 word x 12 bit Transmit FIFO, encodes it into both HBP and BPRZ data streams at the selected data rate, and converts the digital data stream to ARINC 717 bus compatible outputs. There are separate outputs for the HBP and BPRZ ARINC 717 buses. The receive and transmit sections operate at the same data rate and they are configured and monitored via the SPI interface. Refer to Figure 1 for the Block Diagram of the HI-3717 In order to avoid inadvertent transceiver operation, Control Register 0, CTRL0, should be programmed last. Writing CTRL0 sets the desired data rate which, after one bit period, the internal clocks are enabled. This in turn makes the transmitter or receiver operational. Changing the data rate on the fly may result in unpredictable operation during the transition to the new programmed state. A full reset, POR or MR, should be issued before reprogramming the data rate. Data Rate For correct ARINC 717 date rate reception, transmission and bit timing, the HI-3717 requires a 24 MHz reference clock source applied to the ACLK input. This clock is divided down to achieve the data rate programmed with CNTL0. The input receive data is 8X oversampled relative to the programmed data rate. ARINC 717 requires a basic data rate of 64 wps with support for 128, 256 and 512 wps. The HI-3717 offers an expanded range of 32 to 8192 wps for testing purposes and future expansion. CTRL0, 32WPS, overrides the state of CTRL0 and sets the data rate to 32 wps. The required 0.1% timing tolerance is maintained over all data rates. Line Driver Output Slew Rates The slew rate of the HBP and BPRZ outputs is controllable with CNTR0. A 7.5µs slew rate conforms to all the required ARINC 717 data rates. In addition, a 1.5µs is provided for the higher data rates and a 10µs for the 32 wps data rate. Receiver Format INITIALIZATION AND RESET The HI-3717 generates a full reset upon application power. The power-on-reset (POR) sets all registers to their default values, places the Receive and Transmit FIFOs to their empty state, and clears the sync detection logic. It also sets both the HBP and BPRZ outputs to the high impedance state and the input sampling and decoders are disabled. See Register Descriptions for complete definition of the default values. The part can also be initialized to the full reset state by applying a 100ns active low pulse to the external MR pin. A software reset is also possible via the SPI communications interface by writing a “1” to the CTRL1. This bit places both the Receive and Transmit FIFO’s in the empty state, clears the sync detection logic, and sets both the HBP and BPRZ line drivers to a high impedance state. All other registers remain unchanged. The device is held in the reset state until a “0” is written to CTRL1. The ARINC 717 format of the receiver is selectable as HBP or BPRZ by the state in CNTL0, RXSEL, OR’d with the state of the external RSEL input pin. A “0” on RSEL and CNTL0 selects HBP and a “1” on either RSEL or CNTL0 selects BPRZ. Refer to Table 3 for the detail description of each bit in Control Register 0. Input Synchronization Mode The HI-3717 has three different synchronization modes, depending on how it is being used. 1. Flight Recorder Mode This is the normal synchronization mode. In this mode the HI-3717 searches for the four subframe sync marks: SYNC1 = Octal 1107 SYNC2 = Octal 2670 SYNC3 = Octal 5107 SYNC4 = Octal 6670 in the correct sequential order starting from SYNC1 and the exact bit time determined by the programmed word rate. When synchronization is achieved the INSYNC pin as well as the INSYNC bit of the Receive FIFO Status Register, RXFSTAT are set to “1” on the next valid SYNC1 mark. The valid SYNC1 mark and following data words are stored in the Receive FIFO. Sync time varies from 4 seconds to a worst case of 8 seconds for a valid data stream. CONFIGURATION The HI-3717 is configured via the SPI communications bus by writing to Control Register 0, CTRL0, and Control Register 1, CTRL1. They are reset to 0x00 following a Power On Reset (POR) or a Master Reset (MR) but remain unchanged on a Software Reset, CTRL1, SRST. The function of each register bit is shown in the Register Descriptions. H OLT INTEGRATED CIRCUITS 10 HI-3717 FUNCTIONAL DESCRIPTION (cont.) The first word stored in the Receive FIFO is available when RXFSTAT, RFEMPTY, is reset to “0”, which is 12-bit periods (one word time) after INSYNC is set to “1”. The HI-3717 remains in sync as long as the proper sync sequence is maintained. INSYNC is reset to “0” when the next expected subframe sync mark is not present. The HI-3717 will initiate a new synchronization process at the next valid SYNC1 mark. Once the part falls out of sync, the whole previous subframe should be discarded. 2. Test Mode In this mode the HI-3717 searches for any two subframe sync marks in the correct sequential order and the exact starting time for the sync mark. INSYNC is set to “1” when the third valid sync mark is detected. The part must continue to detect each sync mark in the correct order and with the correct starting time to stay in sync. This method reduces the time required to obtain sync to about 2 seconds typical and a worst case of 3 seconds. 3. No Sync Detect Mode In this mode, the INSYNC is set to “1” and all data is stored in the Receive FIFO. Without sync detection, the Receive FIFO just records the sequential bits, not words, from the bus. It is up to the user to detect the sync marks and determine the word boundaries in this mode. In both the Flight Recorder Mode and the Test Mode, the HI-3717 uses a proprietary sync tracking and detection method which allows multiple random false sync marks in the user data without increasing the sync time. with RSEL pin or CTRL1, writing the transmit FIFO and reading the receive FIFO. All status pins and registers reflect the status of the loopback operation. FIFO Status Pin Assignment Register, FSPIN This register assigns the function of the external RFIFO and TFIFO pins. The RFIFO pin reflects the state of one of the three Receive FIFO status flags (RFFULL, RFHALF and RFEMPTY) in the Receive FIFO Status Register, RXFSTAT. The TFIFO pin reflects the state of one of two Transmit FIFO status flags (TFULL or TFHALF) in the TFXSTAT register. Refer to the FSPIN Register Description in Table 7 for register assignment details. Word Count Utility Register, WRDCNT The MATCH pin goes high when the HI-3717 is in the INSYNC condition and the word count and subframe count matches the value programmed in the Word Count Utility Register. Note: The INSYNC pin is set to “1” when the second consecutive SYNC1 mark of the proper sync sequence is received. The Word Count Utility Register and Match pin function can be used for the standard ARINC 717 data rates and all of the expanded data rates, except 8192 wps. ARINC 717 RECEIVER The input data stream for ARINC 717 can be one of two formats. The main ARINC 717 bus to a Digital Flight Data Recorder (DFDR) uses Harvard Bi-phase (HBP) encoding and the auxiliary output bus to an Aircraft Integrated Data System (AIDS) uses Bi-Polar Return to Zero (BPRZ) encoding as shown in Figure 6. The HI-3717 has an independent ARINC 717 receive channel with a selectable on-chip HBP analog line receiver for connection to the main incoming ARINC 717 data bus or a BPRZ analog line receiver for connection to an auxiliary data bus. The ARINC 717 specification requires the following detection levels for the HBP inputs: STATE HI NULL LO DIFFERENTIAL VOLTAGE +2 Volts to +8 Volts NA -2 Volts to -8 Volts Digital Loopback Normal HI-3717 operation is with CTRL1 set to “0”. Setting it to “1” places the part in digital loopback mode. In this mode the analog line receivers are disconnected from the data samplers and both output line drivers are placed in a high impedance state. The output encoders are connected to input sampler / decoder. The part may be verified by selecting the desired receive decode format +5V Harvard Bi-Phase -5V +10V Bi-Polar Return to Zero -10V Data LSB 1 0 1 1 0 1 0 1 0 0 1 1 MSB FIGURE 6. ARINC 717 HBP & BPRZ Differential Input Signal Format HOLT INTEGRATED CIRCUITS 11 HI-3717 FUNCTIONAL DESCRIPTION (cont.) The auxiliary BPRZ input detection levels are the same as standard ARINC 429 levels: STATE ONE NULL ZERO DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts For Havard Bi-phase, HBP, coding, the sampler validates a HI (One) or LO (Zero) if the signal is in that state for at least two samples. There is no Null state for the HBP format. The Bi-Polar Return to Zero, BPRZ, coding sampler validates that at least two consecutive Ones or two consecutive Zeroes are followed by at least two consecutive Null states. Decoders The decoder recovers the clock and resynchronizes each valid one or zero to the transition bit period. The Harvard Bi-phase, HBP, decoder confirms the sampler only provided a valid One or Zero, not both, then detects the presence of absence of an edge in the data bit period. The output of the decoder is a “1” if there was a transition, otherwise a “0”. The Bi-Polar Return to Zero, BPRZ, decoder confirms the sampler only provided a valid One or Zero, followed by a valid Null. The decoder output is a “1” for a valid One and “0” for a valid Zero. Once the data is captured, it is re-sampled to the recovered transition rate clock (sample clock sent to the sync detector) and resampled to recover the data bit rate clock. The decoders will operate correctly when the input data bit period is not more than 2 sample clocks (25%) larger or 1 sample clock (12.5%) smaller than the nominal value. The slower input frequency causes a mismatch between the sampled data and the recovered clock. The faster input frequency causes issues with internal edge detection logic. Any incorrectly decoded data will cause the next sync mark to be missed and the INSYNC bit to go to “0”. The HI-3717 guarantees recognition of these levels with a common mode voltage with respect to GND less than ±25V for the worst case conditions (3.15V supply, 8V HBP signal level and 13V BPRZ signal level). Design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the signal (including nulls) is outside the differential voltage ranges, the HI-3717 receiver rejects the data. Bit Timing & Input Sampling The bit timing for both the receive and transmit functions is the data rate programmed in CTRL0. The HI-3717 allows the following word / bit rates: 32 words/sec. 64 words /sec. 128 words/sec. 256 words/sec. 512 words /sec. 1024 words/sec. 2048 words/sec. 4096 words/sec. 8192 words/sec. = = = = = = = = = 384 Bits/sec 768 Bits/sec. 1536 Bits/sec. 3072 Bits/sec. 6144 Bits/sec. 12288 Bits/sec. 24576 Bits/sec. 49152 Bits/sec. 98304 Bits/sec. The 32 WPS data rate is typically used for testing purposes. The input data from the selected analog line receiver is oversampled at 8X relative to the word rate programmed in CTRL0. This is 4X oversample of the transition rate since the code rate for both methods is double the data rate. The sampler uses three separate shift registers, one each for Ones, Zero and Null detection. When the input signal is within the differential voltage range of one of the valid states (One, Zero or Null) of the selected data format, the sampler clocks “1” into that register and a “0” into the other two. When the signal is outside the differential voltage ranges defined for all the shift registers, a “0” is clocked into all three registers. Only one shift register can clock “1” for a given sample. The Null shift register is only used for the BPNZ format. RINA-40 VDD DIFFERENTIAL AMPLIFIERS COMPARATORS SYNC Detect The HI-3717 employs a proprietary, four level sync algorithm that samples each bit and compares each combination of 12-bits against the four valid ARINC 717 subframe sync marks. In the Flight Mode, once a valid SYNC1 mark is discovered, it continues to look for each of the next three subframe sync marks in the proper order and timing. If any one is not found, the search starts over looking for SYNC1 again. Once all four sync marks are detected in the proper order and location in a frame, the INSYNC pin is set to “1” at the next SYNC1 subframe sync mark if it is the correct value and it occurs at the proper relationship to the previous valid sync mark. This is the default synchronization mode for the HI-3717. In the Software Synchronization Mode, CTRL1 = “1”, once two consecutive valid subframe sync marks are detected, the INSYNC bit is set to “1” at the next consecutive valid subframe sync mark if it occurs at the proper relationship to the previous valid sync marks. The first valid subframe sync mark does not have to be SYNC1 in this mode but each successive subframe sync marks must be the next in the sequence and properly spaced from the preceding valid subframe sync mark. INSYNC is set to “0” when the next expected subframe sync mark is missed in the Flight Mode and Software Synchronization Modes. The HI-3717 sync detection logic is reset and the part initiates the full synchronization process again. The data from the subframe preceding the first incorrect subframe sync mark should be discarded. No data is passed to the Receive FIFO until synchronization is reestablished. RINA ONE GND VDD NULL ZERO RINB RINB-40 GND RSEL CNTL0 FIGURE 7. ARINC 717 Receiver Inputs H OLT INTEGRATED CIRCUITS 12 HI-3717 FUNCTIONAL DESCRIPTION (cont.) There are also two bits in the Receive FIFO Status Register, RXFSTAT that provide a realtime indicator when each of the four ARINC 717 subframe sync marks are received. The bits are valid only when INSYNC is “1” and are updated when the subframe sync word is loaded into the Receive FIFO. The final mode is No Synchronization, CRTL1 = “1”. In this mode data is captured and loaded directly to the Receive FIFO in the order it was received. It is the responsibility of the user to extract the data from the FIFO and determine word, frame and subframe boundaries. The INSYNC bit remains “0” while in this mode. Receive FIFO and Retrieving Data Data is transferred from the Receive FIFO starting with the valid subframe sync mark when INSYNC was set to “1” and continues with each consecutive 12-bit word until INSYNC is set to “0”. Each time a valid ARINC 717 word is loaded to the Receive FIFO the RFFULL, RFHALF and RFEMPTY bits in the Receive FIFO Status Register (RXFSTAT) are updated. Each word is retrieved from the Receive FIFO via the SPI interface using SPI Op-code instruction 0xF6 (word only), 0xFE (word & word count) or 0xC (Fast Read). The SPI read instruction 0xF6 format is an 8-bit op-code followed by two 8-bit data words. The four most significant bits (MSB) of the first data word are always “0” followed by the first four MSB of the ARINC 717 word. The second data word contains the remaining 8-bits of the ARINC 717 word. The least significant bit (LSB) of the ARINC 717 word is the LSB of the second 8-bit data word. The format for read word and word count instruction 0xFE is the same as the read instruction with the addition of two additional 8-bit data bytes that contain the word count and the corresponding sync subframe information. The third 8-bit SPI data byte contains the 8 MSB bits of the word count. The fourth data byte is comprised of remaining 5 bits of the word count as well as the two bit code for the subframe number in the same format as described in the RFXSTAT Register Description. Refer to Example 5 in Figure 5 for more details on the format for this instruction. The Fast Read instruction 0xC uses only one SPI data byte for a read operation. This is accomplished by using only first four bits for the SPI op-code and placing the first four most significant bits of the ARINC 717 word in the four remaining bit locations of what are normally part of an op-code. The remaining 8-bits of the ARINC 717 word are in a normal SPI data byte. This method use one less SPI data byte than a normal read instruction. Up to 32 ARINC 717 words may be held in the Receive FIFO. The RFFULL bit (RXFSTAT) is set to “1” when the Receive FIFO is full. Failure to unload the Receive FIFO when full will result in loss of new data words until there are less than 32 words in the FIFO. The RFOVF bit (RXFSTAT) and external FROV pin are set to “1” when an attempt is made to write to a full Receive FIFO. The Receive FIFO half-full flag, the RFHALF bit (RXFSTAT