HI-6121PCT

November, 2010 HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface (SPI) MIL-STD-1553 Remote Terminal ICs FEATURES • • GENERAL DESCRIPTION The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic silicon gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus interface for access to registers and RAM and is offered in a 100-pin plastic quad flat pack (PQFP). The HI-6121 has a 4-wire SPI (Serial Peripheral Interface) host connection and comes in a reduced pin count 52-pin PQFP or 9mm x 9mm 64-pin QFN. Both devices handle all aspects of the MIL-STD-1553 protocol, including message encoding, decoding, error detection, illegal command detection and data buffering. Host data management is simplified by storing message information and data within the onchip 32K x 16 static RAM. A descriptor table in shared RAM provides fully programmable memory management. Multiple descriptor tables can be implemented for fast context switching. Transmit and receive commands can use any of four different data buffer modes: indexed (single) buffering, pingpong (double) buffering or two circular buffer schemes. Transmit and receive commands for each subaddress may use different buffer modes. Mode code commands employ a simple scheme for storing mode data and message information with programmable interrupts. The device provides internal illegalization capability, allowing any subset of subaddress, command T/R bit, broadcast vs non-broadcast and word count (or mode code) to be illegalized, resulting in a total of 4,096 possible combinations. The illegalization table resides in internal RAM. The RT can also operate without illegal command detection, providing “in form” responses to all valid commands. Broadcast command recognition is optional. The HI-6120 and HI-6121 provide programmable interrupts for automatic message handling, message status and general status. A host interrupt history log maintains information about the last 16 interrupts. The HI-6120 and HI-6121 can be configured for automatic self-initialization. A dedicated SPI port reads data from external serial EEPROM memory to fully configure the descriptor table, illegalization table and host interrupts. Internal dual-redundant transceivers provide direct connection to bus isolation transformers. The device is offered with industrial temperature range as well as extended temperature range with optional burn-in. A “RoHS compliant” lead-free option is also offered. • • • • • • • • • Fully integrated 3.3V Remote Terminal meets all requirements for MIL-STD-1553B Notice 2 Four data buffer modes for subaddress transmit and receive commands. Data buffer modes are independently selectable for transmit and receive commands on each subaddress Simplified mode code command handling Integral 16-bit Time-Tag counter has programmable options for clock, interrupts and auto-synchronization Message information and time-tag words are stored with message data words for all transacted messages In compliance with MIL-STD-1553B Notice 2, received data from broadcast messages may be optionally separated from non-broadcast received data Optional interrupt log buffer stores the most recent 16 interrupts to minimize host service duties Optional illegal command detection uses internal table Optional automatic self-initialization at reset ±8kV ESD Protection (HBM, all pins) MIL-STD-1760 compliant PIN CONFIGURATION (TOP) 52 - TXINHB 51 - TXINHA 50 - AUTOEN 49 - VCC 48 - GND 47 - SSYSF 46 - ACTIVE 45 - READY 44 - TTCLK 43 - ACKINT 42 - INTMES 41 - INTHW 40 - BENDI COMP - 1 CE - 2 MODE - 3 SI - 4 SCK - 5 SO - 6 MCLK - 7 RTA0 - 8 RTA1 - 9 RTA2 - 10 MR - 11 RTA3 - 12 RTA4 - 13 HI-6121PQx HI-6121 in PQFP-52 Package 39 - TEST 38 - LOCK 37 - MTSTOFF 36 - BUSA 35 - VCCP 34 - BUSA 33 - BUSB 32 - VCCP 31 - BUSB 30 - TEST0 29 - TEST1 28 - TEST2 27 - TEST3 DS6120 Rev. B HOLT INTEGRATED CIRCUITS www.holtic.com 1 RTAP - 14 MISO - 15 MOSI - 16 VCC - 17 GND - 18 ECS - 19 EECOPY - 20 ESCK - 21 EE1K - 22 TEST7 - 23 TEST6 - 24 TEST5 - 25 TEST4 - 26 11/10 HI-6120, HI-6121 NOTES: HOLT INTEGRATED CIRCUITS 2 HI-6120, HI-6121 Table of Contents 1. BLOCK DIAGRAM ........................................................................................... 10 2. PIN DESCRIPTIONS ....................................................................................... 11 3. FUNCTIONAL OVERVIEW .............................................................................. 16 3.1. Shared RAM Utilization .............................................................................................. 16 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.5. 3.2.1. 3.2.2. 3.2.3. 3.2.4. 3.2.5. 3.2.6. Descriptor Table .......................................................................................................... 16 Illegalization Table ....................................................................................................... 16 Message Data Buffers................................................................................................. 16 Storage for Mode Code Commands ........................................................................... 16 Interrupt Log ................................................................................................................ 17 Clock Interrupts ........................................................................................................... 17 Remote Terminal Address Inputs ................................................................................ 17 Integral Time-Tag Counter........................................................................................... 17 Dual Bus Transceivers ................................................................................................ 17 Encoder and Decoders ............................................................................................... 17 Auto-Initialization Serial EEPROM Interface ............................................................... 17 3.2. Hardware Feature Summary ...................................................................................... 17 4. MEMORY AND REGISTER ADDRESSING ..................................................... 18 5. REGISTERS..................................................................................................... 20 5.1. Configuration Register 1 (0x0000)............................................................................ 21 5.2. Configuration Register 2 (0x0001)............................................................................ 24 5.3. Operational Status Register (0x0002) ...................................................................... 28 5.4. Current Command Register (0x0003) ...................................................................... 30 5.5. Current Control Word Address Register (0x0004) .................................................... 30 5.6. Descripter Table Base Address Register (0x0005) .................................................. 30 5.7. Pending Interrupt Register (0x0006) ........................................................................ 31 5.8. 1553 Status Word Bits Register (0x0007) ................................................................ 33 5.9. Time-Tag Register (0x0008) ..................................................................................... 34 5.10. Interrupt Log Address Register (0x0009).................................................................. 35 5.11. Current Message Information Word Address Register (0x000A) ............................. 35 5.12. Memory Address Pointer Register (HI-6121 only) (0x000F) ................................... 36 5.13. Interrupt Enable Register (0x0010) .......................................................................... 36 HOLT INTEGRATED CIRCUITS 3 HI-6120, HI-6121 5.14. Time-Tag Utility Register (0x0011)............................................................................ 38 5.15. Bus A Select Register (0x0012) ................................................................................ 39 5.16. Bus B Select Register (0x0013) ............................................................................... 39 5.17. Built-in Test Word Register (0x0014) ........................................................................ 40 5.18. Alternate Built-in Test Word Register (0x0015) ........................................................ 41 5.19. Reserved Register (0x0016)..................................................................................... 41 5.20. Test Control Register (0x0017) ................................................................................ 41 5.21. Loopback Test Transmit Data Register (0x0018) ..................................................... 45 5.22. Loopback Test Receive Data Register (0x0019) ...................................................... 45 6. COMMAND RESPONSES ............................................................................... 46 6.1. RT to RT Commands. ................................................................................................ 47 7. COMMAND ILLEGALIZATION TABLE ............................................................. 48 8. TEMPORARY RECEIVE DATA BUFFER......................................................... 52 9. INTERRUPT LOG BUFFER ............................................................................. 52 10. DESCRIPTOR TABLE ...................................................................................... 55 10.1. Receive Subaddress Control Word ............................................................................ 57 10.2. Transmit Subaddress Control Word ........................................................................... 60 10.3. Data Buffer Options for Mode Code Commands ........................................................ 62 10.4. Receive Mode Control Word ...................................................................................... 63 10.5. Transmit Mode Control Word...................................................................................... 65 11. MESSAGE DATA BUFFERS ............................................................................ 69 11.1. Subaddress Message Information Words ................................................................. 70 11.1.1. Receive Subaddress Command ................................................................................ 70 11.1.2. Transmit Subaddress Command ............................................................................... 72 11.2. Mode Command Message Information Words ........................................................... 73 11.2.1. Receive Mode Command ........................................................................................... 73 11.2.2. Transmit Mode Command .......................................................................................... 75 11.3. Ping-Pong Data Buffering ........................................................................................... 78 11.3.1. Double Buffered (Ping-Pong) Mode ............................................................................ 78 11.3.2. Ping-Pong Enable / Disable Handshake ..................................................................... 78 11.3.3. Broadcast Message Handling in Ping-Pong Mode ..................................................... 80 11.4. Indexed Data Buffer Mode.......................................................................................... 82 11.4.1. Single Message Mode................................................................................................. 82 HOLT INTEGRATED CIRCUITS 4 HI-6120, HI-6121 11.4.2. Broadcast Message Handling in Index Mode ............................................................. 82 11.5. Circular Buffer Mode 1................................................................................................ 86 11.6. Circular Buffer Mode 2................................................................................................ 90 12. MODE COMMAND PROCESSING.................................................................. 95 12.1. General Considerations .............................................................................................. 95 12.2. Mode Command Interrupts ......................................................................................... 95 12.3. Mode Command Data Words ..................................................................................... 95 12.4. Standard Mode Command Processing....................................................................... 98 12.5. Simplified Mode Command Processing...................................................................... 98 13. INTERRUPT MANAGEMENT .......................................................................... 99 13.1. Host Message Detection Options ............................................................................... 99 13.2. Host Interrupt Generation ........................................................................................... 99 13.2.1. Interrupt Log Address Register ................................................................................. 100 13.2.2. Interrupt Address Word (IAW) ................................................................................... 100 13.2.3. Interrupt Identification Word (IIW) ............................................................................ 100 14. RESET AND INITIALIZATION ........................................................................ 101 14.1. Master Reset using the MR pin and Optional Auto-Initialization............................... 101 14.2. Software Reset ......................................................................................................... 105 14.3. Reset Remote Terminal Mode Code ........................................................................ 105 14.4. Serial EEPROM Programming Utility ...................................................................... 105 15. HOST INTERFACE ........................................................................................ 107 15.1. HI-6120 Host Bus Interface ...................................................................................... 107 15.1.1. Bus Wait States and Data Prefetch........................................................................... 107 15.2. HI-6121 Serial Peripheral Interface .......................................................................... 108 15.2.1. Serial Peripheral Interface (SPI) Basics ................................................................... 108 15.2.2. HI-6121 SPI Commands ........................................................................................... 109 15.2.3. Fast-Access Commands for Registers 0-15 ............................................................ 109 15.2.4. Indirect Addressing of RAM and Registers .............................................................. 109 15.2.5. Data Prefetch for SPI Read Cycles ............................................................................111 15.2.6. Special Purpose Commands......................................................................................111 15.2.7. Descriptor Table Prefetch Exceptions ....................................................................... 113 16. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS ... 117 17. ELECTRICAL CHARACTERISTICS .............................................................. 144 HOLT INTEGRATED CIRCUITS 5 HI-6120, HI-6121 17.1. Absolute Maximum Ratings ...................................................................................... 144 17.2. Recommended Operating Conditions ...................................................................... 144 17.3. DC Electrical Characteristics .................................................................................... 144 17.4. AC Electrical Characteristics ― HI-6121 Host Bus Interface Timing........................ 145 17.5. AC Electrical Characteristics ― HI-6120 Host Bus Interface Timing........................ 146 18. MIL-STD-1553 BUS INTERFACE .................................................................. 151 19. THERMAL CHARACTERISTICS ................................................................... 152 20. ADDITIONAL PIN / PACKAGE CONFIGURATIONS ..................................... 152 20.1. HI-6121PCx (64-pin QFN) ........................................................................................ 152 20.2. HI-6120PQx (100-pin QFN) ...................................................................................... 153 21. ORDERING INFORMATION .......................................................................... 154 22. REVISION HISTORY ..................................................................................... 155 23. PACKAGE DIMENSIONS .............................................................................. 156 HOLT INTEGRATED CIRCUITS 6 HI-6120, HI-6121 List of Figures Figure 1. HI-6120 / HI-6121 Block Diagram................................................................................. 10 Figure 2. Address Mapping for Registers and RAM .................................................................... 19 Figure 3. MIL-STD-1553 Command Word Structure ................................................................... 46 Figure 4. Deriving the Illegalization Table Address From the Received Command Word ........... 49 Figure 5. Fixed Address Mapping for Illegalization Table ........................................................... 50 Figure 6. Summary of Illegalization Table Addresses for Mode Code Commands ...................... 51 Figure 7. Fixed Address Mapping for Interrupt Log Buffer .......................................................... 54 Figure 8. Address Mapping for Descriptor Table ......................................................................... 56 Figure 9. Deriving a Descriptor Table Control Word Address From Command Word ................. 57 Figure 10. Illustration of Ping-Pong Buffer Mode ........................................................................ 79 Figure 11. Ping-Pong Buffer Mode Example for a Receive Subaddress .................................... 81 Figure 12. Illustration of Indexed Buffer Mode ............................................................................ 84 Figure 13. Indexed Buffer Mode Example for a Receive Subaddress (broadcast not enabled) . 85 Figure 14. Illustration of Circular Buffer Mode 1 .......................................................................... 88 Figure 15. Circular Buffer Mode 1 Example for a Receive Subaddress ..................................... 89 Figure 16. Illustration of Circular Buffer Mode 2 .......................................................................... 93 Figure 17. Circular Buffer Mode 2 Example for a Receive Subaddress ..................................... 94 Figure 18. Generalized Single-Byte Transfer Using SPI Protocol. SCK is Shown for SPI Modes 0 and 3 ........................................................................................................................... 108 Figure 19. Single-Word (2-Byte) Read From RAM or a Register ...............................................110 Figure 20. Single-Word (2-Byte) Write To RAM or a Register ....................................................110 Figure 21. HI-6121 Host Bus Interface Timing Diagram ............................................................ 146 Figure 22. Register and RAM Write Operations for BTYPE = 1 ................................................ 147 Figure 23. Register and RAM Write Operations for BTYPE = 0 ................................................ 148 Figure 24. Register and RAM Read Operations for BTYPE = 1 ................................................ 149 Figure 25. Register and RAM Read Operations for BTYPE = 0 ................................................ 150 HOLT INTEGRATED CIRCUITS 7 HI-6120, HI-6121 Figure 26. MIL-STD-1553 Direct Coupled Test Circuits............................................................. 151 Figure 27. MIL-STD-1553 Transformer Coupled Test Circuits................................................... 151 HOLT INTEGRATED CIRCUITS 8 HI-6120, HI-6121 List of Tables Table 1. Pin Descriptions (Both HI-6120 and HI-6121) .................................................................11 Table 2. Pin Descriptions (HI-6120 only) ..................................................................................... 14 Table 3. Pin Descriptions (HI-6121 only) ..................................................................................... 15 Table 4. Register Summary ......................................................................................................... 20 Table 5. Settings and Responses to Interrupt-Causing Messages .............................................. 38 Table 6. Interrupt Information Word Bits Summary ...................................................................... 52 Table 7. Summary of Data Buffer Modes. ................................................................................... 70 Table 8. Circular Buffer Mode 2 (Initialization factors based on message block size) ................. 91 Table 9. Mode Code Command Summary................................................................................... 96 Table 10. Summary of Interrupt Outputs. .................................................................................... 99 Table 11. Interrupt Identification Word ....................................................................................... 100 Table 12. Summary of Changes Due to MR Master Reset or SRST Software Reset ............... 103 Table 13. Fast-Access SPI Commands for Registers 0-15 ........................................................115 Table 14. SPI Commands using Address Pointer Register.........................................................116 HOLT INTEGRATED CIRCUITS 9 HI-6120, HI-6121 1. BLOCK DIAGRAM LOCK EE1K AUTOEN EECOPY MTSTOFF RTA4 - 0 RTAP BENDI BWID BTYPE WPOL CONFIG. OPTION LOGIC SHARED STATIC RAM AND REGISTERS 32K X 16 ADDRESS SPACE LOGIC POWER VCC GND TRANSCEIVER POWER VCCP CONTROL ADDRESS DATA HI-6120 ONLY INTERNAL CLOCKS MCLK TTCLK (OPT) R / W or WE STR or OE WAIT or WAIT A15:1 A0 / LB D15:0 CE SCK SI SO HOST SPI INTERFACE HI-6121 ONLY HOST BUS INTERFACE HI-6120 ONLY CONTROL ADDRESS DATA MEMORY ACCESS MANAGER TEST LOGIC TEST7:0 TEST MODE COMP CONTROL ADDRESS DATA TXINHA BUSA ACKHW ACKMES } * REMOTE TERMINAL STATE MACHINE MESSAGE SEQUENCER AND DUAL ENCODERDECODERS BUSA BUS SSYSF MR INTHW INTMES READY ACTIVE DISCRETE SIGNAL INTERFACE TO HOST TXINHB BUSB BUS BUSB BUS TRANSCEIVERS * Combined into ACKINT pin on HI-6121PQx variant ESCK SPI MASTER MODE INTERFACE TO OPTIONAL SERIAL EEPROM (AUTO-CONFIG) Figure 1. HI-6120 / HI-6121 Block Diagram HOLT INTEGRATED CIRCUITS 10 MISO MOSI ECS HI-6120, HI-6121 2. PIN DESCRIPTIONS Table 1. Pin Descriptions (Both HI-6120 and HI-6121) Pin INTHW Function OUTPUT Description Hardware Interrupt output, active low.This signal is programmed as a brief lowgoing pulse output, or as a level output by the INTSEL bit in Configuration Register 1. Message Interrupt output, active low. This signal is programmed as a brief low-going pulse output, or as a level output by the INTSEL bit in Configuration Register 1. Master Reset, active low. Internal 50KΩ pull-up resistor. The host can also assert software reset by setting the SRST bit in Configuration Register 1. Memory test disable, active high. Internal 50KΩ pull-down resistor. When this pin is low, the device performs a memory test on the entire RAM after rising edge on the MR reset pin. When this pin is high, the RAM test is skipped, resulting in a faster reset process. For further information, refer to Section 14 on page 101. EEPROM Copy, active high. Internal 50KΩ pull-down resistor. This input is used to start the process that copies registers and configuration tables to serial EEPROM. Refer to Section 14 on page 101. Auto-Initialize Enable, active high. Internal 50KΩ pull-down resistor. If this pin is high at rising edge on MR reset input, automatic initialization proceeds, copying configuration data to registers and RAM from an external serial EEPROM via the dedicated auto-initialization SPl port. Refer to Section 14 on page 101. When the AUTOEN pin is high, the EE1K input sets the range of the auto-initialization process. When EE1K is low, registers and RAM occupying the 32K address range from 0x0 to 0x7FFF are initialized. For applications needing faster initialization, when EE1K is high, only registers and RAM occupying the 1K address range from 0x0 to 0x03FF are initialized. This pin has an internal 50KΩ pull-down resistor. If the AUTOEN pin is low, this pin is not used. Refer to Section 14 on page 101. Remote terminal address bits 4 - 0, and parity bit. Internal 50KΩ pull-up resistors. The RTAP pin should provide odd parity for the address present on pins RTA4:0. Terminal address and parity pin levels are latched into the Operational Status register when rising edge occurs on the MR pin. The Operational Status Register value (not these pins) reflects the active terminal address. The register value can be overwritten by the host under some circumstances. See section 5.3 on page 28. Internal 50KΩ pull-down resistor. Pin state is latched into the Operational Status register LOCK bit when rising edge occurs on the MR pin. If Operational Status register LOCK bit is high, terminal address in the register cannot be overwritten by a host register write. If Operational Status register LOCK bit is low, the host can overwrite the five terminal address bits and address parity bit in the Operational Status register. Transmit Inhibits for Bus A and Bus B, active high. Internal 50KΩ pull-down resistors. These inputs are logically ORed with the corresponding TXINHA and TXINHB bits in Configuration Register 1. If the input pin or register bit is high, bus transmit is disabled. INTMES MR OUTPUT INPUT MTSTOFF INPUT EECOPY INPUT AUTOEN INPUT EE1K INPUT RTA4:0 RTAP INPUTS LOCK INPUT TXINHA TXINHB INPUTS HOLT INTEGRATED CIRCUITS 11 HI-6120, HI-6121 Pin Function Description Pin is low when auto-initialization or built-in test is in-process. The host must not access shared RAM or device registers when pin state is low. When output is high, the shared RAM and registers may be configured, and device will begin terminal execution when the STEX (start execution) bit in Configuration Register 1 is set. Pin is high when the HI-6120 / HI-6121 is actively processing a valid MILSTD-1553 command, otherwise low. The falling edge signifies message completion. Master clock input, 50.0 MHz ±0.01% (100ppm). Internal 50KΩ pull-down resistor. Time-Tag Clock input. Internal 50KΩ pull-down resistor. When Configuration Register 1 bits TTCK2:0 = 001, this pin is the clock input for the Time Tag counter. For other values of TTCK2:0, the Time-Tag counter is internally clocked so the TTCLK pin is not used. Subsystem fail input, active high. Internal 50KΩ pull-down resistor. When this input is high, the HI-6120 / HI-6121 terminal sets the SUBSYS flag in its status word. Chip select output for the dedicated Serial Peripheral Interface (SPI) that connects to the optional external serial EEPROM used for automatic self-initialization. For this auto-initialization SPI, the device operates in SPI master mode while the external memory operates in slave mode. This SPI is separate from the host SPI found in the HI-6121. Serial Clock output signal for the dedicated auto-initialization SPI connected to external auto-initialization EEPROM. Serial Input signal (Master-In Slave-Out) for the dedicated auto-initialization SPI connected to external auto-initialization EEPROM. Internal 50KΩ pull-down resistor. Serial Output signal (Master-Out Slave-In) for the dedicated auto-initialization SPI connected to external auto-initialization EEPROM. Bi-directional analog interface to MIL-STD-1553 bus A isolation transformer, positive and negative signals respectively. Bi-directional analog interface to MIL-STD-1553 bus B isolation transformer, positive and negative signals respectively. 3.3V supply voltage inputs for logic and transceiver circuits. Ground pin for logic and transceiver circuits. Test enable. Internal 50KΩ pull-down resistor. The host asserts this pin to perform RAM self-test or loopback tests. Test pins used for factory testing. Internal 50KΩ pull-down resistor. Do not connect these pins. Test pin used for factory testing. Internal 50KΩ pull-up resistor. Do not connect this pin. Test pin used for factory testing. Internal 50KΩ pull-down resistor. Do not connect this pin. HOLT INTEGRATED CIRCUITS 12 READY OUTPUT ACTIVE MCLK TTCLK OUTPUT INPUT INPUT SSYSF INPUT ECS OUTPUT ESCK MISO MOSI BUSA, BUSA BUSB, BUSB VCC, VCCP GND TEST TEST7:0 MODE COMP OUTPUT INPUT OUTPUT ANALOG ANALOG POWER POWER INPUT BI-DIR INPUT INPUT HI-6120, HI-6121 Pin CE Function INPUT Description Chip Enable, active low. Internal 50KΩ pull-up resistor. When asserted, this pin enables host read or write accesses to device RAM or registers. On HI-6121, it is normally connected to a host SPI slave select output signal. Configuration pin for selecting “endianness” of the host interface when byte transfers are used. Internal 50KΩ pull-up resistor. Endianness is the system attribute that indicates whether integers are represented with the most significant byte stored at the lowest address (big endian) or at the highest address (little endian). Internal storage is “big endian.” When using the HI-6120, this pin only applies when the host bus is configured for 8-bit width, that is, when BWID equals 0. When the HI-6120 is configured for 16-bit bus width, the BENDI input pin is “don’t care.” When using the HI-6121, this pin controls the byte order of the 16-bit data following the SPI command. When BENDI is low, “little endian” is chosen; the low order byte (bits 7:0) is transacted before the high order byte (bits 15:8). When BENDI is high, “big endian” is chosen and the high order byte is transacted on the host bus before the low order byte. Hardware Interrupt Acknowledge, active high. Internal 50KW pull-down resistor. This input is only used when the INTSEL bit in Configuration Register 1 is asserted to enable level interrupts. After interrupt assertion causes the INTHW output to go low, a high state (60ns minimum duration) on ACKHW will clear the INTHW output to logic 1. The interrupt is also cleared automatically by reading the Pending Interrupt Register. Message Interrupt Acknowledge, active high. Internal 50KW pull-down resistor. This input is only used when the INTSEL bit in Configuration Register 1 is asserted to enable level interrupts. After interrupt assertion causes the INTMES output to go low, a high state (60ns minimum duration) on ACKMES will clear the INTMES output to logic 1. The interrupt is also cleared automatically by reading the Pending Interrupt Register. BENDI INPUT ACKHW* INPUT ACKMES* INPUT * Note: These pins are combined into the ACKINT pin on HI-6121PQx variant. HOLT INTEGRATED CIRCUITS 13 HI-6120, HI-6121 Table 2. Pin Descriptions (HI-6120 only) Pin Function Description Tri-state data bus for host read/write operations upon registers and shared RAM. Internal 50KΩ pull-down resistors. All read/write operations transact 16 bit words, but bus width can be configured for 8 or 16 bits. For 8 bit bus width, pins D15:8 are not connected; each 16-bit word is transacted as a pair of upper and lower byte operations, with data presented sequentially on pins D7:0. For compatibility with different host processors, when byte transfers are enabled the BENDI input pin sets whether the low order byte is transferred before the high order byte, or vice versa. Address bus for host read/write operations upon registers and shared RAM. For 16-bit bus width, address bit A0 (LB) from the host is not used. For 8-bit bus width, bit A0 equals 0 during the first byte read/write access; while A0 equals 1 during the second byte access. Configuration pin for host bus width. Internal 50KΩ pull-up resistor. High selects 16-bit bus width, low selects 8-bit bus width. Configuration pin for host bus read/write control signal style. Internal 50KΩ pull-up resistor. High selects “Intel style” using separate read strobe OE (output enable) and write strobe WE. Low selects “Motorola style” using combined read/write strobe STR and read/write select signal, R/W. R/W (read/write) signal when BTYPE pin is low, or WE (write enable) when BTYPE pin is high. Internal 50KΩ pull-up resistor. Used for host read or write accesses to device RAM or registers. Important: This pin or the CE pin should be high during all address transitions. When BTYPE pin is low, common STR (read/write strobe). When BTYPE pin is high, OE (output enable). Internal 50KΩ pull-up resistor. Used for host read or write accesses to device RAM or registers. Host bus read cycle “wait” output. For compatibility with different host processors, this output can be made active high or active low, set by the state of the WPOL input pin. The WAIT output may be ignored when the host processor’s read cycle time is sufficiently slow to meet worst case (slowest) read cycle timing for this device, or when wait cycles have been enabled from the processor. The WAIT output is useful when the host processor runs at high clock rates and/or when processor read wait states do not provide adequate timing margin for worst case (slowest) read cycle timing for this device. See Section 15.1 on page 107 for further information. Configuration pin for WAIT output polarity. Internal 50KΩ pull-up resistor. When WPOL is low, the “wait” output is active low (WAIT). When WPOL is high, the “wait” output is active high (WAIT). The HI-6120 uses pre-fetching to speed up any series of reads from successive addresses. As long as successive reads are sequential, only the first word’s read cycle generates a WAIT (WAIT) output. No WAIT is generated for following words read. D15:0 I/O A15:1 and A0 (LB) BWID INPUTS INPUT BTYPE INPUT R/W or WE INPUT STR or OE INPUT WAIT or WAIT OUTPUT WPOL INPUT HOLT INTEGRATED CIRCUITS 14 HI-6120, HI-6121 Table 3. Pin Descriptions (HI-6121 only) Pin SO SI SCK Function OUTPUT INPUT INPUT Description Serial Peripheral Interface (SPI) Serial Output pin. SO is normally connected to MISO (Master In - Slave Out) pin on host SPI port. The SO pin is tri-stated when not transmitting serial data to host. Serial Peripheral Interface (SPI) Serial Input pin. Internal 50KΩ pull-down resistor. SI is normally connected to MOSI (Master Out - Slave In) pin on host SPI port. Serial Peripheral Interface (SPI) Serial Clock pin. Internal 50KΩ pull-down resistor. SCK is normally connected to SCK output pin on host SPI port. Interrupt Acknowledge, active high. Internal 50KΩ pull-down resistor. This input is only used when the INTSEL bit in Configuration Register 1 is asserted to enable level interrupts. After interrupt assertion causes the INTHW or INTMES output to go low, a high state (60ns minimum duration) on ACKINT will clear the INTHW or INTMES output to logic 1. Interrupt outputs on INTHW and INTMES are also cleared by reading the Pending Interrupt Register. ACKINT (HI-6121PQX variant only) INPUT HOLT INTEGRATED CIRCUITS 15 HI-6120, HI-6121 3. FUNCTIONAL OVERVIEW The Holt HI-6120 or HI-6121 provides a complete Remote Terminal (RT) interface between a host and a MIL-STD-1553B dual redundant data bus. It automatically handles all aspects of the MIL-STD-1553 protocol, namely, encoding/decoding, message formatting, error checking, message data buffering, protocol checking, illegalization and default terminal responses. Internal static RAM is shared by the host and device logic, providing efficient storage for message data and information about messages, updated after each message transaction. The shared RAM also contains host-initialized tables that define terminal operation. Two options are offered for host interface. The HI-6120 uses a 16-bit tri-state data bus, ideally suited for memory-mapped host processor operation. The HI-6121 uses a 3-wire Serial Peripheral Interface (SPI) with powerful SPI command set. Figure 2 shows address mapping for registers and RAM. Registers occupy the lowest 32 addresses of the 32K memory address space. Internal registers (or contained bit fields) are partitioned as read-only or read-write so the host can exercise configuration control without risk of misconfiguration caused by accidental writes to device-maintained registers or bit fields. Dedicated output pins convey status to the host, and generate host interrupts for preselected events. Before processing messages, internal registers and transmit data buffers in shared RAM must be initialized by the host to define the desired message responses. Host initialization can be replaced by optional auto-initialization using parameters in external EEPROM. codes may be illegalized (see below). The Descriptor Table Base Address Register is initialized with the starting address of the Descriptor Table. Multiple Descriptor Tables can be used for fast context switching, with the active table designated by the base address register. 3.1.2. Illegalization Table Optional illegal command detection utilizes an Illegalization Table in the shared RAM. The table can illegalize any logical combination of 11 command word bits for subaddress, T/R bit and word count (or mode code), plus broadcast vs non-broadcast status, resulting in a total of 4,096 possible combinations. The Illegalization Table Base Address Register is initialized with the table’s start address. Terminal response to an illegal command sets “message error” status and transmits Status Word only. If illegal command detection is not used (that is, no “illegal” entries in Illegalization Table), the terminal responds “in form” to all valid commands. 3.1.3. Message Data Buffers 3.1. 3.1.1. Shared RAM Utilization Descriptor Table The host-initialized Descriptor Table, residing in shared RAM, defines terminal response to valid commands. The table is comprised of 4-word Descriptor Blocks. Each of 32 subaddresses and 32 mode code values has two descriptor blocks, one for transmit and one for receive, for a total of 128 descriptor blocks. The first word in each descriptor block defines message options (interrupt selections, data buffer mode, etc.). Except for Indexed buffer mode (where one word counts messages) the remaining three words point to allocated data storage in shared RAM. After Master Reset is negated and before message processing, the host must initialize descriptor blocks for each utilized subaddress and mode code. Unused subaddresses and unimplemented mode After master reset, all locations in shared memory are reset to 0000 hex. Ordinary transmit or receive commands transfer 1 to 32 data words. These are called “subaddress commands,” distinguishing them from “mode code commands,” described in the next paragraph. By initializing the Descriptor Table, the host allocates space in shared RAM for storing message data words and message information words. Data pointers in the table assign separate data buffer addresses in memory for each command. Data storage arrangement differs by choice of data buffer method. Two examples are shown for each of the four buffer modes in Figures 11-18. After successfully transacting a message with one or more received data words, the RT writes into the assigned data buffer. While transacting a message with one or more transmitted data words, the RT reads data for transmission from the assigned data buffer. Before transmit commands occur, the host should write desired data into assigned transmit data buffers in shared RAM. Transmit subaddress data buffers can be optionally loaded by auto-initialization. 3.1.4. Storage for Mode Code Commands MIL-STD-1553 defines “mode code commands” that are used for command and control, instead of data transfer. The various “mode commands” transfer a single data word, or no data word at all. The user has two choices for storing mode command data: (1) similar to subaddress command data, mode command data can be stored in RAM data buffers assigned by the host-initialized Descriptor Table, or (2) When “simplified mode command processing” is chosen, mode command data is stored HOLT INTEGRATED CIRCUITS 16 HI-6120, HI-6121 within the Descriptor Table itself. Just six defined mode commands transfer a data word; thus, option 2 is often preferred since initialization is easier. Consistent, predictable terminal responses can be set up for all mode commands, including the reserved and undefined mode codes. An option bit in Configuration Register 1 globally sets whether the 22 undefined mode commands are treated as illegal (RT response dependent on command’s Illegalization Table setting) or invalid (no RT response whatsoever, and no RT status change). nally generated frequencies, or from an external source. The user can enable automatic counter synchronization in response to “synchronize” mode commands, and optional host interrupts are provided for time-tag counter roll-over, and counter match to a stored value in the Time-Tag Utility register. 3.2.4. Dual Bus Transceivers 3.1.5. Interrupt Log The device maintains information from the last 16 interrupts in a 32-word circular buffer in shared RAM known as the Interrupt Log. Two 16-bit words characterize each interrupt; one word identifies the interrupt type (Interrupt Identification Word) and one word identifies the command that generated the interrupt (Interrupt Address Word). After reset, the Interrupt Log Address Register is reset to the fixed starting address of the 32 word Interrupt Log. After each occurring interrupt, the device updates the register to point to the log address used for the next occurring interrupt. Built-in bus transceivers provide direct interface between the device and MIL-STD-1553 bus isolation transformers. The transceivers convert digital data to and from differential Manchester II encoded bus signals. A pair of “transmit inhibit” input pins exercises direct control over transmission for both buses. 3.2.5. Encoder and Decoders 3.2. 3.2.1. Hardware Feature Summary Clock Interrupts The RT contains separate Manchester II encoders and decoders for each bus. Encoder-decoder logic interfaces directly with the dual-bus MIL-STD-1553 transceivers. The decoder checks for proper sync pulse and Manchester waveform, edge skew, correct number of bits and parity. During transmission, each encoded word is looped back through the decoder to check for errors. Bus sampling is clocked at 25 MHz, providing superior tolerance to zero-crossing distortion. A 50 MHz master clock input is required. The Time-Tag counter clock is selected from six internally generated frequencies, or may use an external clock input signal. 3.2.6. Auto-Initialization Serial EEPROM Interface 3.2.2. Remote Terminal Address Inputs The 5-bit Remote Terminal address is set using pins RTA0 to RTA4. The RTAP input pin should be set or reset to present matching odd parity. The state of the RT address and parity pins is latched into the Operational Status register upon rising edge on the MR master reset input. The state of the LOCK input is latched into the Operational Status register at the same time, and controls whether or not the active terminal address and parity in the Operational Status register can be overwritten by host writes into the register. Between Master Reset assertions, the state of the RTA and RTAP inputs is “don’t care”. If the value of RT address and parity in the Operational Status register has parity error, terminal operation is disallowed. The device has an automatic self-initialization feature. If self-initialization is enabled after MR master reset, the device reads configuration settings from external serial EEPROM to load the Descriptor Table, Illegalization Table, transmit mode command data and registers for terminal operation. Self-initialization can optionally initialize transmit data buffers with fixed data from EEPROM. A mechanism is provided to initially program or later modify the external serial EEPROM memory, by copying host-loaded tables and register values to the serial EEPROM. 3.2.3. Integral Time-Tag Counter A free-running 16-bit counter provides time-tag values that are recorded for each message transacted. The time-tag counter can be clocked from one of six interHOLT INTEGRATED CIRCUITS 17 HI-6120, HI-6121 4. MEMORY AND REGISTER ADDRESSING The HI-6120 and HI-6121 have an internal address space of 32K 16-bit words. All memory addresses in this data sheet are expressed as hexadecimal numbers, using the C programming convention where the prefix “0x” denotes a hexadecimal value; e.g., 0x00FF represents 00FF hex. All device RAM and register address mapping is word oriented, rather than byte oriented. Register and memory addresses throughout this document reflect word addressing. For all HI-6121 and most HI-6120 applications, word oriented addressing applies. Word oriented addressing with the HI-6120 uses address inputs A15 to A1; address input A0 is not used as fifteen bits are sufficient for a 32K address range. HI-6120 ONLY: When required by the application, the host bus interface HI-6120 is able to use byte transfers. All 8-bit microprocessors (and some 16-bit and 32-bit microprocessors) use (or can use) byte-oriented memory accesses. To provide byte capability, the HI-6120 has a sixteenth bus address input, A0. Byte oriented addressing with the HI-6120 uses all 16 address pins, A15:A0 to address 64K bytes. The A0 input denotes whether the first or second byte in the word is being addressed, while A15:A1 indicate the word address. This difference must be considered when assigning HI-6120 pointer values or accessing RAM or registers. From the microprocessor’s standpoint, any host-assigned RAM buffer address will be double the value of the buffer’s pointer stored in RAM. This paragraph only applies to HI-6120 using 8-bit bus width. From this point on, all register and memory addresses presented in this data sheet are 15bit word addresses. From the host standpoint, register operations and RAM operations are performed identically. Registers occupy the lowest 32 addresses, 0x0 to 0x001F. Depending on function, individual registers may be read-only, readwrite, or a combination of read-only and read-write bit fields. Read-only registers, and read-only bit fields contained in registers, are protected against accidental host overwrite by device logic. Addresses in the range 0x0020 to 0x7FFF apply to static RAM memory. All RAM is read-write and can be written or read by either the host or the internal device logic. Some memory locations (specifically Descriptor Table Control Words) contain bits updated by both host and device. These locations are protected against accidental data collision by device arbitration logic which acts when concurrent writes by both host and device occur. HOLT INTEGRATED CIRCUITS 18 HI-6120, HI-6121 0x7FFF Host-Allocated Subaddress Data Buffers. Comprising 97% of the memory address space, this RAM is allocated into subaddress data buffers by the Descriptor Table. 0x0400 0x03FF Descriptor Table. Defines terminal behavior for valid commands: how data is stored, host interrupts, etc. 512 Words Multiple Descriptor Tables can be used for fast context switching. The active Descriptor Table is defined by the Descriptor Table Base Address Register. Illegalization Table. Initialized by the host, this table identifies illegal commands. 256 Words 0x00FF 0x0200 0x01FF Unallocated Memory. This space in shared RAM can be assigned by the host. 160 Words 0x0100 0x00FF 0x0060 0x005F 0x0040 0x003F 0x0020 0x001F 0x0000 Interrupt Log Data Buffer. 32 Words Expanded at right 0x0000 Temporary Receive Data Buffer. 32 Words Registers (listed on next page) 32 Locations Figure 2. Address Mapping for Registers and RAM HOLT INTEGRATED CIRCUITS 19 HI-6120, HI-6121 5. REGISTERS Residing at the start of the memory address space, 32 addresses are reserved for HI-6120 and HI-6121 registers. Register addresses overlay the shared RAM address space, but are separate from the shared dual-port RAM. All register bits are active high. Unless otherwise indicated, all registers are reset in software to the logic zero condition after Master Reset (except any bits reflecting the state of input pins). For all registers, bit 15 is the most significant. Table 4. Register Summary Register Number 0 1 2 3 4 5 6 7 8 9 10 11-14 15 16 17 18 19 20 21 22 23 24 25 26-31 Hex Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B-0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A-0x001F Register Name Configuration Register 1 Configuration Register 2 Operational Status Register Current Command Register Current Control Word Address Register Descriptor Table Base Address Register Pending Interrupt Register 1553 Status Word Bits Register Time-Tag Register Interrupt Log Address Register Current Message Information Word Address Register Reserved Memory Address Pointer (HI-6121 Only) Interrupt Enable Register Time-Tag Utility Register Bus A Select Register Bus B Select Register Built-In Test (BIT) Word Register Alternate Built-In Test (BIT) Word Register Reserved Test Control Register Loopback Test Transmit Data Register Loopback Test Receive Data Register Reserved HOLT INTEGRATED CIRCUITS 20 HI-6120, HI-6121 5.1. Configuration Register 1 (0x0000) This 16-bit register is Read-Write and is fully maintained by the host. All bits are active high. H B IN US HA B IN US TS B S D EL S TT EL C TT K2 C TT K1 C ST K0 E SR X ST X MSB 15 14 13 12 11 10 9 8 7 6 X 5 4 3 2 1 0 LSB NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is unchanged unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset Function Bus A Inhibit. 15 INHBUSA R/W 0 When set, this bit disables transmit and receive for Bus A. This bit is logically ORed with the TXINHA input signal to control Bus A transmitter enablement. Bus A transmission is disabled if the INHBUSA register bit or TXINHA input pin is asserted. The TXINHA pin does not affect the Bus A receiver. Bus B Inhibit. 14 INHBUSB R/W 0 When set, this bit disables transmit and receive for Bus B. This bit is logically ORed with the TXINHB input signal to control Bus B transmitter enablement. Bus B transmission is disabled if the INHBUSB register bit or TXINHB input pin is asserted. The TXINHB pin does not affect the Bus B receiver. Interrupt Mode Select. 13 INTSEL R/W 0 When this bit is low, pulse interrupt outputs are selected for INTMES and INTHW output pins. When this bit is high, level interrupts are enabled which require host acknowledgment for interrupt pin reset. HOLT INTEGRATED CIRCUITS 21 S U TIN MV C N IN OV TI SM C E C2 SS P R D 8 IN BC HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Shutdown Select. This bit affects terminal response to “transmitter shutdown” mode code commands and only applies when the MCOPT4 bit in Configuration Register 2 equals logic 0 for automatic shutdown after “transmitter shutdown” and “selected transmitter shutdown” mode code commands. When MCOPT4 and SDSEL are both logic 0, a valid “transmitter shutdown” mode command automatically disables the inactive bus transmitter and receiver (complete ”bus shutdown”). This is the recommended mode of operation and is the default state of these two bits after MR reset. 12 SDSEL R/W 0 When MCOPT4 is logic 0 and SDSEL is logic 1, “transmitter shutdown” or “selected transmitter shutdown” mode commands automatically disable just the inactive bus transmitter, but the bus receiver remains enabled. The terminal fully complies with valid commands received on the inactive bus (storing received data, etc.), except it does not transmit status or data onto that bus (”mute terminal”). This mode of operation is not recommended but may be required in some applications. See MCOPT4 bit in Configuration Register 2 for further information concerning “transmitter shutdown” and “selected transmitter shutdown” mode commands. The Built-In Test (BIT) Word Register contains status flags that reflect automatic shutdown status when the MCOPT4 bit in Configuration Register 2 is logic 0. See page xx. Time-Tag Counter Clock Select. These three bits select the time-tag counter clock source from the following options: TTCK2 11, 10, 9 TTCK2:0 R/W 0 0 0 0 0 1 1 1 1 TTCK1 0 0 1 1 0 0 1 1 TTCK0 0 1 0 1 0 1 0 1 Clock Source Time-Tag counter disabled External clock provided at TTCK input pin Internally generated 2μs clock Internally generated 4μs clock Internally generated 8μs clock Internally generated 16μs clock Internally generated 32μs clock Internally generated 64μs clock Start Execution. Assertion of this bit initiates RT operation; negation of this bit inhibits or stops RT operation. Upon STEX assertion, RT parity-address error prevents terminal operation, regardless of the logical state of the STEX bit. If RT address parity error occurs, the Status Register and Pending Interrupt Register RTAPF bits will be asserted. This bit is cleared after MR pin master reset. Software Reset. 7 SRST R/W (SR = 0) 8 STEX R/W 0 0 Assertion of this bit immediately initiates the software reset process. This bit should not be set to logic 1 during auto-initialization. This bit is cleared after MR master reset and automatically self-resets after being set by the host. Not used. 6,5 ----- R/W (SR = 0) 0 HOLT INTEGRATED CIRCUITS 22 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Broadcast Commands Invalid. If this bit is high, commands addressed to RT address 31 are treated as invalid: There is no terminal recognition of commands to RT address 31; there is no RT command response, and no status updating for the benefit of following “transmit status” or “transmit last command” mode commands. If this bit is low, commands addressed to RT address 31 are treated as valid broadcast commands. Undefined Mode Codes Invalid. This bit globally defines whether undefined mode code commands are treated as valid (default) or invalid commands. This bit applies only to the following undefined mode code commands: Mode Codes 0 through 15 with T/R bit = 0 Mode Codes16, 18 and19 withT/R bit = 0 Mode Codes 17, 20 and 21 with T/R bit = 1 If this bit is low (default state after MR pin reset) undefined mode code commands are considered valid, and RT response is based on individual mode command settings in the Illegalization Table: If a mode command is legal, the RT “responds in form” and updates status. If a mode command is illegal, the RT asserts Message Error status and (if non-broadcast) transmits only its Status Word without associated data word. Later in this data sheet, the section “RT Message Responses, Options & Exceptions” fully describes terminal response for each mode code value, command word T/R bit state, and option settings. If this bit is high, undefined mode code commands are treated as invalid: There is no RT recognition of an invalid command, no RT command response, and no status updating for the benefit of following “transmit status” or “transmit last command” mode commands. If this bit is high, the terminal stores data associated with broadcast commands separately from data associated with non-broadcast commands to meet the requirements of MIL-STD-1553B Notice 2. If this bit is low, broadcast command data is stored in the same buffer as non-broadcast command data. Simplified Mode Command Processing. 1 SMCP R/W 0 When asserted, the device applies simplified processing for all valid mode code commands. The later section entitled “Mode Command Processing” describes this option. Single-Strobe Read for 8-Bit Parallel Bus Mode. This bit only applies to HI-6120 (not HI-6121) and only applies when the parallel host bus is configured for 8-bit bus width. When performing 2-byte read accesses of external memory, some microprocessors with 8-bit bus assert individual Read Enable (or STROBE) pulses for high and low bytes. Other microprocessors assert a single, wider Read Enable (or STROBE) pulse, while simply changing the low address bit (A0 / LB) to access the two bytes. For this last case, the SSRD8 bit should be set when writing device configuration, before register or RAM readback is performed. 4 BCSTINV R/W 0 3 UMCINV R/W 0 2 NOTICE2 R/W 0 0 SSRD8 R/W 0 HOLT INTEGRATED CIRCUITS 23 HI-6120, HI-6121 5.2. Configuration Register 2 (0x0001) This 16-bit register is Read-Write and is fully maintained by the host. All bits are active high. TO S TO EL S1 TR EL X0 TT DB LO RT AD T AL AG TB M IT CW O M PT C4 O M PT C O3 M PT C2 O MP C T1 O PT 0 X MSB 15 14 13 12 11 10 9 8 7 6 5 4 X 3 X 2 X 1 X 0 LSB NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset. Bit No. Mnemonic R/W Reset Function Time-Out Select for RT-RT Receive Commands. These bits select the “no response” time-out for RT-RT receive commands. Message error occurs when the transmitting Remote Terminal fails to begin transmission before time-out occurs. Time interval boundaries are defined in RT validation test plan Figure 8 “RT-RT Timeout Measurement.” MIL-STD1553B stipulates that 54 to 60μs is the acceptable range for time-out. However, longer time-out options are provided for systems using long buses and/ or utilizing bus repeaters that add delay to bus traffic. RT-RT time-out can be selected from the following options: TOSEL1 1 1 0 0 TOSEL0 1 0 1 0 RT-RT Time-Out 150μs 125μs 100μs 57μs reset) 15,14 TOSEL1:0 R/W 0 (default after MR pin master Temporary Receive Data Buffer. Setting this bit enables a temporary data buffer for all receive commands. When enabled, the RT stores received data words in a 32-word data buffer during message processing. Upon error-free message completion, all saved words are written to data buffer memory in a burst. When the temporary receive data buffer is disabled, the RT writes each received data word to the subaddress data buffer memory as it is received. Should message error occur during data word reception, this mode results in loss of data integrity, as vaild data from the prior command is partially overwritten by data from a message with error. MIL-STD-1553 states that data should be disregarded for messages ending in error. This bit should only be modified while Configuration Register 1 STEX bit is low. Changes occurring while STEX = 1 cause unpredictable results. In a typical application, the buffer is not directly accessed by the host, although there is no restriction preventing host data access. Load Time-Tag Counter. 12 TTLOAD R/W 0 When this bit is written from logic 0 to logic 1, data contained in the TimeTag Utility register is written to the Time-Tag counter. The TTLOAD register bit self-resets after use. See MCOPT3 bit which affects automatic Time-Tag counter loading upon “synchronize” mode command with data word. 13 TRXDB R/W 0 HOLT INTEGRATED CIRCUITS 24 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Reset Time-Tag Counter. 11 RTTAG R/W 0 Assertion of this bit clears the Time-Tag counter and counting is disabled until the bit is negated. Also the “synchronize” mode command (MC1) causes automatic Time-Tag counter reset. Alternate BIT Word Enable. If this bit is logic 0, the device responds to a “transmit BIT word” mode command (MC19) by sending the word stored in the Built-In Test Word register, at address 0x0014. If this bit is logic 1, the terminal transmits the word stored in the Alternate Built-In Test Word register, at address 0x0015. The alternate register allows the user to fully define the BIT word, while the default register location contains several predefined, device-controlled status bits. Mode Code Option 4. Note: Mode commands MC4 and MC5 are not affected by the MCOPT4 bit, but are included in this description to present a complete picture of device response to bus shutdown mode commands. The Bus Controller exercises “shutdown“ control over the terminal’s connection to the inactive MIL-STD-1553 bus using the “transmitter shutdown” (MC4) or “selected transmitter shutdown” (MC20 decimal) mode code commands. When the inactive transmitter is shutdown, the HI-612x device inhibits further transmission on that bus. Once shutdown, the transmitter can be reactivated by (a) an “override transmitter shutdown” (MC5) mode command, (b) an “override selected transmitter shutdown” (MC21 decimal) mode command, (c) a “reset remote terminal” (MC8) mode command, (d) hardware MR master reset or (e) software reset by setting the SRST bit in Configuration Register 1. When the MCOPT4 bit is reset, the device automatically performs bus shutdown and shutdown override in response to mode commands. When the MCOPT4 bit is set, the device only transmits status; the host must perform bus shutdown and override duties by asserting control of the TXINHA and TXINHB bits in Configuration Register 1, or by controlling the input pins with the same function. Mode commands MC4 (”transmitter shutdown”) and MC5 (”override transmitter shutdown”) have unconditional shutdown or override response. When MC4 is received, the terminal fulfills shutdown for the inactive bus, disabling the transmitter and receiver, or transmitter only, depending on the state of the SDSEL bit in Configuration Register 1. The device affirms shutdown status by updating bits 15-12 in the BIT Word Register. When mode command MC5 is received, inactive bus transmit and receive is automatically reenabled by the device; “shutdown override” status is affirmed by resetting the inactive bus shutdown bit(s) in the BIT Word Register. 10 ALTBITW R/W 0 9 MCOPT4 R/W 0 HOLT INTEGRATED CIRCUITS 25 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function The “selected transmitter shutdown” (MC20 decimal) and “override selected transmitter shutdown” (MC21 decimal) mode commands act similarly to MC4 and MC5 respectively, except bus shutdown (or shutdown override) is conditional, based on the value of a mode data word received with the command. To act on a given bus, the received mode data word must match a predetermined “bus select” value. Bus shutdown (or shutdown override) can only act on the inactive bus, and only when the received mode data word matches the “bus select” value for that bus. When a MC20 mode data word matches the “bus select” value for the inactive bus, the terminal fulfills shutdown for the inactive bus, disabling the transmitter and receiver, or transmitter only, depending on the state of the SDSEL bit in Configuration Register 1. The device affirms shutdown status by updating bits 15-12 in the BIT Word Register. When a MC21 mode data word matches the “bus select” value for the inactive bus, the terminal fulfills shutdown override for the inactive bus, enabling the transmitter (and receiver, if the SDSEL bit in Configuration Register 1 is logic 0). The device affirms override status by resetting bits 15-12 in the BIT Word Register. When the MCOPT4 bit equals zero, unique “bus select” values should be initialized by the host in the “Bus A Select” register (0x0012) and “Bus B Select” register (0x0013) for fulfillment of “selected transmitter” shutdown and override mode commands. When MCOPT4 equals zero, transmitter shutdown (or shutdown override) automatically occurs when the received mode data value matches the inactive bus “Bus Select” register. 9 MCOPT4 (continued) R/W 0 Below shows device response for “transmitter shutdown” and “override transmitter shutdown” mode code commands for different option configurations: The MCOPT4 bit in Configuration Register 2 is logic 0 or 1 Inactive Bus Tx & Rx Disabled (Enabled). (only Tx is disabled, if the SDSEL config. bit = 1) In BIT Word Register, TXSD & Status Word RXSD bits updated. transmitted, (only TXSD bit unless updated, if the broadcast SDSEL config. bit = 1) MC4 (or MC5) unconditional fulfillment The MCOPT4 bit in Configuration Register 2 is logic 0 MC20 (or MC21) if mode data value matches “Bus Select” value MC20 (or MC21) if mode data does NOT match “Bus Select” value Inactive Bus Tx & Rx Disabled (Enabled). (only Tx is disabled, if the SDSEL config. bit = 1) In BIT Word Register, TXSD & Status Word RXSD bits updated. transmitted, (only TXSD bit unless updated, if the broadcast SDSEL config. bit = 1) Status Word transmitted, unless broadcast In BIT Word Register, TXSD & RXSD bits are static Inactive Bus Tx & Rx status not changed HOLT INTEGRATED CIRCUITS 26 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function The MCOPT4 bit in Configuration Register 2 is logic 1 MC20 (or MC21) if mode data value matches “Bus Select” value MC20 (or MC21) if mode data does NOT match “Bus Select” value Inactive Bus Tx & Rx status NOT changed (Host can modify BUSINH bit in Configuration Reg 1) Inactive Bus Tx & Rx status not changed Status Word transmitted, unless broadcast Status Word transmitted, unless broadcast In BIT Word Register, TXSD & RXSD bits are static In BIT Word Register, TXSD & RXSD bits are static 9 MCOPT4 (continued) R/W 0 Mode Code Options 3 and 2. If both of these bits equal one, the data word received with a valid “synchronize” mode command (MC17) is unconditionally loaded into the Time-Tag counter. For non-broadcast MC17 commands, the counter load occurs before status word transmission. If both of these bits equal 0, the external host assumes responsibility for actions needed to perform “synchronize” duties upon reception of the valid MC17 “synchronize”mode code command, but status transmission automatically occurs. The binary 01 and 10 combinations of the MCOPT3 and MCOPT2 bits support certain extended subaddressing schemes. If the MCOPT3-MCOPT2 bits equal 01, the received data word is automatically loaded into the TimeTag counter if bit 0 of the received data word equals 0. If the MCOPT3MCOPT2 bits equal 10, the received data word is automatically loaded into the Time-Tag counter if bit 0 of the received data word equals 1. For non-broadcast MC17 commands, the counter load occurs before status word transmission. Mode Code Option 1. If this bit is logic 0, reception of a “transmit vector word” mode command (MC16) causes automatic reset of the Service Request status bit. The Service Request bit is reset in the Status Word Bits register before status word transmission begins. If the MCOPT1 bit is logic 1, the external host assumes responsibility for resetting the Service Request bit in the Status Word Bits register. Mode Code Option 0. 5 MCOPT0 R/W 0 If this bit is logic 0, reception of a “reset remote terminal” mode command (MC8) causes automatic assertion of SRST software reset. If non-broadcast mode command, reset occurs after status word transmission is complete. If this bit is logic 1, the external host assumes responsibility for actions needed to perform terminal reset. Not Used 8,7 MCOPT3:2 R/W 0 6 MCOPT1 R/W 0 4-0 ----- R/W 0 HOLT INTEGRATED CIRCUITS 27 HI-6120, HI-6121 5.3. Operational Status Register (0x0002) All sixteen register bits are active high. After rising edge on the MR master reset input pin, bits 15 - 8 reflect the state of input pins RTA4 through RTA0, RTAP, LOCK and AUTOEN; register bits 7 - 3 are reset to logic 0 state. Register bits 8 - 0 are always read-only. If the register’s LOCK bit is logic 0, bits 15 - 9 are read-write but cannot be written unless STEX in Configuration Register 1 is low. If the register LOCK bit is logic 1, bits 15 - 9 are is read-only. Once the LOCK bit is set, unlock requires a new MR master reset assertion with the LOCK input pin at logic 0 state. MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The value “PIN” denotes the bit is set to the value of the corresponding pin following Master Reset. This register is unaffected by software reset. Bit No. 15-11 Mnemonic R/W RTA4 - 0 R/W Reset PIN Function Remote Terminal Address bits 4 - 0. Remote Terminal Address Parity. These bits contain the active remote terminal address. After a rising edge on the MR master reset input signal, these bits reflect the state of the RTA4 - 0 and RTAP input pins. When the register LOCK bit is high, these bits are read-only. When the register LOCK bit is low (and STEX in Configuration Register 1 equals 0) auto-initialization (see bit 8) or the host can overwrite these bits to change the terminal address and parity. Terminal Address Lock. 9 LOCK R/W PIN After a rising edge on the MR master reset input signal, this bit reflects the state of the LOCK input pin. When the LOCK bit is high, this bit is read-only. When LOCK is low (and STEX in Configuration Register 1 equals 0) autoinitialization (see bit 8) or the host can write this bit to logic 1 to lock the active terminal address. Auto-Initialize Enable. This read-only bit reflects the state of the AUTOEN input pin that applied at the rising edge on the MR master reset input signal. If the register AUTOEN bit is high, device auto-initialization was performed following MR reset. When auto-initialization is complete, the device waits for the host to assert the STEX bit in Configuration Register 1 to enable terminal operation. Auto-initialization of the Control Register can optionally set STEX to begin terminal operation without host assistance. See section entitled “Reset and Initialization” for details. Ready status. 7 READY R 0 This read-only bit reflects the state of the output pin READY and is cleared on reset. The bit is asserted after post-reset internal terminal initialization is complete, indicating that shared RAM is ready to accept configuration data from the host. 10 8 RT A RT 4 A RT 3 A RT 2 A RT 1 A RT 0 A LO P C AU K T R OE EA N AC DY T M IVE C N MD C R MD C T RT D A EE PF C R KF AM IF 8 7 6 5 4 3 2 1 0 LSB RTAP R/W PIN AUTOEN R PIN HOLT INTEGRATED CIRCUITS 28 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Active status. 6 ACTIVE R 0 When set, this read-only bit indicates the terminal is presently processing a message. This bit reflects the state of output pin ACTIVE and is cleared on reset. Note: Ths bit and the corresponding output pin are asserted upon valid command detection and negated when command processing is completed. Mode Code Command Type Flags (No-Data, Receive-Data and TransmitData). These three bits reflect the state of the command stored in the Current Command Register, 0x0003: Current Command Type MCND 5,4,3 MCRD MCTD R 0 Subaddress (not mode code) Mode code (no data word) Mode code (receive data) Mode code (transmit data) Mode code (undefined, no data) RT Address Parity Fail. 2 RTAPF R 0 This bit is set when Remote Terminal address parity error is present. The bit is low when correct odd parity applies to the terminal address latched in bits 15-10. This bit is high when parity error is present. EEPROM Checksum Fail. 1 EECKF R 0 This bit only applies when auto-initialization is enabled. While performing auto-initialization, this bit is set if the checksum tallied from read EEPROM data doesn’t match the checksum value stored in EEPROM. This failure also sets bit 1 in the Built-In Test Word Register (0x0014). RAM Initialization Fail. 0 RAMIF R 0 This bit only applies when auto-initialization is enabled. While performing initialization, this bit is set if a write-then-read RAM value doesn’t match its counterpart location in the serial EEPROM. This failure also sets bit 1 in the Built-In Test Word Register (0x0014). MCND 0 1 0 0 1 MCRD 0 0 1 0 1 MCTD 0 0 0 1 1 Current Command Word Subaddress, transmit or receive MC0 to MC15, T/R bit equals 1 MC16 to MC31, T/R bit equals 0 MC16 to MC31, T/R bit equals 1 MC0 to MC15, T/R bit equals 0 HOLT INTEGRATED CIRCUITS 29 HI-6120, HI-6121 5.4. Current Command Register (0x0003) This 16-bit register is Read-Only and is fully maintained by the device. CURRENT COMMAND 15:0 C C C C C C C C 8 C 7 CC 6 5 C 4 C 3 C 2 C 1 C 0 LSB MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset. Bit No. Mnemonic R/W Reset Function Current Command Word. 15-0 CC15:0 R 0 This register contains the last valid command received over either MILSTD-1553 bus. This register is updated 5us after the ACTIVE output is asserted. Bit 15 is MSB. 5.5. Current Control Word Address Register (0x0004) This 16-bit register is Read-Only and is fully maintained by the device. CURRENT CONTROL WORD ADDRESS 15:0 A A A A A A A A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 LSB MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset. Bit No. Mnemonic R/W Reset Function Current Control Word Address Register 15-0 CCW15:0 R 0 This register contains the address for the descriptor table Control Word corresponding to the current command stored in the Current Command Register (0x0003). This register is updated 5us after the ACTIVE output is asserted. Bit 15 is MSB. Also see “Current Message Information Word Address” register, 0x000A. 5.6. Descripter Table Base Address Register (0x0005) DESCRIPTOR TABLE BASE ADDRESS 15:0 0 A A A A A A 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 LSB MSB 15 14 13 12 11 10 9 This 16-bit register is Read-Write and is fully maintained by the host. This register is loaded with 0x0200 after MR pin master reset or SRST software reset. The host maintains this register to specify the starting address for the Descriptor Table. For fast context switching, the host may initialize multiple Descriptor Tables, then update this register to load the new base address when the active Descriptor Table changes. The base address must be chosen with bits 7:0 = 00000000. These bits (and the highest address bit) cannot be set in the register. The primary Descriptor Table HOLT INTEGRATED CIRCUITS 30 HI-6120, HI-6121 (enabled at reset) should reside at address space 0x0200 to 0x03FF. Other tables (if used) could begin at address multiples of 0x0200, like 0x0400 and 0x0600. Bit 15 and bits 8:0 cannot be set and will always read logic 0. Thus a value written by the host must equal or exceed 0x200. 5.7. Pending Interrupt Register (0x0006) This 16-bit register is Read-Only. If the corresponding bit is set in the Interrupt Enable Register when a predetermined interrupt-causing event occurs, these actions occur: (1) a pending interrupt bit is set in this register, (2) the INTMES or INTHW output is asserted, depending on interrupt type, (3) the interrupt is registered in the Interrupt Log. If the corresponding bit is reset in the Interrupt Enable Register when a predetermined interrupt-causing event occurs, there is no reaction. To simplify host interrupt management, when the host reads this register, the Pending Interrupt Register automatically resets to 0x0000 and (if level interrupts are enabled by the INTSEL configuration bit) the INTMES and/or INTHW output pins are automatically negated. For further information on interrupt behavior, also see descriptions for Interrupt Enable register and Interrupt Log Address register, and refer to the later section entitled “Interrupt Management”. EQ IW Z A IB R X X X 8 7 6 5 4 3 2 1 0 LSB MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset. Bit No. Mnemonic R/W Reset Function Index Equal Zero Interrupt. If the IXEQZ bit is set in the Interrupt Enable register and the subaddress descriptor Control Word allows the IXEQZ interrupt, this bit is asserted for (a) subaddresses using indexed buffer mode when the index decrements from 1 to 0, or (b) subaddresses using circular buffer modes when the pre-determined number of messages has been transacted. The INTMES output is asserted and the Interrupt Log is updated. Interrupt When Accessed. 14 IWA R 0 If the IWA bit is set in the Interrupt Enable register and the subaddress descriptor Control Word allows the IWA interrupt, this bit is asserted each time a valid legal message is transacted for the subaddress. The INTMES output is asserted and the Interrupt Log is updated. Broadcast Command Received Interrupt. 13 IBR R 0 If the IBR bit is set in the Interrupt Enable register and the subaddress descriptor Control Word allows the IBR interrupt, this bit is asserted each time a valid legal broadcast message is transacted for the subaddress. The INTMES output is asserted and the Interrupt Log is updated. Not used. 15 IXEQZ R 12,11 ----- R IL C M SP D IF LB AIL FA LB FB TT IN TT T1 IN RT T0 AP EE F C R KF AM IF IX M ER R 0 0 HOLT INTEGRATED CIRCUITS 31 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Message Error Interrupt. 10 MERR R 0 If the MERR bit is set in the Interrupt Enable register, this bit is asserted when a message error is detected. Errors can be caused by Manchester encoding problems or protocol errors. The INTMES output is asserted and the Interrupt Log is updated. Not used. Illegal Command Interrupt. 8 ILCMD R 0 If the ILCMD bit is set in the Interrupt Enable register, this bit is asserted each time an illegal message (determined by the Illegalization Table) occurs for a new command. The INTMES output is asserted and the Interrupt Log is updated. See section “Illegalization Table” for additional information. SPI Fail Interrupt (HI-6121 only). 7 SPIFAIL R 0 The HI-6121 uses a SPI interface for host access. The device operates in SPI Slave mode. If the SPIFAIL bit is set in the Interrupt Enable register, this bit is asserted each time an incorrect number of SCK clocks occurs during SPI chip select assertion, The INTHW output is asserted and the Interrupt Log is updated. Loopback Fail Bus A and Loopback Fail Bus B Interrupts. 6,5 LBFA, LBFB R 0 During all transmitted command responses, the device compares words transmitted to the received and decoded words detected on the bus. If the LBFA or LBFB bit is set in the Interrupt Enable register, this bit is asserted each time this loopback detects mismatch. The INTMES output is asserted and the Interrupt Log is updated. Time-Tag Interrupt 1. 4 TTINT1 R 0 If the TTINT1 bit is set in the Interrupt Enable register, this bit is asserted each time the free-running Time-Tag counter value matches the value stored in the Time-Tag Utility Register. The INTHW output is asserted and the Interrupt Log is updated. Time-Tag Interrupt 0. 3 TTINT0 R 0 If the TTINT0 bit is set in the Interrupt Enable register, this bit is asserted each time the free-running Time-Tag counter value rolls over from full count 0xFFFF to 0x0000. The INTHW output is asserted and the Interrupt Log is updated. RT Address Parity Fail Interrupt. This bit is asserted when RT address and parity bits latched in the Operational Status Register do not exhibit odd parity (odd number of bits having logic 1 state). Because the RTAPF bit is always set in the Interrupt Enable register, the INTHW output is asserted and the Interrupt Log is updated. When parity error occurs, the RT will not begin operation, regardless of the state of the Control Register STEX bit. Initialization EEPROM Checksum Fail Interrupt. 1 EECKF R 0 This bit is asserted if serial EEPROM checksum failure occurs during autoinitialization. Because the EECKF bit is always set in the Interrupt Enable register, the INTHW output is asserted and the Interrupt Log is updated. 9 ----- R 0 2 RTAPF R 0 HOLT INTEGRATED CIRCUITS 32 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function RAM Initialization Fail Interrupt. 0 RAMIF R 0 This bit is asserted after auto-initialization if an initialized RAM location does not match its 2 corresponding serial EEPROM locations. Because the RAMIF bit is always set in the Interrupt Enable register, the INTHW output is asserted and the Interrupt Log is updated. 5.8. 1553 Status Word Bits Register (0x0007) This 16-bit register is Read-Write and is fully maintained by the host. All bits are active high. Bits set in this register are reflected in the outgoing MIL-STD-1553 status word. D C LR EQ C R BU ) * S SS Y YS F E) * ST AN TX SV C R TF (M IN (B 0 0 0 0 0 8 0 7 0 6 0 5 0 4 3 2 0 1 0 LSB MSB 15 14 13 12 11 10 9 * STATUS BIT AUTOMATICALLY CONTROLLED BY DEVICE The”dynamic bus control acceptance” bit is not implemented; this device cannot function as bus controller. The host controls the Instrumentation, Busy, Terminal Flag, Service Request and Subsystem Flag status word bits by writing to bits 9:0 in this register. Remote terminal status word responses reflects the assertion of these register bits until negated by the host, unless the Immediate Clear function (bit 15) is enabled. The position of register bits 4 and 10 correspond to the Broadcast Command Received (BCR) and Message Error (ME) bits in the terminal status word. Transmit state for the BCR and ME bits in the terminal’s status word is controlled by the device, based on prior command transactions. This pair of register bits cannot be set by a host write operation and always read back logic 0, so do not reflect the true status of these status flags. NOTE: ‘Reset’ refers to bit value following either Master Reset (MR) or software reset. Bit No. Mnemonic R/W Reset Function Transmit (Once) and Clear. When this bit is set, the register is cleared after any set bits 0-9 are used once in a transmitted status word. This bit does not affect operation of the Transmit Status Word and Transmit Last Command mode codes. Example: Transaction of a valid legal command with the INST and TXANDCLR bits asserted results in status word transmission with the Instrumentation bit set. If the following command is Transmit Status or Transmit Last Command mode code, the Instrumentation bit remains set. Not used, these bits cannot be set. Instrumentation. When this bit is asserted, the Instrumentation status bit is set. Service Request. When this bit is asserted, the Service Request status bit is set. Not used, these bits cannot be set. 15 TXANDCLR R/W 0 14-10 9 8 7-4 ----INST SVCREQ ----- R R/W R/W R 0 0 0 0 HOLT INTEGRATED CIRCUITS 33 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Busy (global). When this bit is asserted, the device asserts Busy bit in status response for all valid commands. Instead of globally enabling Busy status for all commands here, the host can assert Busy status for selected commands by asserting the Busy bit in descriptor table Control Words for the individual commands. When response to a command conveys Busy status, the device suppresses transmission of data words that would normally accompany status transmission. For any message transacted with Busy status, the WASBUSY flag is asserted in the stored Message Information Word. Subsystem Flag. This register bit is logically ORed with the SSYSF input pin. If either SSYSF register bit or SSYSF pin is asserted, the SSYSF Subsystem Flag status bit is set. If the Configuration Register 2 MCOPT1 bit equals 0, reception of a “transmit vector word” mode command (MC16) causes automatic reset of the SSYSF status bit in this register; when this occurs, the register bit is reset before status word transmission begins. Not used, this bit cannot be set. Terminal Flag. When this bit is asserted, the Terminal Flag status bit is set. 3 BUSY R/W 0 2 SSYSF R/W 0 1 0 ----TF R R/W 0 0 5.9. Time-Tag Register (0x0008) This register is Read Only and is cleared after MR pin Master Reset or SRST software reset. Reads to this register address return the current value of the free running 16-bit Time Tag counter. Counter resolution is programmed by TTCK2:0 bits in Configuration Register 1. Options are: 2, 4, 8, 16, 32 and 64us, or externally provided clock. TIME-TAG COUNT 15:0 15 14 13 12 11 10 9 MSB 15 14 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LSB The device automatically resets the Time-Tag count when a “synchronize” mode command without data (MC1) is received. In addition, the host can reset the Time-Tag count at any time by asserting the RTTAG bit in Configuration Register 2. The MCOPT2 and MCOPT3 bits in Configuration Register 2 allow automatic loading of Time-Tag count using the data word received with a “synchronize with data” mode command, MC17. If both of these bits equal one, the data word received with a valid “synchronize” mode command (MC17) is unconditionally loaded into the Time-Tag counter. For non-broadcast MC17 commands, the counter load occurs before status word transmission. If both MCOPT2 and MCOPT3 bits equal 0, the external host assumes responsibility for actions needed to perform “synchronize” duties upon reception of the valid MC17 “synchronize” command, but status transmission automatically occurs. The binary 01 and 10 combinations of the MCOPT2 and MCOPT3 bits support certain extended subaddressing schemes. If the MCOPT3-MCOPT2 bits equal 01, the received data word is automatically loaded into the Time-Tag counter if the low order bit of the received data word (bit 0) equals 0. If the MCOPT3-MCOPT2 bits equal 10, the received data word is automatically loaded into the Time-Tag counter if the low order bit of the received data word (bit 0) equals 1. For non-broadcast MC17 commands, the counter load occurs before status word transmission. HOLT INTEGRATED CIRCUITS 34 HI-6120, HI-6121 5.10. Interrupt Log Address Register (0x0009) This 16-bit register is Read-Only and is fully maintained by HI-6120/21 logic. The register contains 0x0040 after MR pin master reset but is not affected by SRST software reset. Bits 7:0 contain an address pointer for the 32-word Interrupt Log Buffer located in shared RAM. The value in Interrupt Log Address register bits 7:0 indicates the storage address where interrupt information words will be stored for the next occurring interrupt, 0x40 - 0x5E. The value is always even since two words are stored for each interrupt. Bits 15:8 contain a count value for the number of interrupts logged (0 - 255) since the Interrupt Log Address Register was last read. The count increment stops at 255. Bits 15:8 are reset automatically after this register is read by the host. INTERRUPT COUNT 7:0 C C C C C C C C 8 0 7 1 6 MSB 15 14 13 12 11 10 9 INTERRUPT LOG ADDRESS 7:0 0 5 A 4 A 3 A 2 A 1 0 0 LSB To help the host process interrupts, the device maintains information from the 16 most recent interrupts in a 32-word ring buffer in shared RAM, found at address range 0x0040 to 0x005F. Each interrupt stores two information words: the Interrupt Identification Word (IIW) identifies the interrupt type(s) that occurred; the Interrupt Address Word (IAW) identifies the interrupt source. For interrupts that result from message processing, the IAW contains the 16-bit address of the command’s Control Word in the Descriptor Table. For hardware interrupts, the IAW value is 0x0000. After MR master reset, the device automatically resets this register to 0x0040, an interrupt count of zero and log address of 0x40. During terminal operation, the host can read bits 15:8 to see the number of interrupts logged in the buffer since the last read operation upon the register. Information words for the sixteenth interrupt are stored in buffer addresses 0x005E and 0x005F, and the Interrupt Log Address “rolls over” to read 0x40, where interrupt information for the seventeenth interrupt will be stored. For further information on interrupts, see descriptions for the Interrupt Enable register, the Pending Interrupt register, and see the later section entitled “Interrupt Management”. 5.11. Current Message Information Word Address Register (0x000A) This 16-bit register is Read-Only and is fully maintained by the device. This register is cleared after MR pin master reset, but is not affected by SRST software reset. Also see “Current Control Word Address” register, 0x0004. CURRENT MSG INFO WORD ADDRESS 15:0 A A A A A A A A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 LSB MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset. Bit No. Mnemonic R/W Reset Function Current Message Information Word Address Register 15-0 MIWA15:0 R/W 0 This register contains the data buffer address for the last command’s Message Information Word, or MIW, corresponding to the current command stored in the Current Command Register (0x0003). This register is updated 5us after the ACTIVE output is asserted. Bit 15 is MSB. HOLT INTEGRATED CIRCUITS 35 HI-6120, HI-6121 5.12. Memory Address Pointer Register (HI-6121 only) (0x000F) This register is Read-Write and is cleared after MR pin master reset, but is not affected by SRST software reset. This register is maintained by the host. The contained value is a memory address used when fulfilling RAM or register read or write operations via the HI-6121 Serial Peripheral Interface (SPI). See data sheet section, ”Host Serial Peripheral Interface (SPI)” for further details. For HI-6120 devices, writes to this address have no effect; the address reads back 0x0000 if a host read cycle occurs. MEMORY ADDRESS 15:0 15 14 13 12 11 10 9 MSB 15 14 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LSB 5.13. Interrupt Enable Register (0x0010) This 16-bit register is Read-Write (except bits 2-0 are read only) and is fully maintained by the host. All bits are active high. For further information on interrupts, see descriptions for the Pending Interrupt and Interrupt Log Address registers, and refer to the later section entitled “Interrupt Management”. X X X 8 7 6 5 4 3 MSB 15 14 13 12 11 10 9 An interrupt type is globally disabled when the corresponding bit in this register is reset. This allows the external host or subsystem to temporarily disable interrupt servicing for some or all interrupts. While an interrupt enable bit is negated, the terminal does not generate an interrupt output signal for the corresponding interrupt event. Note: Asserting an interrupt bit in this register after an event occurs does not generate an interrupt for that event. For some interrupts that result from message processing, interrupt enable bits in a each command’s descriptor Control Word act in combination with settings in this register to respond appropriately to interrupt-causing events. NOTE: ‘Reset’ refers to bit value following Master Reset (MR). This register is unaffected by software reset. Bit No. Mnemonic R/W Reset Function Index Equal Zero Interrupt. When this bit is asserted, interrupts are globally enabled for (a) subaddresses using indexed buffer mode when the index decrements from 1 to 0, and (b) subaddresses using a circular buffer mode when the pre-determined number of messages has been transacted. When this bit is asserted, occurrence of an IXEQZ event (a) or (b) causes INTMES output assertion (if the IXEQZ bit is set in the command’s descriptor Control Word). Interrupt When Accessed Interrupt. 14 IWA R/W 0 When this bit is asserted, interrupts are globally enabled for each message occurrence to subaddresses in which the Descriptor Control Word allows the IWA interrupt. When this bit is asserted, occurrence of an IWA event causes INTMES output assertion (if the IWA bit is set in the command’s descriptor Control Word). 15 IXEQZ R/W IL C M SP D IF LB AIL FA LB FB TT IN TT T1 IN RT T0 AP EE F C R KF AM IF EQ IW Z A IB R IX M ER R 1 2 1 1 1 0 LSB 0 HOLT INTEGRATED CIRCUITS 36 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Broadcast Command Received Interrupt. 13 IBR R/W 0 When this bit is asserted, interrupts are globally enabled for each broadcast message to subaddresses in which the Descriptor Control Word allows the IBR interrupt. When this bit is asserted, occurrence of an IBR event causes INTMES output assertion (if the IBR bit is set in the command’s descriptor Control Word). Not Used. Message Error Interrupt. When this bit is high, the INTMES interrupt output is asserted when a message error is detected. Errors are caused by Manchester encoding problems or protocol errors. Interrupt assertion occurs whenever the terminal sets the ME “message error” bit in the terminal’s status word. The detected error type can be found in Message Information Word stored as a result of message processing. Not Used. Illegal Command Interrupt. Illegal commands are defined in the Illegalization Table. When enabled, the ILCMD interrupt is asserted when the Illegalization Table bit corresponding to the received command is logic 1. The Illegalization Table should only contain nonzero values when “illegal command detection” is being applied. When illegal commands are received, the terminal responds by transmitting status word with ME “message error” flag set; no data words are transmitted. If this ILCMD bit is high, all illegal commands cause INTMES interrupt output assertion. See next section entitled “Pending Interrupt Register” (below) and the section entitled “Illegalization Table” for further information. SPI Fail Interrupt (HI-6121 only). 7 SPIFAIL R.W 0 The HI-6121 uses a SPI interface for host access. The device operates in SPI Slave mode. When this bit is high, the INTHW output is asserted and the Interrupt Log is updated each time an incorrect number of SCK clocks occurs during SPI chip select assertion. Loopback Fail Bus A and Loopback Fail Bus B Interrupts. 6,5 LBFA, LBFB R/W 0 During all transmitted command responses, the device compares words transmitted to the received and decoded words detected on the bus. When this bit is high, the INTMES output is asserted and the Interrupt Log is updated each time loopback detects word mismatch. Time-Tag Interrupt 1. 4 TTINT1 R/W 0 If this bit is logic 1, the INTHW interrupt output is asserted and the TTINT1 bit is set in the Pending Interrupt register each time the free-running TimeTag counter value matches the value stored in the Time-Tag Utility Register. 12,11 ----- R/W 0 10 MERR R/W 0 9 ----- R/W 0 8 ILCMD R.W 0 HOLT INTEGRATED CIRCUITS 37 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Time-Tag Interrupt 0. 3 TTINT0 R/W 0 If this bit is logic 1, the INTHW interrupt output is asserted and the TTINT0 bit is set in the Pending Interrupt register each time the free-running TimeTag counter value rolls over from 0xFFFF full count to 0x0000. RT Address Parity Fail Interrupt. 2 RTAPF R 1 When this bit is high, the INTHW interrupt is asserted when RT address parity error is detected. This bit is 1 after MR master reset and cannot be reset by host register write. Initialization EEPROM Checksum Fail Interrupt. 1 EECKF R 1 When this bit is high, the INTHW interrupt is asserted if serial EEPROM checksum failure occurs during auto-initialization. This bit is 1 after MR master reset and cannot be reset by host register write. RAM Initialization Fail Interrupt. 0 RAMIF R 1 When this bit is high, the INTHW interrupt is asserted after auto-initialization if an initialized RAM location does not match its 2 corresponding serial EEPROM locations. This bit is 1 after MR master reset and cannot be reset by host register write. The Interrupt Enable Register lets the host temporarily or permanently disable interrupt servicing for some or all interrupt types. When bits are reset in this register, interrupt output signals are globally disabled for the corresponding interrupt types. Asserting a bit in the Interrupt Enable register after an event occurs does not generate an interrupt for that event. The IXEQZ, IWA and IBR interrupts result from message processing. The host can enable or disable these three interrupt types for individual subaddresses and mode code commands by setting or resetting the IXEQZ, IWA and IBR bits in descriptor table Control Words corresponding to each subaddress or mode command. While the ILCMD and MERR interrupts also result from message processing, these interrupts (along with all hardware interrupts) are globally enabled or disabled, and are unaffected by descriptor table settings. Table gives a summary of settings and responses to interrupt-causing messages. Table 5. Settings and Responses to Interrupt-Causing Messages SETTING Descriptor Control Word IXEQZ, IWA & IBR Bits Reset Set Set All Interrupts Except IXEQZ, IWA & IBR (no Control Word bits) Interrupt Enable Register Bit for Interrupt Type Don’t Care Reset Set Reset Set RESPONSE Effect on Corresponding Bit in Pending Interrupt Register No Change No Change Pending Int. Register bit is set No Change Pending Int. Register bit is set Is Interrupt Output Signal Generated No No Yes No Yes 5.14. Time-Tag Utility Register (0x0011) This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset, but is not affected by SRST software reset. This register has two functions associated with the free-running Time-Tag counter: HOLT INTEGRATED CIRCUITS 38 HI-6120, HI-6121 TIME-TAG UTILITY15:0 15 14 13 12 11 10 9 MSB 15 14 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LSB Function 1: When Configuration Register 2 is written causing a 0 to 1 transition of the TTLOAD bit, the value contained in the Time-Tag Utility register is loaded into the Time-Tag counter. Function 2: If the TTINT1 bit in the Interrupt Enable register is set, the Interrupt Pending register TTINT1 bit is set and the INTHW interrupt output is asserted each time the free-running Time-Tag counter value matches the value stored in the Time-Tag Utility register. 5.15. Bus A Select Register (0x0012) This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset, but is not affected by SRST software reset. The Bus A Select register is only used when the MCOPT4 bit in Configuration Register 2 equals 0. This MCOPT4 setting means the device automatically fulfills mode commands MC20 (decimal) “selected transmitter shutdown” or MC21 “override selected transmitter shutdown”. BUS A SELECT REGISTER15:0 15 14 13 12 11 10 9 MSB 15 14 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LSB “Transmitter shutdown” or “shutdown override” can only occur for the inactive bus. If either mode command is received on Bus B, the inactive bus is Bus A. The device compares the received mode data word to the contents of the Bus A Select register to determine whether inactive Bus A is selected for “transmitter shutdown” or “transmitter shutdown override”. (Bus shutdown or shutdown override can only occur for the inactive bus.) If the data word matches the value stored in the Bus A Select register and MCOPT4 equals 0, the device automatically fulfills MC20 “transmitter shutdown” or MC21 “shutdown override” without host assistance: If the mode command received was MC20, the Transmit Shutdown A bit in the built-in test (BIT) word is asserted. If mode command MC21 was received, the Transmit Shutdown A bit in the BIT Word is negated. Refer to Configuration Register 2 description of MCOPT4 bit for additional details. 5.16. Bus B Select Register (0x0013) This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset, but is not affected by SRST software reset. The Bus B Select register is only used when the MCOPT4 bit in Configuration Register 2 equals 0. This MCOPT4 setting means the device automatically fulfills mode commands MC20 (decimal) “selected transmitter shutdown” or MC21 “override selected transmitter shutdown”. BUS B SELECT REGISTER15:0 15 14 13 12 11 10 9 MSB 15 14 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LSB “Transmit shutdown” or “shutdown override” can only occur for the inactive bus. If either mode command is received on Bus A, the inactive bus is Bus B. The device compares the received mode data word to the contents of the Bus B Select register to determine whether inactive Bus B is selected for “transmitter shutdown” or “transmitter shutdown override”. If the data word matches the value stored in the Bus B Select register and MCOPT4 equals 0, the device automatically fulfills MC20 “transmit shutdown” or MC21 “shutdown override” without host assistance: If the mode HOLT INTEGRATED CIRCUITS 39 HI-6120, HI-6121 command received was MC20, the Transmit Shutdown B bit in the built-in test (BIT) word is asserted. If mode command MC21 was received, the Transmit Shutdown B bit in the BIT Word is negated. Refer to Configuration Register 2 description of MCOPT4 bit for additional details. 5.17. Built-in Test Word Register (0x0014) Bits 4-11 in this 16-bit register are read-write, the remaining bits are read-only. The ten assigned bits are written by the device when predetermined events occur. The host may overwrite the device-written bits 5 and 4. After MR pin master reset, bits 13-12, 5-4 and 0 are reset. Bits 15-14 will be set if the corresponding TXINHA or TXINHB input pins are high. Bits 3-1 will be set if RT address parity error, or post-MR memory test or auto-initialization failure occurred. UNASSIGNED BITS ARE USER DEFINED MSB 15 14 13 12 11 10 9 8 7 6 5 If the ALTBITW option bit in Configuration Register 2 is zero when a valid “transmit BIT word” mode command (MC19) is received, the current value in this register is transmitted as the mode data word in the terminal response. The value is also copied to the assigned data buffer for MC19, after mode command fulfillment. NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The value “PIN” denotes the bit is set to the value of the corresponding pin following Master Reset. The bit value following software reset is unchanged unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset Function Transmitter A Shutdown. Transmitter B Shutdown. 15 14 TXASD TXBSD R PIN These read-only bits are set when the corresponding bus transmitter was disabled by assertion of the bus TXINHA or TXINHB input pin, or by fulfillment of a “transmitter shutdown” mode command MC4 or MC20. Refer to the description for the SDSEL bit in Configuration Register 1 and the description for the MCOPT4 bit in Configuration Register 2 for further information. Receiver A Shutdown. Receiver B Shutdown. 13 12 RXASD RXBSD R SR = 0 SR = PIN 0 These read-only bits are set when the corresponding bus receiver was disabled concurrently with the bus transmitter by a “transmitter shutdown” mode command MC4 or MC20. Refer to the description for the SDSEL bit in Configuration Register 1 and the description for the MCOPT4 bit in Configuration Register 2 for further information. User defined. Host can write any value. Built-In-Self-Test (BIST) Loopback Fail Bus A (see Section 5.20). This bit is set if Bus A loopback failure error occurs during built-in self-test. BIST Loopback Fail Bus B (see Section 5.20). This bit is set if Bus B loopback failure error occurs during built-in self-test 11-6 5 4 ----BLBFA BLBFB R/W R R 0 SR = 0 0 0 SR = 0 B BL FA B BM FB T RT F AP EE F L TF F BI N H A TX SD B R SD XA R SD XB SD TX BL 4 3 2 1 0 LSB HOLT INTEGRATED CIRCUITS 40 HI-6120, HI-6121 Bit No. Mnemonic R/W 3 BMTF R Reset Test Result Function BIST Memory Test Fail (see Section 5.20). This bit is set if error occurs during built-in self-test for device RAM memory. RT Address Parity Failure. 2 RTAPF R Test Result This bit is asserted when Operational Status Register bits 15:10 reflect parity error. After MR master reset, bits 15:10 in the Operational Status Register reflect input pin states, but will be overwritten if subsequent auto-initialization is performed (if AUTOEN pin is high) and the initialization EEPROM contains different data for Operational Status Register bits 15:10. Auto-Initialization EEPROM Load Fail. 1 EELF R Test Result This bit only applies when auto-initialization is enabled (AUTOEN input pin state equals 1). This bit is set if, after MR master reset, failure occurs when copying serial EEPROM to registers and RAM. When this occurs, bit 0 or bit 1 will be set in the Operational Status Register (0x0002) to indicate type of failure. Terminal Flag Bit Inhibited. 0 TFBINH R SR = 0 0 This bit is set when the Terminal Flag status bit is disabled while fulfilling an “inhibit terminal flag bit” mode code command (MC6). This bit is reset if terminal flag status bit disablement is later cancelled by an “override inhibit terminal flag bit” mode code command (MC7). 5.18. Alternate Built-in Test Word Register (0x0015) This 16-bit register is Read-Write and is fully maintained by the external host. This register is cleared after MR pin master reset but is unaffected by SRST software reset. ALTERNATE BUILT-IN TEST WORD REGISTER15:0 15 14 13 12 11 10 9 MSB 15 14 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LSB If the ALTBITW option bit in Configuration Register 2 equals one when a valid “transmit BIT word” mode command (MC19) is received, the current value in this register is transmitted as the mode data word in the terminal response. The value is also copied to the assigned data buffer for MC19, after mode command fulfillment. 5.19. Reserved Register (0x0016) Register 0x0016 is used for factory testing. It is cleared after MR pin master reset and cannot be written by the host while the TEST input pin is low. 5.20. Test Control Register (0x0017) This register controls RAM built-in self-test, and transceiver loopback testing. Bits 0, 1, 8, 9 are Read Only. The remaining bits in this register are Read-Write but can be written only when the TEST input pin is high. If TEST = 0, these bits will read back 0x0000. HOLT INTEGRATED CIRCUITS 41 HI-6120, HI-6121 This register supports two types of test: Register bits 15 - 8 are used for RAM built-in self test (RAM BIST). Register bits 7 - 2 are used for transceiver loopback testing (either digital loopback or analog loopback). FR A R MA BF R FA BS IL R EL BS 2 R EL BS 1 R EL0 BS R TR BP T R AS BF S AI L 0 MSB 15 14 13 12 11 10 9 8 7 0 6 5 4 3 2 1 0 LSB Under internal logic control, this device uses one RAM self test (Inc / Dec Test described below) to check internal RAM memory after MR pin master reset. Test Control Register bits 15 - 8 provide a means for the host to perform RAM self-test at other times. Register bits 13:11 select RAM test type. Then bit 10 starts the selected RAM test, and bits 9-8 report a pass/fail result after test completion. All tests are destructive, overwriting data present before test commencement. NOTE: ‘Reset’ refers to bit value following either Master Reset (MR) or software reset. Bit No. Mnemonic R/W Reset Function Full RAM Access Enable. 15 FRAMA R/W 0 During normal operation, some bits in certain RAM locations (e.g., Descriptor Table Control Words) cannot be written by the host. When the FRAMA bit is asserted, host writes to RAM are unrestricted to permit full testing. During normal completion, this bit must be reset to logic 0. RAM BIST Force Failure. 14 RBFFAIL R/W 0 When this bit is asserted, RAM test failure is forced to verify that RAM BIST logic is functional. RAM BIST Select Bits 2-0. This 3-bit field selects the RAM BIST test mode applied when the RBSTART bit is set: RBSEL2:0 Selected RAM Test 000 001 010 13,12,11 RBSEL2:0 R/W 0 011 100 101 110 111 Idle Pattern Test, described below Write 0x0000 to RAM address range 0x0000 0x7FFF Read and verify 0x0000 over RAM address range 0x0000 - 0x7FFF Write 0xFFFF to RAM address range 0x0000 0x7FFF Read and verify 0xFFFF over RAM address range 0x0000 - 0x7FFF Inc / Dec Test performs only steps 5 - 8 of the Pattern Test below Idle Test Time 14.42ms 170μs 500μs 170μs 500μs 1.32ms - LB AL LB OG S LB YN BU C LB SE ST L LB AR PA T LB SS FA IL HOLT INTEGRATED CIRCUITS 42 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Description of the RAM BIST “PATTERN” test selected when register bits RBSEL2:0 = 001: Note: Test read /write accesses to addresses 0x0000 - 0x001F involve 32 RAM locations not accessible to the host. These accesses do not affect the host-accessible registers, overlaying the same address range. 1. Write 0x0000 to all RAM locations, 0x0000 through 0x7FFF. 2. Repeat the following sequence for each RAM location from 0x00000 through 0x7FFF: a. b. c. d. e. f. g. h. i. j. 13,12,11 RBSEL2:0 (continued) R/W 0 Read and verify 0x0000 Write then read and verify 0x5555 Write then read and verify 0xAAAA Write then read and verify 0x3333 Write then read and verify 0xCCCC Write then read and verify 0x0F0F Write then read and verify 0xF0F0 Write then read and verify 0x00FF Write then read and verify 0xFF00 Write 0x0000 then increment RAM address and go to step (a) 3. Write 0xFFFF to all RAM locations, 0x0000 through 0x7FFF 4. Repeat the following sequence for each RAM location from 0x00000 through 0x7FFF: a. b. c. d. e. f. g. h. i. j. Read and verify 0xFFFF Write then read and verify 0x5555 Write then read and verify 0xAAAA Write then read and verify 0x3333 Write then read and verify 0xCCCC Write then read and verify 0x0F0F Write then read and verify 0xF0F0 Write then read and verify 0x00FF Write then read and verify 0xFF00 Write 0xFFFFthen increment RAM address and go to step (a) 5. Write each cell’s memory address into each RAM location from 0x00020 to 0x7FFF. 6. Read each memory location from 0x00000 to 0x7FFF and verify it contains its address. 7. Write 1s complement of each cell’s memory address, into each RAM location (same addr range). 8. Read each memory location and verify it contains the 1s complement of its address. RAM BIST Start. 10 RBSTRT R/W 0 Writing logic 1 to this bit initiates the RAM BIST test selected by register bits RBSEL2:0. The RBSTRT bit can only be set if the TEST input pin is high and if register bit 15 is already asserted. This bit is automatically cleared upon test completion. Register bits 9-8 indicate pass / fail test result. HOLT INTEGRATED CIRCUITS 43 HI-6120, HI-6121 Bit No. 9 Mnemonic RBPASS R/W Reset Function RAM BIST Pass. R 0 Device logic asserts this bit when the selected RAM test completes without error. This bit is automatically cleared when RBSTRT bit 10 is set. RAM BIST Fail. Device logic asserts this bit when failure occurs while performing the selected RAM test. This bit is automatically cleared when RBSTRT bit 10 is set. When BIST failure occurs, a clue to the failing RAM address can be read at register address 0x001E. For speed, the RAM BIST concurrently tests 4 quadrants of the RAM address range, in parallel. If test failure occurs, register address 0x001E contains the RAM address being tested in the lowest RAM quadrant. Actual failure will occur in any of these four locations: at RAM address “ADDR” stored in register 0x001E, or ADDR+0x2000, or ADDR+0x4000 or ADDR+0x6000. Not Used. These bits cannot be set. A READ will return 0x0000. Loopback Test Analog. The device supports either digital or analog loopback testing for either bus transceiver. When the LBALOG bit is low, digital loopback is selected and no data is transmitted onto the selected external MIL-STD-1553 bus. When the LBALOG bit is high, analog loopback is selected and a test word is transmitted onto and received from the selected external MIL-STD-1553 bus. Loopback Test Word Sync Select. 4 LBSYNC R/W 0 When the LBSYNC bit is high, the loopback test word is transmitted with command sync. When the LBSYNC bit is low, the loopback test word is transmitted with data sync. Loopback Test Bus Select. 3 LBBUSEL R/W 0 When this bit is low, loopback testing occurs on Bus A. When this bit is high, loopback testing occurs on Bus B. Loopback Test Start. 2 LBSTART R/W 0 Writing logic 1 to this bit initiates the loopback test selected by register bits 3, 4 and 5. The LBSTRT bit can only be set if the external TEST pin is already asserted, and is automatically cleared upon test completion. Register bits 1,0 indicate pass / fail test result. Loopback Test Pass. 1 LBPASS R 0 Device logic asserts this bit when the selected RAM test completes without error. This bit is automatically cleared when LBSTART bit 2 is set. Loopback Test Fail. 0 LBFAIL R 0 Device logic asserts this bit when failure occurs while performing the selected loopback test. Failure is comprised of Manchester encoding error, parity error, wrong sync type or data mismatch. This bit is automatically cleared when LBSTART bit 2 is set. 8 RBFAIL R 0 7,6 ----- R 0 5 LBALOG R/W 0 HOLT INTEGRATED CIRCUITS 44 HI-6120, HI-6121 5.21. Loopback Test Transmit Data Register (0x0018) This 16-bit register is Read-Write and is fully maintained by the host. This register is cleared after MR pin master reset, but is not affected by SRST software reset. The value contained in this register is used when performing digital loopback testing. See Test Control Register, 0x0016, for additional information. LOOPBACK TEST TRANSMIT DATA REGISTER15:0 15 14 13 12 11 10 9 MSB 15 14 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LSB 5.22. Loopback Test Receive Data Register (0x0019) This 16-bit register is Read-Only. This register is cleared after MR pin master reset, but is not affected by SRST software reset. Data is written to this register when performing digital loopback testing. See Test Control Register, 0x0016, for additional information. LOOPBACK TEST RECEIVE DATA REGISTER15:0 15 14 13 12 11 10 9 MSB 15 14 13 12 11 10 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 LSB HOLT INTEGRATED CIRCUITS 45 HI-6120, HI-6121 6. COMMAND RESPONSES A brief review of MIL-STD-1553 commands and responses is appropriate here to establish terminology used in the rest of this data sheet. Shown in Figure 3, each command word is comprised of a sync field, three 5-bit data fields, a single bit denoting Transmit / Receive direction and ends with a parity bit. The hardware decoder uses the sync field to determine word type (command vs. data). Word validity is based on proper sync encoding, Manchester II encoding, correct bit count and correct odd parity for the 16 data bits. Once a valid word with command sync is found, the sync and parity are stripped before the command’s 16 data bits are stored for further processing. Command Sync T/R Bit to mode code commands by the mode code number. For example, a mode command with 5-bit mode code field of 0x10 is called MC16, and the full range of mode code values is MC0 through MC31 (decimal). Mode codes MC16 through MC31 (0x10 through 0x1F) have a single associated data word. When the command T/R bit equals 0, the data word is contiguous with the command word and received by the RT. When the command’s T/R bit equals 1, the data word is transmitted by the RT, following the terminal’s transmitted status word. Mode codes MC0 through MC15 (0x0F) do not have associated data words. For these 16 commands, the command T/R bit does not specify “direction”. These commands must be transmitted with T/R bit equal to 1. If the T/R bit is 0, the mode command is “undefined”. Twenty-two mode commands are “undefined mode commands ” in MIL-STD-1553B: Word Count Field * Parity Bit Terminal Address Field Subaddress (SA) Field * Word Count field is replaced by Mode Code field when the SA field equals 0x00 or 0x1F Mode Codes 0 through 15 with T/R bit = 0 Mode Codes16, 18 and19 with T/R bit = 0 Mode Codes 17, 20 and 21 with T/R bit = 1 The UMCINV bit in Configuration Register 1 determines how these undefined mode commands are handled by the HI-6120/21. If the UMCINV configuration bit equals 1, the undefined mode commands are treated as invalid. They are not recognized by the device. There is no terminal response and status is not updated. If the UMCINV configuration bit equals 0, the 22 undefined mode commands are considered valid; this is the default condition following reset. For this case, terminal response depends on whether or not the application uses “illegal command detection.” If illegal command detection is not used, all Illegalization Table entries should be logic 0, including the 22 entries for these undefined commands. (The Illegalization Table is fully described in Section 7 on page 48. After MR reset, all entries equal logic 0.) The terminal responds “in form”, transmitting clear status (and a single mode data word if the command is MC17, MC20 or MC21 with T/R bit = 1). Terminal status is updated. If illegal command detection applies, the Illegalization Table entries for these 22 undefined commands should be initialized to logic 1. In this case, the terminal will respond with status word only, with Message Error bit set. No mode data word is transmitted. Terminal status is updated. Twenty-seven mode codes are considered “reserved” in MIL-STD-1553B: Figure 3. MIL-STD-1553 Command Word Structure A “valid command” can be specifically addressed to the individual HI-6120 terminal (the command word’s embedded Terminal Address field matches the terminal address latched in the Operational Status register) or can be a “broadcast command” addressed to all terminals. Broadcast commands are always addressed to RT address 31 (0x1F). In systems where broadcast commands are disallowed, RT31 is not used as a conventional terminal address. When set, the BCSTINV bit in Configuration Register 1 renders RT31 commands as “invalid”: broadcast commands are indistinguishable from commands addressed to other terminals. Invalid commands are simply disregarded. When the command word’s 5-bit SA (subaddress) field is in the range of 1 to 30 (0x01 to 0x1E) the command is considered a “subaddress command”. The terminal will either receive or transmit data words, and “direction” is specified by the command’s T/R bit. The number of data words transacted is specified in the 5-bit word count field, ranging from 1 to 32 words. Thirty-two data words is represented when the word count field equals 0x00. When the command’s 5-bit subaddress field equals 0 or 31 (0x1F) a “mode code” command is indicated; the low order five bits no longer specify a word count, instead they convey a mode code value. This data sheet refers HOLT INTEGRATED CIRCUITS 46 HI-6120, HI-6121 Mode Codes 9 through 15 with T/R bit = 1 Mode Codes 22 through 31 with T/R bit = 1 Mode Codes 22 through 31 with T/R bit = 0 Treatment of these reserved mode commands depends on their respective Illegalization Table entries. As described above for undefined mode commands, response depends on whether or not illegal command detection applies. Any mode commands not implemented in the HI-6120/21 terminal should be treated the same as reserved mode commands. For example, command MC0 (with T/R = 1) is probably unimplemented because the HI-6120 does not have provisions for accepting “dynamic bus control”. The important point is that “illegal command detection” should be universally applied (or not applied) when setting up a HI-6120/21 Remote Terminal application. Here are the two options: Not using Illegal command detection. The HI-6120/21 Illegalization Table is left in its default state (all locations equal to MR post-reset 0x0000). The terminal responds “in form” to all valid commands, whether legal or illegal. Using illegal command detection. The HI-6120/21 Illegalization Table is initialized by the host to implement “illegal command detection”. The host sets bits for all illegal commands. This generally includes the reserved and unimplemented mode commands, unimplemented subaddresses (or specific word counts, T/R bit states, and/or broadcast vs. non-broadcast status within subaddresses). Treatment for the undefined mode commands depends on UMCINV bit. The host defines terminal response for all individual commands by initializing the Descriptor Table, fully described later. At this point, a few comments about the Descriptor Table are appropriate. The command SA (subaddress) field has a range of 0 to 31 (0x1F). When SA is in the range 1 to 30 (0x1E), the command is a transmit or receive “subaddress command”. The number of data words transmitted or received is expressed in the low order 5 bits. When SA equals 0 or 31 (0x1F) the command is a mode command and the mode code value is expressed in the low order 5 bits. For each subaddress, separate table “descriptor blocks” for transmit and receive commands permit different data buffering to be applied. The host initializes the table so each transmit-subaddress and each receive-subaddress uses one of four methods for storing message data. During table initialization, memory is allocated in shared RAM for storing message data according to the application requirements. Each transmit-subaddress and receive-subaddress has one or more data pointers (depending on buffer method) addressing its reserved data buffer(s). Each mode command also has its own table “descriptor block”. Mode commands have either one data word or no associated data words. Descriptor words used as data pointers by “subaddress commands” are instead used for direct storage of transacted mode data words. Mode commands that transmit or receive mode data words have a dedicated storage address range in shared RAM, eliminating the need for descriptor table data pointers. Each mode command with mode data word has its own fixed address for data storage. This includes reserved mode codes with data word. Thus the HI-6120/21 can respond consistently for all mode commands; transmitted data values for “in form” responses (when “illegal command detection” is not used) can be predetermined, even for the reserved mode commands. 6.1. RT to RT Commands. The MIL-STD-1553 standard allows for data word transmission from a specified transmitting terminal to a different receiving terminal. When broadcast commands are allowed, data transmission can be addressed to the broadcast terminal address, RT31. If broadcast is allowed, the host should initialize the BCSTINV (broadcast invalid) bit in Configuration Register 1 to logic 0. All RT to RT commands are characterized by a pair of contiguous command words: Command Word 1 is a receive command addressed to the intended receiving terminal, then Command Word 2 is a transmit command addressed to a single transmitting terminal. Command Word 2 cannot be broadcast address RT31. The HI-6120 automatically detects and handles RT to RT commands, except when either command word contains a subaddress field equal to 0x0 or 0x1F. Either subaddress value indicates a mode code command; the device treats RT to RT commands with mode code as invalid. If either RT-RT command word is addressed to the HI-6120/21 terminal but contains subaddress 0x0 or 0x1F, the command is not recognized; there is no RT command response, and no status updating for the benefit of following “transmit status” or “transmit last command” mode commands. When either RT-RT command word (with subaddress field not equal to 0x0 or 0x1F) is addressed to the HI6120/21 terminal, but the other command word contains subaddress 0x0 or 0x1F, the RT-RT command is not recognized as valid. There is no RT command response, HOLT INTEGRATED CIRCUITS 47 HI-6120, HI-6121 and no status updating for the benefit of following “transmit status” or “transmit last command” mode commands. An RT-RT command pair where Command Word 1 is addressed to the HI-6120/21 terminal and Command Word 2 is addressed to a different terminal is considered an “RT-RT receive” command. When the message is transacted, the device sets the RTRT bit in the Receive Subaddress Message Information Word in the subaddress data buffer. An RT-RT command pair where Command Word 2 is solely addressed to the HI-6120/21 terminal (not RT31) is considered an “RT-RT transmit” command. The Message Information Word does not distinguish the RT to RT transmit message from an ordinary RT to BC transmit command. The device uses a 256-word “Illegalization Table” in shared RAM to distinguish between legal and illegal commands. After the (MR) master reset input is negated, HI-6120/21 performs internal self test including a shared RAM test which leaves all memory locations fully reset. Once self test is complete, the HI-6120/21 READY output goes high to indicate HI-6120/21 readiness for host initialization. At this point, all entries in the Illegalization Table read logic 0, so by default, illegal command detection is not applied. To apply illegal command detection, the host (or autoinitialization) writes the Illegalization Table to set bits for all illegal command combinations. This typically includes any unimplemented subaddresses and/or word counts, undefined mode commands, reserved mode commands and any mode commands not implemented in the terminal design. Host initialization of the table can be replaced by auto-initialization. Once STEX is set in Configuration Register 1, terminal execution begins. Each time a valid command is received, a 1-bit entry (indexed using command word data bits) is fetched from the Illegalization Table: If fetched Illegalization Table bit equals logic 0, the command is “legal”; the terminal responds “in form”, transmitting clear status and transacting the number of data words defined for the message type. Terminal status is updated. If fetched Illegalization Table bit equals logic 1, the command is “illegal”; the terminal responds with status word only, with Message Error bit set. No data words are transmitted. Terminal status is updated. When illegal command detection is not applied, all table entries should read logic 0; the terminal responds “in form” to all valid commands. The illegalization scheme allows any subset of command T/R bit, broadcast vs. non-broadcast status, subaddress and word count (or mode code number), for a total of 4,096 legal/illegal command combinations. Commands may be illegalized down to the word count level. For example, 10-word receive commands to a given subaddress may be legal, while 9-word receive commands to the same subaddress are illegal. Broadcast receive commands are illegalized separately from non-broadcast receive commands. Transmit and receive commands for the same subaddress are illegalized separately. For mode commands, any combination of mode code number, T/R bit and broadcast/non-broadcast status can be legal or illegal. The Illegalization Table is located in shared RAM within 7. COMMAND ILLEGALIZATION TABLE The following pages describe various structures residing in the RAM shared between the host and HI-6120 or HI-6121 command processing logic. The host initializes these structures to control the terminal’s response to received commands. The first structure described is the command Illegalization Table used for “illegal command detection”. Illegal command detection is an optional process. When illegal command detection is not used, the terminal “responds in form” to all valid commands: it sends Clear Status and transacts the number of data words defined in the received command. When illegal command detection is not used, the bus controller cannot tell whether the command is legal or illegal, from the terminal’s transmitted response. If illegal command detection is used, the terminal responds differently when an illegal command is detected. The terminal responds to illegal commands with “message error” status, transmitting only status word. Data word transmission is suppressed if the command type inherently includes transmitted data words. The terminal responds to each legal command with clear status and transacts the number of data words defined in the type of command received. For consistency, apply illegal command detection to all illegal and unimplemented commands, and to all reserved or undefined mode code commands, or “respond in form” to all of these commands (illegal command detection disabled) by leaving the Illegalization Table in the all-cleared default state after MR master reset HOLT INTEGRATED CIRCUITS 48 HI-6120, HI-6121 the fixed address range of 0x0100 to 0x01FF. See Figure 4. The table is comprised of 256 16-bit words. To cover the full range of 1 to 32 data words, each subaddress uses a pair of illegalization registers. The lower register (even memory address) covers word counts 0 to 15, using one bit per word count. As in command encoding, “0” denotes 32 data words. Bit 0 corresponds to 32 data words, bit 1 corresponds to 1 data word and bit 15 corresponds to 15 data words. The upper register (odd memory address) similarly covers word counts 16 to 31, using one bit per word count. Bit 0 corresponds to 16 data words, while bit 15 corresponds to 31 data words. When a command’s subaddress field equals 0 or 31 (0x1F), the command is a mode command. Table entries for mode commands use bits to represent mode code numbers, not word counts. The lower register (even memory address) covers mode codes 0 to 15, using one bit per mode code. Bit 0 corresponds to mode code 0, bit 15 corresponds to mode code 15. The upper register (odd memory address) similarly covers mode codes 16 to 31, using one bit per mode code. Bit 0 corresponds to mode code 16, bit 15 corresponds to mode code 31. There is no functional difference between SA0 mode commands and SA31 mode commands. Since either subaddress indicates a mode command, the subaddress 0 table words should match the subaddress 31 table words in each quadrant. Table entries from 0x0142 to 0x017D do not have to be programmed. These correspond to broadcast transmit subaddress commands (undefined by MIL-STD-1553B) and are always invalid. There is no terminal response. Addressing for the Illegalization Table is derived from the command word T/R bit, subaddress field, MSB of the Word Count (Mode Code) field and the command’s broadcast vs. non-broadcast status as shown below in Figure 4. Bit Fields Comprise Each Received Command Word Command Sync Figure 6 shows individual bit locations in the Illegalization Table for broadcast and non-broadcast variants of all mode commands defined by MIL-STD-1553B. Locations are also identifed for reserved mode codes and undefined mode code commands. The following examples illustrate how the Illegalization Table is initialized to distinguish between legal and illegal commands when “illegal command detection” is being used. Remember: If the terminal does not use illegal command detection, the table is left in its post-MR reset state, with all table locations reset to 0x0000. In this case, all command responses are “in form”. For “subaddress commands” (ordinary receive commands or transmit commands) individual table bits correspond to word counts specified in the received command word. If a bit is 0, the corresponding word count is legal. If a bit is 1, the corresponding word count is illegal. For example, transmit commands to subaddress 1 are controlled by the words at 0x01C2 and 0x01C3. In Figure 5, these words are located in the “RT Address Transmit” block. The word stored at 0x01C3 controls subaddress 1 transmit commands having word counts 16 to 31. The word stored at 0x01C2 controls subaddress 1 transmit commands having word counts 1 to 15 or 32. (Reminder: In MIL-STD-1553B, zero corresponds to 32 words.) Word at 0x01C3 (Tx Subaddr 1) 31 to 16 words Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Words 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Word at 0x01C2 (Tx Subaddr 1) 15 to 1 & 32 words Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Words 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 1 32 Terminal Address TA4:0 Word Count T/R Subaddress (Mode Code) Bit SA4:0 WC4:0 If the word stored at 0x01C3 = 0xFFFF and the word stored at 0x01C2 = 0xFF0F, then commands with 4, 5, 6, or 7 data words are the only legal transmit commands for subaddress 1 and all other word counts are illegal. Receive commands and broadcast receive commands for Subaddresses1 through 30 are encoded similarly. For “mode code commands” (characterized by command word subaddress field equal to 00000 or 11111 binary) individual table bits correspond to individual mode code values. Here “transmit” and “receive” simply indicate the state of the command word T/R bit. (For mode codes 0-15, the T/R bit does not indicate data direction since data is not transacted when fulfilling these commands). P “0” if TA4:0 = 11111 else “1” 00000001 T/R SA4 SA3 SA2 SA1 SA0 WC4 Table Address Figure 4. Deriving the Illegalization Table Address From the Received Command Word HOLT INTEGRATED CIRCUITS 49 HI-6120, HI-6121 0x01FF Tx Subaddress 31 Block (mode codes) Tx Subaddress 30 Block RT Address Tx Mode Codes 31 - 16 RT Address Tx Mode Codes 15 - 0 RT Addr Tx SA30 Word Counts 31 - 16 RT Addr Tx SA30 Word Counts 15 - 0 * 0x01FF 0x01FE 0x01FD 0x01FC RT Address Transmit Quadrant 32 subaddress blocks of 2 words each * Word Count = 0 denotes 32 words RT Address Tx Mode Codes 31 - 16 RT Address Tx Mode Codes 15 - 0 RT Address Rx Mode Codes 31 - 16 RT Address Rx Mode Codes 15 - 0 RT Addr Rx SA30 Word Counts 31 - 16 RT Addr Rx SA30 Word Counts 15 - 0 * Tx Subaddress 1 Block 0x01C1 0x01C0 0x01BF 0x01BE 0x01BD 0x01BC 0x01C0 0x01BF Tx Subaddress 0 Block (mode codes) Rx Subaddress 31 Block (mode codes) Rx Subaddress 30 Block RT Address Receive Quadrant 32 subaddress blocks of 2 words each * Word Count = 0 denotes 32 words RT Address Rx Mode Codes 31 - 16 RT Address Rx Mode Codes 15 - 0 Rx Subaddress 1 Block 0x0181 0x0180 0x017F 0x017E 0x017D 0x017C 0x0180 0x017F Rx Subaddress 0 Block (mode codes) Tx Subaddress 31 Block (mode codes) Tx Subaddress 30 Block Command Sync Broadcast Tx Mode Codes 31 - 16 Broadcast Tx Mode Codes 15 - 0 Broadcast Tx SA30 Word Counts 31 - 16 Broadcast Tx SA30 Word Counts 15 - 0 * Broadcast Transmit Quadrant 32 subaddress blocks of 2 words each SA1 to SA30 are illegal broadcast transmit! Tx Subaddress 1 Block * Word Count = 0 denotes 32 words Broadcast Tx Mode Codes 31 - 16 Broadcast Tx Mode Codes 15 - 0 Broadcast Rx Mode Codes 31 - 16 Broadcast Rx Mode Codes 15 - 0 Broadcast Rx SA30 Word Counts 31 - 16 Broadcast Rx SA30 Word Counts 15 - 0 * 0x0141 0x0140 0x013F 0x013E 0x013D 0x013C 0x0140 0x013F Tx Subaddress 0 Block (mode codes) Rx Subaddress 31 Block (mode codes) Rx Subaddress 30 Block Broadcast Receive Quadrant 32 subaddress blocks of 2 words each * Word Count = 0 denotes 32 words Broadcast Rx Mode Codes 31 - 16 Broadcast Rx Mode Codes 15 - 0 Rx Subaddress 1 Block 0x0101 0x0100 0x0100 Rx Subaddress 0 Block (mode codes) Illegalization Table Comprised of 32 2-word Blocks per Quadrant Example Subaddress Blocks from Each Table Quadrant Figure 5. Fixed Address Mapping for Illegalization Table Figure 6 summarizes the 16 Illegalization Table locations for mode commands. These locations are scattered throughHOLT INTEGRATED CIRCUITS 50 HI-6120, HI-6121 out the overall Illegalization Table shown in Figure 5. Remember: the host must initialize all table locations corresponding to both subaddress 0 and subaddress 31 (11111 binary). Consider an example in which all reserved and all undefined mode commands are illegal. If all defined transmit mode commands are legal except MC0 (”dynamic bus control”) the eight table entries for transmit mode commands would be: 0x01FF and 0x01C1 = 1111 1111 1111 0010 = 0xFFF2 0x01FE and 0x01C0 = 1111 1110 0000 0001 = 0xFE01 0x017F and 0x0141 = 1111 1111 1111 1111 = 0xFFFF 0x017E and 0x0140 = 1111 1110 0000 0101 = 0xFE05 The receive mode command words are encoded similarly. Continuing the same example where all reserved Bit No. 0x01FF and 0x01C1 0x01FE and 0x01C0 0x01BF and 0x0181 0x01BE and 0x0180 0x017F and 0x0141 0x017E and 0x0140 0x013F and 0x0101 0x013E and 0x0100 Tx MC31 - MC16 Tx MC15 - MC0 Rx MC31 - MC16 Rx MC15 - MC0 Br.Tx MC31 - MC16 Br.Tx MC15 - MC0 Br.Rx MC31 - MC16 Br.Rx MC15 - MC0 Transmit Mode Commands With Data Transmit Mode Commands Without Data Receive Mode Commands With Data Receive Mode Commands Without Data Broadcast Transmit Mode Commands With Data Broadcast Transmit Mode Commands Without Data Broadcast Receive Mode Commands With Data Broadcast Receive Mode Commands Without Data and all undefined mode commands are illegal: If all defined receive mode commands are legal, the eight table entries for receive mode commands would be: 0x01BF and 0x0181 = 1111 1111 1100 1101 = 0xFFCD 0x01BE and 0x0180 = 1111 1111 1111 1111 = 0xFFFF 0x013F and 0x0101 = 1111 1111 1100 1101 = 0xFFCD 0x013E and 0x0100 = 1111 1111 1111 1111 = 0xFFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MC # Status MC # Status MC # Status MC # Status MC # Status MC # Status MC # Status MC # Status 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RRRRRRRRRRUUDDUD 15 14 13 12 11 10 9 RRRRRRR 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RRRRRRRRRRDDUUDU 15 14 13 12 11 10 9 UUUUUUU 8 U 7 U 6 U 5 U 4 U 3 U 2 U 1 U 0 U 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R R R R R R R R R R U U NB NB U NB 15 14 13 12 11 10 9 RRRRRRR 8 D 7 D 6 D 5 D 4 D 3210 D NB D NB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 RRRRRRRRRRDDUUDU 15 14 13 12 11 10 9 UUUUUUU 8 U 7 U 6 U 5 U 4 U 3 U 2 U 1 U 0 U RAM Address LEGEND D = Defined Mode Command U = Undefined Mode Command R = Reserved Mode Code NB = Defined Code, But Broadcast Not Allowed Figure 6. Summary of Illegalization Table Addresses for Mode Code Commands HOLT INTEGRATED CIRCUITS 51 HI-6120, HI-6121 8. TEMPORARY RECEIVE DATA BUFFER The 32-word temporary receive data buffer resides in shared RAM in address space 0x0020 to 0x003F. The device optionally uses this buffer for temporary storage of receive data words until successful message completion. To enable the buffer, the host asserts the TRXDC bit in Configuration Register 2. When enabled, the terminal stores received data words in the 32-word buffer during message processing. Upon error-free message completion, all buffered words are written in a burst to the data buffer memory assigned to the specific subaddress in the Descriptor Table. When the TRXDB bit in Configuration Register 2 is negated, the temporary receive data buffer is disabled. At 20us intervals, the terminal writes received data words to assigned subaddress data buffer memory as each word is received. If message error occurs during data reception, data integrity is lost; valid data from the prior receive message may be partially overwritten by data from a message ending in error. MIL-STD-1553 states that all received data from messages ending in error should be disregarded. In a typical application, the temporary buffer is not directly accessed by the host, although there is no restriction preventing host data access. The host should never write data into the temporary buffer space. The Interrupt Identification Word (IIW) identifies the occurring interrupt type using a word format identical to the Pending Interrupt Register. Upon update, all bits except the occurring interrupt type bit(s) are reset. Table 6. Interrupt Information Word Bits Summary IIW - Interrupt Information Word Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ILCMD SPIFAIL LBFA LBFB TTINT1 TTINT0 RTAPF EECKF RAMIF MERR Interrupt IXEQZ IWA IBR Origin Message Message Message --------Message ----Message Hardware Hardware Hardware Hardware Hardware Hardware Hardware Hardware IAW contains 0x0000 IAW contains the Command Word Descriptor Table Address IAW - Interrupt Address Word 9. INTERRUPT LOG BUFFER Two interrupt output pins notify the host upon occurrence of pre-determined interrupt-causing events. The interrupt types are listed below. Each interrupt type only occurs when the corresponding interrupt type bit is asserted in the Interrupt Enable Register. To manage host interrupts, the device architecture uses an Interrupt Log buffer, three control registers, two interrupt output pins and two interrupt acknowledge input pins. The data sheet section entitled “Interrupt Management” provides additional details. Shown in Figure 7, the Interrupt Log Buffer is a 32-word ring buffer located in shared RAM, at address range 0x0040 to 0x005F. To help the host process interrupts, the device interrupt manager maintains information from the 16 most recent interrupts in this buffer. The buffer contains two information words for each occurring interrupt: the Interrupt Identification Word and Interrupt Address Word. More than one bit may be asserted in an Interrupt Identification Word. For example, IBR (interrupt broadcast received) and MERR (interrupt message error) can occur for the same message. One assertion of the INTMES output pin alerts the host when concurrent message interrupts occur. The Interrupt Address Word (IAW) identifies the originating command for message-based interrupts. When interrupts originate from message processing, the Interrupt Address Word (IAW) identifies the interrupt source using the 16-bit address of the command’s Control Word in the Descriptor Table. Hardware interrupts are not linked with command processing. These interrupts write an Interrupt Address Word value of 0x0000. HOLT INTEGRATED CIRCUITS 52 HI-6120, HI-6121 After MR reset or SRST software reset, the device automatically initializes bits 7:0 in the Interrupt Log Address register to the buffer’s base address, 0x0040. The bit 7:0 value read will always be even, ranging from 0x0040 to 0x005E. Once terminal operation begins, the current value of the Interrupt Log Address indicates where the Interrupt Information Word (IIW) for the next occurring interrupt will be stored. On the first interrupt occurring after reset, the device writes the IIW and IAW to offset locations 00000 and 00001 respectively. The device increments the ring buffer pointer after each word is stored, storing interrupt information sequentially in the ring buffer. Information words for the sixteenth interrupt are stored in offset locations 0x1E and 0x1F (buffer addresses 0x005E and 0x005F) and the Interrupt Log Address “rolls over” to again point to offset location 0 (buffer address 0x0040) where the Interrupt Information Word for the seventeenth interrupt will be stored. Bits 15:8 in the Interrupt Log Address register maintain a count of interrupt events since the register was last read. The interrupt count stops at 255 decimal. Counts greater than 16 indicate buffer overrun, but the extended count capacity is provided as a diagnostic aid. HOLT INTEGRATED CIRCUITS 53 HI-6120, HI-6121 0x005F 0x005E 0x005D 0x005C 0x005B 0x005A 0x0059 0x0058 0x0057 0x0056 0x0055 0x0054 0x0053 0x0052 0x0051 0x0050 0x004F 0x004E 0x004D 0x004C 0x004B 0x004A 0x0049 0x0048 0x0047 0x0046 0x0045 0x0044 0x0043 0x0042 0x0041 0x0040 INTERRUPT 16 INTERRUPT 16 INTERRUPT 15 INTERRUPT 15 INTERRUPT 14 INTERRUPT 14 INTERRUPT 13 INTERRUPT 13 INTERRUPT 12 INTERRUPT 12 INTERRUPT 11 INTERRUPT 11 INTERRUPT 10 INTERRUPT 10 INTERRUPT 9 INTERRUPT 9 INTERRUPT 8 INTERRUPT 8 INTERRUPT 7 INTERRUPT 7 INTERRUPT 6 INTERRUPT 6 INTERRUPT 5 INTERRUPT 5 INTERRUPT 4 INTERRUPT 4 INTERRUPT 3 INTERRUPT 3 INTERRUPT 2 INTERRUPT 2 INTERRUPT 1 INTERRUPT 1 Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word Interrupt Address Word Interrupt Information Word The Interrupt Log Address Register points to this address after Interrupt 15 event occurs. Upon Interrupt 16 completion, device logic reinitializes the log address pointer to 0x0040 before Interrupt 17 is processed. EXAMPLE: 2-WORD LOG BUFFER ENTRIES FOR VARIOUS INTERRUPT TYPES... Example 1: MERR bit is set in Interrupt Enable Register. An error occurs while transacting a receive command for subaddress 30: Address Word = 0x0278 Descriptor Address for Rx Subaddress 30.* Information Word = 0x0400 MERR (interrupt message error) bit = 1. Example 2: IWA bit is set in Interrupt Enable Register. The IWA bit is set in Transmit Subaddress 30 Control Word to generate an interrupt upon each message occurrence. A transmit command is received for subaddress 30: Address Word = 0x02F8 Descriptor Address for Tx Subaddress 30.* Information Word = 0x4000 IWA (interrupt when accessed) bit = 1. Example 3: ILCMD bit is set in Interrupt Enable Register. “Illegal Command Detection” is being applied and all Illegalization Table bits for undefined mode codes are set. An undefined Mode Code 0 with T/R bit = 0 is received: Address Word = 0x0300 Descriptor Address for Rx Mode Code 0.* Information Word = 0x0100 ILCMD (interrupt illegal command) bit = 1. Example 4: TTINT0 bit is set in Interrupt Enable Register. The Time-Tag counter rolls over from full count 0xFFFF to 0x0000: Address Word = 0x0000 (all hardware interrupts reset the IAW) Information Word = 0x0010 TTINT0 (Time-Tag interrupt 0) bit = 1 * Figure 8 shows where these addresses occur in the Descriptor Table. Interrupt Log Address Register is initialized by device logic to point to this address after hardware reset (MR) or software reset Figure 7. Fixed Address Mapping for Interrupt Log Buffer HOLT INTEGRATED CIRCUITS 54 HI-6120, HI-6121 10. DESCRIPTOR TABLE The Descriptor Table, resides in shared RAM, in address range 0x0200 to 0x03FF. This table is initialized by the host (or auto-initialization) to define how the terminal processes valid commands. Descriptor Table settings for each command specify where message data is stored, how data is stored, whether host interrupts are generated, and other aspects essential to command processing. Shown in Figure 8, the table consists of 128 consecutive “descriptor blocks”, each comprised of four 16-bit words. The table is organized into four quadrants. The Receive Subaddress and Transmit Subaddress quadrants define response for commands having a subaddress field ranging from 1 to 30 (0x1E). These are simple N-data word receive or transmit commands, where N can range from 1 to 32 words. When the command T/R bit equals 0, the receive command quadrant applies. When the T/R bit equals 1, the transmit command quadrant applies. Both subaddress quadrants are padded at top and bottom with unused Descriptor Blocks for subaddresses 0 and 31 (0x1F). The word space reserved for SA0 and SA31 aligns the table addressing, but values stored in these eight locations is not used. Command subaddresses 0 and 31 indicate mode commands. The response for commands containing either SA value is defined in the two mode command table quadrants. The Receive Mode Command quadrant applies when the command word T/R bit equals 0, while the Transmit Mode Command quadrants applies when T/R equals 1. The term “Transmit Mode Command” is a misnomer. All defined mode commands with mode code less than 0x0F haveT/R bit equal to 1, yet none of these mode commands transmits a data word. They transmit only the terminal status word, just like receive commands. Within the Receive and Transmit Mode Command quadrants, block addressing is based on the low order 5 bits in the command word, containing the mode code value. This is fundamentally different from the Subaddress quadrants in which block addressing is based on the 5-bit subaddress field. Figure 9 shows how to derive Control Word address from the received Command Word. The Control Word address for the last valid command can also be found in the Current Control Word Address register. All 128 4-word Descriptor Blocks start with a Control Word. There are four Control Word variants (described later), based on command type: receive vs. transmit and mode vs. non-mode commands. All descriptor Control Words are initialized by the host (or auto-initialization) to define basic command response. Each Control Word specifies the data buffer method and host interrupt for a specific subaddress or mode command. Each subaddress has both a Receive Subaddress block and a Transmit Subaddress block. Receive and transmit commands to the same subaddress can be programmed to respond differently. The function of the three remaining descriptor words (in each 4-word block) depends on the data buffer method specified in the Control Word. There are 4 data buffer options available: Indexed (or Single Buffer) Method where a predetermined number of messages is transacted using a single data buffer in shared RAM. Several host interrupt options are offered, including an interrupt generated when all N messages are successfully completed. Double (or Ping-Pong) Buffer Method where successive messages alternate between two data buffers in shared RAM. Several host interrupt options are offered. Circular Buffer Mode 1 where buffer boundaries determine when the bulk transfer is complete and message information and time-tag words are stored with message data in a common buffer. Several host interrupt options are offered, including an interrupt generated when the allocated data buffer is full. Circular Buffer Mode 2 where the number of messages transacted defines bulk transfer progress, and message data words are stored contiguously in one buffer while message information and time-tag words are stored in a separate buffer. Several host interrupt options are offered, including an interrupt generated when all N messages are successfully completed. The 4-word Descriptor Table entry for each command (its descriptor block) begins with a Control Word. There are four types of descriptor Control Word: • • • • Receive Subaddress Control Word Transmit Subaddress Control Word Receive Mode Command Control Word Transmit Mode Command Control Word The descriptor Control Word is initialized by the host to select data buffer method and interrupt options. After a command is processed by the HI-6120/21 terminal, the device updates the command’s descriptor Control Word. Update will differ based on the chosen data buffer method. Reading the descriptor table can differ from other RAM accesses. For HI-6120, see Section 15.1.1. For HI-6121, see Sections 15.2.5 and 15.2.7. HOLT INTEGRATED CIRCUITS 55 HI-6120, HI-6121 32 4-Word Blocks per Quadrant 0x03FF Mode Code 31 Block Mode Code 30 Block Descriptor Word 4 for Tx MC30 Descriptor Word 3 for Tx MC30 Descriptor Word 2 for Tx MC30 Control Word for Tx MC30 0x03FB 0x03FA 0x03F9 0x03F8 Transmit Mode Code Quadrant (Mode Codes with T/R bit = 1) 32 Descriptor Blocks of 4 words each Mode Code 1 Block 0x0380 0x037F Mode Code 0 Block Descriptor Word 4 for Rx MC30 Mode Code 31 Block Mode Code 30 Block Descriptor Word 3 for Rx MC30 Descriptor Word 2 for Rx MC30 Control Word for Rx MC30 0x037B 0x037A 0x0379 0x0378 Receive Mode Code Quadrant (Mode Codes with T/R bit = 0) 32 Descriptor Blocks of 4 words each Mode Code 1 Block Example 4-Word Descriptor Blocks from Each Table Quadrant 0x0300 0x02FF Mode Code 0 Block Subaddress 31 Block Subaddress 30 Block See Note. Descriptor Word 4 for Tx SA30 Descriptor Word 3 for Tx SA30 Descriptor Word 2 for Tx SA30 Control Word for Tx SA30 0x02FB 0x02FA 0x02F9 0x02F8 Transmit Subaddress Quadrant 32 Descriptor Blocks of 4 words each Subaddress 1 Block 0x0280 0x027F Subaddress 0 Block Subaddress 31 Block Subaddress 30 Block See Note. See Note. Descriptor Word 4 for Rx SA30 Descriptor Word 3 for Rx SA30 Descriptor Word 2 for Rx SA30 Control Word for Rx SA30 0x027B 0x027A 0x0279 0x0278 Receive Subaddress Quadrant 32 Descriptor Blocks of 4 words each Subaddress 1 Block 0x0200 Subaddress 0 Block See Note. NOTE: SA0 and SA31 indicate mode codes, so are not valid Receive or Transmit Subaddresses. Figure 8. Address Mapping for Descriptor Table (assumes table base address = 0x0200) HOLT INTEGRATED CIRCUITS 56 HI-6120, HI-6121 Command Sync RT Addr TA4:0 T/R Subaddress Word Count Bit SA4:0 WC4:0 Command Sync RT Addr TA4:0 T/R Subaddress Mode Code Bit SA4:0 MC4:0 P Descriptor Address Format Depends On Command Word’s Subaddress P 0x0 0x2 0x0 0x3 00000010 Descriptor Table Address for Subaddress Commands SA4:0 equals 00001 to 11110 T/R SA4 SA3 SA2 SA1 SA0 00 00000011 Descriptor Table Address for Mode Code Commands SA4:0 equals 00000 or 11111 T/R MC4 MC3 MC2 MC1 MC0 00 Figure 9. Deriving a Descriptor Table Control Word Address From Command Word (assumes table base address = 0x0200) 10.1. Receive Subaddress Control Word Receive Subaddress Control Words apply when a valid command word T/R bit equals zero (receive) and the subaddress field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command response and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when Configuration Register 1 STEX bit equals 1. The host can write bits 0-2 and 4-7 only when STEX equals zero; bits 3 and 12-15 can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any read cycle to the Control Word address, the DBAC bit is reset. H D D1 EQ IW Z A IB R U BA SY DC PB BC A PP ST O N C IR 2Z C IR N3 C 2ZN IR 2 2 C ZN IR 1 ST 2ZN O0 PP PP E CN IR 2 C EN IR 1E N Bit maintained by host Bit maintained by device Bit set by device, reset by host read cycle IX M H H H H D1 D D KB D D 8 H 7 H 6 H 5 H 4 H 3 H 2 H 1 H 0 LSB MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is unchanged unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset Function Interrupt When Index Equals Zero. If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables generation of an interrupt for (a) subaddresses using indexed buffer mode when the INDX value decrements from 1 to 0, or (b) subaddresses using a circular buffer mode when the pre-determined number of messages has been transacted. If enabled, upon completion of command processing that results in index = 0, an IXEQZ interrupt is entered in the Pending Interrupt Register, output pin INTMES is asserted, and the interrupt is registered in the Interrupt Log. 15 IXEQZ 0 HOLT INTEGRATED CIRCUITS 57 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Interrupt When Accessed. 14 IWA 0 If the Interrupt Enable Register IWA bit is high, assertion of this bit enables interrupt generation when the subaddress receives any valid receive command. If enabled, upon completion of command processing, an IWA interrupt is entered in the Pending Interrupt Register, output pin INTMES is asserted, and the interrupt is registered in the Interrupt Log. Interrupt Broadcast Received. If the Interrupt Enable Register IBR bit is high, assertion of this bit enables interrupt generation when the subaddress receives a valid broadcast command. If enabled, upon completion of message processing an IBR interrupt is entered in the Pending Interrupt Register, output pin INTMES is asserted, and the interrupt is registered in the Interrupt Log. This bit has no function if the BCSTINV bit is high in Configuration Register 1. In this case, commands to RT address 31 are not recognized as valid by the device. Make Busy. The host asserts the MKBUSY bit to respond with Busy status for commands to this receive subaddress. This bit is an alternative to globally applying Busy status for all valid commands, enabled from the 1553 Status Bits Register. See that register description for additional information. When Busy is asserted, received data words are not stored and the DPB bit does not toggle after message completion. Descriptor Block Accessed. 11 DBAC SR = 0 13 IBR 0 12 MKBUSY 0 0 Internal device logic asserts the DBAC bit upon completion of message processing. The host may poll this bit to detect subaddress activity, instead of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST software reset or a read cycle to this memory address. Data Pointer B. This status bit is maintained by the device and only applies in ping-pong buffer mode. This bit indicates the buffer to be used for the next occurring receive command to this subaddress. When the DPB bit is logic 0, the next message will use Data Pointer A; when DPB is logic 1, the next message uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each error-free message completion. The DPB bit is not altered after messages ending in error, after illegal commands or after messages when the terminal responds with Busy status. This bit is reset to logic 0 by MR master reset or SRST software reset; therefore the first message received after either reset will use Buffer A. This bit is “don’t care” for indexed single-buffer mode or either circular buffer mode. Broadcast Command. Device logic sets this bit when a valid broadcast receive command is received at this subaddress. If IBR bit 13 and Interrupt Enable Register IBR bit are both set, the output pin INTMES is asserted. This bit has no function if the BCSTINV bit is asserted in the Configuration Register 1; in this case commands to RT address 31 are not recognized as valid by the device. This bit is reset to logic 0 by MR master reset or SRST software reset. 10 DPB SR = 0 0 9 BCAST SR = 0 0 HOLT INTEGRATED CIRCUITS 58 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Ping-Pong Enable Acknowledge. This bit is controlled by the device and cannot be written by the host. It only applies if PPEN bit 2 was initialized to logic one by the host after reset, enabling ping-pong buffer mode for this subaddress. Device logic asserts this bit when it recognizes ping-pong is active for this subaddress. Before off-loading the receive data buffer for this subaddress, the host can ask the device to temporarily disable ping-pong by asserting STOPP bit 3. The device acknowledges ping-pong is disabled by negating PPON. The host can safely off-load the buffer without data collision while PPON is negated. After buffer servicing, the host asks the device to re-enable ping-pong by negating STOPP bit 3. The device acknowledges ping-pong is re-enabled by asserting PPON. If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. Each new message overwrites existing data in the buffer specified by DPB bit 10, and the DPB bit does not toggle after command completion. Circular Mode 2 Zero Number. 7-4 CIR2ZN 0 Used only in circular buffer mode 2, this 4-bit field is initialized with the number of trailing zeros in the initialized MIBA address. This is explained in Section 11.6, which fully describes circular buffer mode 2. Stop Ping-Pong Request. 3 STOPP 0 The host asserts this bit to suspend ping-pong buffering for this subaddress. The host resets this bit to ask the device to re-enable ping-pong. The device confirms recognition of ping-pong enable or disable status by writing PPON bit 8. Refer to later section fully describing ping-pong mode. Ping-Pong, Circular Buffer Mode 2 or Circular Buffer Mode 1 Enable. The PPEN, CIR2EN and CIR1EN bits are initialized by the host to select buffer mode. The table below summarizes how buffer mode selection is encoded. In the case of ping-pong, the host initializes the PPEN bit to logic one after reset to enable ping-pong buffering for this subaddress. The host asserts STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the STOPP bit asks the device to re-enable ping-pong. The device confirms pingpong enable or disable state changes by writing the PPON bit. PPEN 1 0 0 0 CIR2EN Don’t Care 1 0 0 CIR1EN Don’t Care Don’t Care 1 0 Buffer Mode Ping-Pong Circular Mode 2 Circular Mode 1 Indexed Single Buffer 8 PPON 0 2 1 0 PPEN CIR2EN CIR1EN 0 0 0 HOLT INTEGRATED CIRCUITS 59 HI-6120, HI-6121 10.2. Transmit Subaddress Control Word Transmit Subaddress Control Words apply when a valid command word T/R bit equals one (transmit) and the subaddress field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command response and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when Configuration Register 1 STEX bit equals 1. The host can write bits 0-2 and 4-7 only when STEX equals zero; bits 3,12 and 14-15 can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any host read cycle to the Control Word address, the DBAC bit is reset. H D D1 X KB D US BA Y DC PB BC A PP ST O CN IR 2 C ZN IR 3 C 2ZN IR 2 2 C ZN IR 1 ST 2ZN O0 PP PP E CN IR 2 C EN IR 1E N IX EQ IW Z A Bit maintained by host Bit maintained by device Bit set by device, reset by host read cycle Bit is not used, may be logic 0 or 1 H H X M H D1 D D D 8 H 7 H 6 H 5 H 4 H 3 H 2 H 1 H 0 LSB MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is unchanged unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset Function Interrupt When Index Equals Zero. If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables generation of an interrupt for (a) subaddresses using indexed buffer mode when the INDX value decrements from 1 to 0, or (b) subaddresses using a circular buffer mode when the pre-determined number of messages has been transacted. If enabled, upon completion of command processing that results in index = 0, an IXEQZ interrupt is entered in the Pending Interrupt Register, output pin INTMES is asserted, and the interrupt is registered in the Interrupt Log. Interrupt When Accessed. 14 IWA 0 If the Interrupt Enable Register IWA bit is high, assertion of this bit enables interrupt generation when the subaddress receives any valid transmit command. If enabled, upon completion of command processing, an IWA interrupt is entered in the Pending Interrupt Register, output pin INTMES is asserted, and the interrupt is registered in the Interrupt Log. Not Used Make Busy. The host asserts the MKBUSY bit to respond with Busy status for commands to this transmit subaddress. This bit is an alternative to globally applying Busy status for all valid commands, enabled from the 1553 Status Bits Register. See that register description for additional information. When Busy is asserted, data words are not transmitted and the DPB bit does not toggle after message completion. 15 IXEQZ 0 13 ----- 0 12 MKBUSY 0 HOLT INTEGRATED CIRCUITS 60 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Descriptor Block Accessed. 11 DBAC SR = 0 0 Internal device logic asserts the DBAC bit upon completion of message processing. The host may poll this bit to detect subaddress activity, instead of using host interrupts. This bit is reset to logic zero by MR master reset, SRST software reset or a read cycle to this memory address. Data Pointer B. This status bit is maintained by the device and only applies in ping-pong buffer mode. This bit indicates the buffer to be used for the next occurring transmit command to this subaddress. When the DPB bit is logic 0, the next message will use Data Pointer A; when DPB is logic 1, the next message uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each error-free message completion. The DPB bit is not altered after messages ending in error, after illegal commands or after messages when the terminal responds with Busy status. This bit is reset to logic 0 by MR master reset or SRST software reset; therefore the first message received after either reset will use Buffer A. This bit is “don’t care” for indexed single-buffer mode or either circular buffer mode. Broadcast Received. The device sets this bit when a broadcast-transmit command is received for this subaddress. Because non-mode broadcast-transmit commands are always illegal, the assertion of this bit in the Control Word by the device indicates an illegal command was received. Terminal response varies, depending on whether or not illegal command detection applies (any bits set in Illegalization Table). This bit has no function if the BCSTINV bit is asserted in Configuration Register 1; in this case commands to RT address 31 are not recognized as valid by the device. This bit is reset to logic 0 by MR master reset or SRST software reset. Ping-Pong Enable Acknowledge. This bit is controlled by the device and should not be written by the host. It only applies if PPEN bit 2 was initialized to logic one by the host after reset, enabling ping-pong buffer mode for this subaddress. The RT asserts this bit when it recognizes ping-pong is active for this subaddress. Before loading the transmit data buffer for this subaddress, the host can ask the RT to temporarily disable ping-pong by asserting STOPP bit 3. The RT acknowledges ping-pong is disabled by negating PPON. The host can safely load the buffer without data collision while PPON is negated. After buffer servicing, the host asks the RT to re-enable ping-pong by negating STOPP bit 3. The RT acknowledges ping-pong is re-enabled by asserting PPON. If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. Each new message transmits data from the same buffer, specified by DPB bit 10, and the DPB bit does not toggle after command completion. Circular Mode 2 Zero Number. Used only in circular buffer mode 2, this 4-bit field is initialized with the number of trailing zeros in the initialized MIBA address. This is explained in Section 11.6, which fully describes circular buffer mode 2. 10 DPB SR = 0 0 9 BCAST SR = 0 0 8 PPON 0 7-4 CIR2ZN 0 HOLT INTEGRATED CIRCUITS 61 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Stop Ping-Pong Request. 3 STOPP 0 The host asserts this bit to suspend ping-pong buffering for this subaddress. The host resets this bit to ask the RT to re-enable ping-pong. The RT confirms recognition of ping-pong enable or disable status by writing PPON bit 8. Refer to later section describing ping-pong mode for more information. Ping-Pong, Circular Buffer Mode 2 or Circular Buffer Mode 1 Enable. The PPEN, CIR2EN and CIR1EN bits are initialized by the host to select buffer mode. The table below summarizes how buffer mode selection is encoded. 2 1 0 PPEN CIR2EN CIR1EN 0 0 0 In the case of ping-pong, the host initializes the PPEN bit to logic one after reset to enable ping-pong buffering for this subaddress. The host asserts STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the STOPP bit asks the device to re-enable ping-pong. The device confirms pingpong enable or disable state changes by writing the PPON bit. PPEN 1 0 0 0 CIR2EN Don’t Care 1 0 0 CIR1EN Don’t Care Don’t Care 1 0 Buffer Mode Ping-Pong Circular Mode 2 Circular Mode 1 Indexed Single Buffer 10.3. Data Buffer Options for Mode Code Commands Data buffer options for mode code commands differ from options offered for subaddress commands. Mode commands cannot use either circular data buffer method, but may use double (ping-pong) buffering or single (indexed) buffering. Single message Index mode (INDX = 0) is suitable in many applications (see Section 11.4.1). An alternative called Simplified Mode Command Processing (SMCP) may be globally applied for all mode code commands (see Section 12.5). To use single (indexed) buffer or double (ping-pong) buffer for mode commands, the SMCP bit in Configuration Register 1 is logic 0. The Control Word PPEN bit for each mode command determines whether ping-pong or indexed buffering is used. To use Simplified Mode Command Processing, the SMCP bit in Configuration Register 1 is set to logic 1. The Control Word PPEN bit for mode commands is “don’t care” (no longer specifies index or ping-pong buffer mode) because Simplified Mode Command Processing stores mode command data and message information words directly within each mode command’s redefined Descriptor Table block. When SMCP is enabled, mode code command descriptor blocks (in the Descriptor Table) do not contain data pointers to reserved buffers elsewhere in the shared RAM. Instead, each 4-word descriptor block itself contains the message information word, the time-tag word and the data word transacted for each mode command (for mode codes 16-31 decimal). When Simplified Mode Command Processing is used, the range of active bits is reduced in each receive or transmit mode command Control Word. Interrupt control and response is not affected by the SMCP option. Simplified Mode Command Processing is fully presented in the later data sheet section entitled “Mode Code Commands.” HOLT INTEGRATED CIRCUITS 62 HI-6120, HI-6121 10.4. Receive Mode Control Word Receive Mode Control Words apply when the command word T/R bit equals zero (receive) and the subaddress field has a value of 0 or 31 (0x1F). The descriptor Control Word defines terminal command response and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when Configuration Register 1 STEX bit equals 1. The host can write bit 2 only when STEX equals zero; bits 3 and 12-15 can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any read cycle to the Control Word address, the DBAC bit is reset. When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code Processing), the receive mode Control Word looks like this: H D LSB D1 X KB D US BA Y DC PB BC A PP ST O N ST O PP PP EN IX EQ IW Z A IB R Bit maintained by host Bit maintained by device Bit set by device, reset by host read cycle Bit is not used, may be logic 0 or 1 H H M H H D1 D D D 8 X 7 X 6 X 5 X 4 H 3 H 2 X 1 X 0 MSB 15 14 13 12 11 10 9 When SMCP applies, the number of active mode Control Word bits is reduced: H D LSB D1 X BA SY C A PP ST O N IX EQ IW Z A IB R KB U Bit maintained by host Bit maintained by device Bit set by device, reset by host read cycle Bit is not used, may be logic 0 or 1 M H H H H D1 X BC D D D 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is unchanged unless specifically indicated by an “SR” value. Bit No. Mnemonic R/W Reset Function Interrupt When Index Equals Zero. If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables generation of an interrupt for mode code commands using indexed buffer mode when the INDX value decrements from 1 to 0. Upon completion of command processing that results in INDX = 0, when IXEQZ interrupts are enabled, an IXEQZ interrupt is entered in the Pending Interrupt Register, the INTMES output pin is asserted, and the interrupt is registered in the Interrupt Log. Interrupt When Accessed. 14 IWA 0 If the Interrupt Enable Register IWA bit is high, assertion of this bit enables interrupt generation at each instance of a valid mode code command. Upon completion of command processing, when IWA interrupts are enabled, an IWA interrupt is entered in the Pending Interrupt Register, the INTMES output pin is asserted, and the interrupt is registered in the Interrupt Log. 15 IXEQZ 0 HOLT INTEGRATED CIRCUITS 63 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Interrupt Broadcast Received. If the Interrupt Enable Register IBR bit is high, assertion of this bit enables interrupt generation at each instance of a valid broadcast receive mode code command. Upon completion of command processing, when IBR interrupts are enabled, an IBR interrupt is entered in the Pending Interrupt Register, the INTMES output pin is asserted, and the interrupt is registered in the Interrupt Log. This bit has no function if the BCSTINV bit is high in Configuration Register 1. In this case, commands to RT address 31 are not recognized as valid by the device. Make Busy. The host asserts the MKBUSY bit to respond with Busy status for commands to this mode code. This bit is an alternative to globally applying Busy status for all valid commands, enabled from the 1553 Status Bits Register. See that register description for additional information. When Busy is asserted, mode data words received with MC16-MC31 are not stored and the DPB bit does not toggle after message completion. Descriptor Block Accessed. 11 DBAC SR = 0 13 IBR 0 12 MKBUSY 0 0 Internal device logic asserts the DBAC bit upon completion of message processing. The host may poll this bit to detect mode command activity, instead of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST software reset or a read cycle to this memory address. Data Pointer B. This status bit is maintained by the device and only applies for mode commands using ping-pong buffer mode. This bit indicates the buffer to be used for the next occurring mode command. When the DPB bit is logic 0, the next message will use Data Pointer A; when DPB is logic 1, the next message uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each error-free message completion. The DPB bit is not altered after messages ending in error, after illegal commands, or after messages when the terminal responds with Busy status. This bit is reset to logic 0 by MR master reset or SRST software reset; therefore the first message received after either reset will use Buffer A. This bit is “don’t care” for indexed single-buffer mode. Broadcast Received. Device logic sets this bit when a valid broadcast mode command is received having T/R bit = 0. This bit has no function if the BCSTINV bit is asserted in Configuration Register 1. In this case, RT address 31 commands are not recognized as valid by the HI-6120/21. This bit is reset to logic 0 by MR master reset or SRST software reset. 10 DPB SR = 0 0 9 BCAST SR = 0 0 HOLT INTEGRATED CIRCUITS 64 HI-6120, HI-6121 Bit No. Mnemonic R/W Reset Function Ping-Pong Enable Acknowledge. This bit is read only and only applies for mode commands using ping-pong mode (PPEN bit 2 was initialized to logic 1 by the host after reset). The device asserts this bit when it recognizes ping-pong is active for this mode code. Before off-loading the receive data buffer for this mode code, the host can ask the device to temporarily disable ping-pong by asserting STOPP bit 3. The device acknowledges ping-pong is disabled by negating PPON. The host can safely load or off-load the buffer without data collision while PPON is negated. After buffer servicing, the host asks the device to re-enable ping-pong by negating STOPP bit 3. The device acknowledges ping-pong is re-enabled by asserting PPON. If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for this subaddress, ping-pong is disabled. Each new message overwrites existing data in the buffer specified by DPB bit 10, and the DPB bit does not toggle after command completion. 7-4 ----0 Not Used Stop Ping-Pong Request. 3 STOPP 0 The host asserts this bit to suspend ping-pong buffering for this mode code. The host resets this bit to ask the device to re-enable ping-pong. The device confirms recognition of ping-pong enable or disable status by writing PPON bit 3. Ping-Pong Buffer Enable. The PPEN bit is initialized by the host to select buffer mode. If this bit is high, ping-pong buffering is selected. If this bit is low, indexed single buffering is selected. After reset, the host initializes this bit to logic 1 to enable ping-pong buffering for this mode code. The host asserts STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the STOPP bit asks the device to re-enable ping-pong. The device confirms ping-pong enable or disable state changes by writing the PPON bit. Not Used. 8 PPON 0 2 PPEN 0 1,0 ----- 0 10.5. Transmit Mode Control Word Transmit Mode Control Words apply when the command word T/R bit equals one (transmit) and the subaddress field has a value of 0 or 31 (0x1F). The descriptor Control Word defines terminal command response and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution begins. Bits 8-11 cannot be written by the host; these bits are updated by the device during terminal execution, that is, when Configuration Register 1 STEX bit equals 1. The host can write bit 2 only when STEX equals zero; bits 3 and 12-15 can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just the DBAC, DPB and BCAST bits. Following any read cycle to the Control Word address, the DBAC bit is reset. When single-message indexed buffering or ping-pong buffering is used instead of SMCP (Simplified Mode Code Processing), the transmit mode Control Word looks like this: HOLT INTEGRATED CIRCUITS 65 HI-6120, HI-6121 KB D US BA Y DC PB BC A PP ST O N H D LSB D1 X ST O PP PP EN IX EQ IW Z A IB R Bit maintained by host Bit maintained by device Bit set by device, reset by host read cycle Bit is not used, may be logic 0 or 1 H H M H H D1 D D D 8 X 7 X 6 X 5 X 4 H 3 H 2 X 1 X 0 MSB 15 14 13 12 11 10 9 When SMCP applies, the number of active mode Control Word bits is reduced: H D LSB D1 X D BA SY C BC A PP ST O N IX EQ IW Z A IB R KB U Bit maintained by host Bit maintained by device Bit set by device, reset by host read cycle Bit is not used, may be logic 0 or 1 H H M H H D1 X D D 8 X 7 X 6 X 5 X 4 X 3 X 2 X 1 X 0 MSB 15 14 13 12 11 10 9 NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is unchanged unless specifically indicated by an “SR” value. Bit No. Mnemonic RW Reset Function Interrupt When Index Equals Zero. If the Interrupt Enable Register IXEQZ bit is high, assertion of this bit enables generation of an interrupt for mode code commands using indexed buffer mode when the INDX value decrements from 1 to 0. Upon completion of command processing that results in INDX = 0, when IXEQZ interrupts are enabled, an IXEQZ interrupt is entered in the Pending Interrupt Register, the INTMES output pin is asserted, and the interrupt is registered in the Interrupt Log. Interrupt When Accessed. 14 IWA 0 If the Interrupt Enable Register IWA bit is high, assertion of this bit enables interrupt generation at each instance of a valid mode code command. Upon completion of command processing, when IWA interrupts are enabled, an IWA interrupt is entered in the Pending Interrupt Register, the INTMES output pin is asserted, and the interrupt is registered in the Interrupt Log. Interrupt Broadcast Received. If the Interrupt Enable Register IBR bit is high, assertion of this bit enables interrupt generation at each instance of a valid broadcast transmit mode code command. Upon completion of command processing, when IBR interrupts are enabled, an IBR interrupt is entered in the Pending Interrupt Register, the INTMES output pin is asserted, and the interrupt is registered in the Interrupt Log. This bit has no function if the BCSTINV bit is high in Configuration Register 1. In this case, commands to RT address 31 are not recognized as valid by the device. 15 IXEQZ 0 13 IBR 0 HOLT INTEGRATED CIRCUITS 66 HI-6120, HI-6121 Bit No. Mnemonic RW Reset Function Make Busy. The host asserts the MKBUSY bit to respond with Busy status for commands to this mode code. This bit is an alternative to globally applying Busy status for all valid commands, enabled from the 1553 Status Bits Register. See that register description for additional information. When Busy is asserted, mode data words are not transmitted with MC16-MC31, and the DPB bit does not toggle after message completion. The MKBUSY bit is not heeded if set in the Control Word for mode code command MC8 “reset remote terminal”. For this command only, Busy is inhibited for the status response transmitted before the reset process begins. Descriptor Block Accessed. 11 DBAC SR = 0 12 MKBUSY 0 0 Internal device logic asserts the DBAC bit upon completion of message processing. The host may poll this bit to detect mode command activity, instead of using host interrupts. This bit is reset to logic 0 by MR master reset, SRST software reset or a read cycle to this memory address. Data Pointer B. This status bit is maintained by the device and only applies for mode commands using ping-pong buffer mode. This bit indicates the buffer to be used for the next occurring mode command. When the DPB bit is logic 0, the next message will use Data Pointer A; when DPB is logic 1, the next message uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each error-free message completion. The DPB bit is not altered after messages ending in error, after illegal commands, or after messages when the terminal responds with Busy status. This bit is reset to logic 0 by MR master reset or SRST software reset; therefore the first message received after either reset will use Buffer A. This bit is “don’t care” for indexed single-buffer mode. Broadcast Received. Device logic sets this bit when a valid broadcast mode command is received having T/R bit = 1. This bit has no function if the BCSTINV bit is asserted in Configuration Register 1. In this case, RT address 31 commands are not recognized as valid by the HI-6120/21. This bit is reset to logic 0 by MR master reset or SRST software reset. Ping-Pong Enable Acknowledge. This bit is read only and only applies for mode commands using ping-pong mode (PPEN bit 2 was initialized to logic 1 by the host after reset). The device asserts this bit when it recognizes ping-pong is active for this mode code. Before loading the transmit data buffer for this mode code, the host can ask the device to temporarily disable ping-pong by asserting STOPP bit 3. The device acknowledges ping-pong is disabled by negating PPON. The host can safely load or off-load the buffer without data collision while PPON is negated. After buffer servicing, the host asks the device to re-enable ping-pong by negating STOPP bit 3. The device acknowledges ping-pong is re-enabled by asserting PPON. If PPEN bit 2 is asserted and PPON bit 8 is negated when a new command arrives for this mode code, ping-pong disable handshake is in effect: The device applies single-buffer index mode using Data Pointer A or Data Pointer B, per DPB bit 10. The DPB bit does not toggle after command completion. 10 DPB SR = 0 0 9 BCAST SR = 0 0 8 PPON 0 HOLT INTEGRATED CIRCUITS 67 HI-6120, HI-6121 Bit No. Mnemonic RW 7-4 ----Reset 0 Function Not Used Stop Ping-Pong Request. 3 STOPP 0 The host asserts this bit to suspend ping-pong buffering for this mode code. The host resets this bit to ask the device to re-enable ping-pong. The device confirms recognition of ping-pong enable or disable status by writing PPON bit 3. Ping-Pong Buffer Enable. The PPEN bit is initialized by the host to select buffer mode. If this bit is high, ping-pong buffering is selected. If this bit is low, indexed single buffering is selected. After reset, the host initializes this bit to logic 1 to enable ping-pong buffering for this mode code. The host asserts STOPP bit 3 to ask the device to temporarily disable ping-pong. Negating the STOPP bit asks the device to re-enable ping-pong. The device confirms ping-pong enable or disable state changes by writing the PPON bit. Not Used. 2 PPEN 0 1,0 ----- 0 HOLT INTEGRATED CIRCUITS 68 HI-6120, HI-6121 11. MESSAGE DATA BUFFERS The memory structures described up to this point comprise not more than 1K words of the lower memory address space. The remaining memory is allocated by the host for message data storage, to fulfill application requirements. This section describes the remaining data structures in shared RAM that control (and result from) command processing. By initializing the Descriptor Table, the host allocates memory space for storing data for each subaddress used in the Remote Terminal application. Each legal Receive Subaddress and each legal Transmit Subaddress are usually assigned unique buffer memory spaces. (Exception: To comply with the requirements for MIL-STD-1553 data wrap-around, it is convenient to assign the data wrap-around subaddress to use the same buffer space for both receive and transmit commands.) As an option, data from broadcast receive commands can be stored separately from data resulting from nonbroadcast receive commands. Each subaddress buffer can use any of four data storage methods offered. Subaddress (non-mode) commands are transacted with one to 32 data words. These are stored in a data buffer in shared RAM. For receive commands, the device stores data received during message processing in the shared RAM buffer. Later, the host retrieves these data words from the buffer. In the case of transmit commands, the host has previously stored transmit data words in the transmit subaddress buffer. The device retrieves these data words for transmission while processing the transmit command. For each complete message processed, the message data stored in the buffer is comprised of these elements: 1. Message Information Word. 2. Time-Tag Word. 3. One to 32 Data Words transmitted or received during message transaction ( except no data word for mode code commands 0 - 15 decimal). The Message Information word and Time-Tag word are generated by the device and stored in assigned buffer space to aid the host in further message processing. The Message Information word contains message type, word count and message error information. The 16-bit Time-Tag word contains the value in the device internal Time-Tag counter when the command is validated. The host initializes the Descriptor Table entry for each subaddress or mode command to select one of four data buffering methods. HOLT INTEGRATED CIRCUITS 69 1. Indexed (Single Buffer) Method (see 11.4). A predetermined number of messages (N) is transacted using a single data buffer in shared RAM. Several host interrupt options are offered, including host interrupt when all N messages are successfully completed. This method also supports single-message mode when N is purposely initialized to zero. 2. Double (or Ping-Pong) Buffer Method (see 11.3). Successive messages alternate between two 34word data buffers in shared RAM. Several host interrupt options are offered. 3. Circular Buffer Mode 1 (see 11.5). Buffer boundaries determine when the bulk transfer is complete. Message information and time-tag words are stored in the same buffer with data words. Several host interrupt options are offered, including host interrupt when the allocated data buffer is full. 4. Circular Buffer Mode 2 (see 11.6). The number of messages transacted defines bulk transfer progress. Message data words are stored contiguously in one buffer while message information and time-tag words are stored in a separate buffer. Several host interrupt options are offered, including host interrupt when all N messages are completed. The data buffer options are summarized in Table 7. Simplified Mode Command Processing. This is a global option that applies for all mode code commands, when enabled. Mode commands have either one data word, or no data word. Instead of using data buffers for storing this limited mode command data, the message data is stored directly within the Descriptor Table. This option for mode commands is described in the section called “Mode Command Processing.” Broadcast Data Separation When the NOTICE2 option is enabled, data words resulting from broadcast receive commands will be stored separately from data resulting from non-broadcast receive commands when using indexed or ping-pong buffer modes. When NOTICE2 applies, all subaddresses using indexed or ping-pong modes must have an assigned 34-word broadcast data buffer in addition to the primary buffers listed above. Broadcast data segregation cannot be done using either circular buffer mode. HI-6120, HI-6121 Table 7. Summary of Data Buffer Modes. Buffer Mode Indexed Ping-Pong Circular 1 Circular 2 Data Buffer(s) Number and Size One. Host defines size for N messages Message Info Word Stored in same buffer as data Suitable for Mode Codes? Primary Application Yes, only single For transacting N (multiple) messages message mode with optional host interrupt when done Yes No No For transacting single messages, alternating between A and B buffers For transacting messages until buffer is full / empty, optional interrupt when done For transacting N (multiple) messages with optional host interrupt when done. Data buffer holds contiguous pure data. Two 34-word buffers, Stored in same one message each buffer as data One. Host defines size for N words Stored in same buffer as data One. Host defines Stored in size for N messages, separate buffer plus Msg Info Block (Msg info block) 11.1. Subaddress Message Information Words 11.1.1. Receive Subaddress Command For receive subaddress commands, the device stores the received data words plus two additional words. The device adds a receive subaddress Message Information Word and a Time-Tag Word to the received data words. The device stores the Message Information and Time-Tag words ahead of the data words associated with the receive command, as shown below. If message error occurs, the RT stores only the receive subaddress Message Information Word and Time-Tag Word. Once a message error is detected, the device sets the MERR bit in the receive subaddress Message Information word. When this occurs, all data words are considered invalid. Whenever the receive subaddress Message Information Word MERR bit is set, the host should disregard the record’s data word(s). Here is an example data structure for a 3-word receive command. Notice that the receive subaddress Data Pointer points to the data structure starting address, not the first data word. The data pointer is located in the receive subaddress command’s Descriptor Block, fully described later: Data Buffer Hex Address Data pointer equals 0x0500 → 0x0500 0x0501 0x0502 0x0503 0x0504 Word Description Device Writes Word ... Message Information Word After message completion Time-Tag Word “ “ “ Data Word 1 After message completion (See Note) Data Word 2 “ “ “ “ “ Data Word 3 “ “ “ “ “ Note: The data words are written after message completion when Configuration Register 2 TRXDB is 1, otherwise written when received. HOLT INTEGRATED CIRCUITS 70 HI-6120, HI-6121 O IW ER DR G ER AP R W ER CR T SY ER NR M ER ER R WR AS IL BS CY M TX D R RT TE R RR BU T S W ID C 4 W C 3 W C 2 W C 1 W C 0 MSB 15 14 13 12 11 10 9 TM 8 7 6 5 4 3 2 1 0 LSB The following bits comprise the receive subaddress Message Information Word: Bit No. Mnemonic Function Time-Out Error. 15 TMOERR This bit is asserted for RT-RT receive messages when the transmitting terminal fails to start its status word and data transmission before time-out occurs, per TOSEL0-1 bits in Configuration Register 2. Invalid Word Error. 14 IWDERR Assertion of this bit indicates Manchester error or parity error was observed in a received data word. Gap Error. 13 GAPERR Assertion of this bit indicates bus activity was detected immediately after the last expected receive data word or that a gap occurred before all expected data words were received. Word Count Error. 12 WCTERR This bit is asserted if command is received with less data words than the command word specifies. For example, a receive command for three data words is received with two contiguous data words. Sync Error. 11 SYNERR This bit is asserted when an incorrect (command/status) sync type occurs in received data words. Message Error. 10 MERR This bit is asserted when message error status change occurs during command processing. See bits 7 and 11-15 for details. Was Busy. 9 WASBSY This bit is asserted when the terminal responds to the receive command with BUSY status, due to global BUSY bit set in 1553 Status Bits Register, or command-specific MKBUSY bit set in the descriptor table Control Word. Received data words were buffered normally. Illegal Command Received. 8 ILCMD This bit is asserted when the Illegalization Table bit corresponding to the received command is logic 1. The Illegalization Table should only contain nonzero values when “illegal command detection” is being applied. See section entitled Illegalization Table for further information. HOLT INTEGRATED CIRCUITS 71 HI-6120, HI-6121 Bit No. Mnemonic Function RT-RT Transmit Remote Terminal Error. This bit is set when the terminal decodes a valid RT-RT receive command, but one of four potential errors is detected in the second command word, CW2: (1) CW2 is addressed to broadcast address RT31. (2) the CW2 T/R bit equals 0, (3) the CW2 subaddress is a mode command indicator, 00000 or 11111, or (4) CW2 has same non-broadcast terminal address as receive command word CW1. The TXRTERR bit is also set when status word received from the transmitting terminal is invalid (e.g., parity error) or bits 15:11 in the status word reflect the wrong RT address (does not match CW2). 6 RTRT Remote Terminal to Remote Terminal Transfer. Assertion of this bit indicates the receive command was an error-free RT-to-RT transfer. Bus Identification. 5 BUSID If this bit equals zero, message was transacted on Bus A. If bit equals one, it was transacted on Bus B. Word Count. 4-0 WC4:0 This 5-bit field contains the word count extracted from the command word. Zero indicates 32 words. 7 TXRTERR 11.1.2. Transmit Subaddress Command The external host is responsible for organizing the data packet (i.e., storing N data words) in shared RAM and initializing the applicable data pointer. The host must allocate two memory locations at the starting address of the data record for device storage of the transmit subaddress Message Information Word and Time-Tag Word. Here is an example data structure for a 3-word transmit command. Notice that the Data Pointer points to the data structure starting address, not the first data word. The data pointer is located in the transmit subaddress command’s Descriptor Block. Data Buffer Hex Address Data pointer equals 0x0500 → 0x0500 0x0501 0x0502 0x0503 0x0504 Word Description Word is Written By ... Message Information Word Device, after message completion Time-Tag Word “ “ “ “ Data Word 1 Host, prior to terminal’s data transmit Data Word 2 “ ““ “ “ “ Data Word 3 “ ““ “ “ “ AP W ER CR TE R R M ER WR AS IL BS CY M D X X X 8 X 7 6 5 4 3 2 1 0 LSB MSB 15 14 13 12 11 10 9 The following bits comprise the transmit subaddress Message Information Word. RT R BU T S W ID 4 W 3 W 2 W 1 W 0 G HOLT INTEGRATED CIRCUITS 72 HI-6120, HI-6121 Bit No. 15,14 13 Mnemonic ----GAPERR Function Not Used. Gap Error. Assertion of this bit indicates bus activity was detected immediately after the transmit command word, when a gap was expected. Word Count Error. This bit is asserted if command is received with unexpected data word(s). Not Used. Message Error. 10 MERR This bit is asserted when message error status change occurs during command processing. See bits 12 and 13 for details. Was Busy Status. 9 WASBSY This bit is asserted when the terminal responds to the transmit command with BUSY status, due to global BUSY bit set in 1553 Status Bits Register, or command-specific MKBUSY bit set in the descriptor table Control Word. No data words were transmitted. Illegal Command Received. 8 ILCMD This bit is asserted when the Illegalization Table bit corresponding to the received command equals one. The Illegalization Table should only contain nonzero values when “illegal command detection” is being applied. See section entitled Illegalization Table for further information. Not Used. Remote Terminal to Remote Terminal Transfer. Assertion of this bit indicates the transmit command was an error-free RT-to-RT transfer. Bus Identification. 5 BUSID If this bit equals zero, message was transacted on Bus A. If bit equals one, it was transacted on Bus B. Word Count. 4-0 WC4:0 This 5-bit field contains the word count extracted from the command word. Zero indicates 32 words. 12 11 WCTERR ----- 7 6 ----RTRT 11.2. Mode Command Message Information Words Mode command data structures in shared RAM are similar to those for subaddresses. Mode codes 0 through 15 (0x0F) do not have an associated data word, so data structures for these mode code values have just a Message Information Word and Time-Tag Word. The Message Information Word is stored at the memory address specified by the descriptor table Data Pointer. Mode codes 16 through 31 (0x10 through 0x1F) have one associated data word. The Message Information Word is stored at the memory address specified by the descriptor table Data Pointer, and the Time-Tag Word is stored in the following location. The data word is stored at the memory address specified by the Data Pointer plus two locations. 11.2.1. Receive Mode Command The receive mode command data structure contains a Message Information Word, a Time-Tag Word and may contain one Data Word. If a receive mode command has a data word, the device may apply the data as defined by MILHOLT INTEGRATED CIRCUITS 73 HI-6120, HI-6121 STD-1553, plus store the received single mode data word at the address specified by the Data Pointer, plus two locations. Refer to data sheet section entitled “Mode Command Action Summary”. Here is an example data structure for a receive mode command with data (mode code values 0x10 through 0x1F). Notice that the Data Pointer points to the data structure starting address, not the mode data word. The data pointer is located in the receive mode command’s Descriptor Block, fully described later: Data Buffer Hex Address Data pointer equals 0x0500 → 0x0500 0x0501 0x0502 Word Description Word is Written By ... Message Information Word Device, after message completion Time-Tag Word “ “ “ “ Mode Data Word “ “ “ “ Three receive mode commands with data are not defined under MIL-STD-1553B. These are MC16, MC18 and MC19 (mode codes 0x10, 0x12 and 0x13 respectively). However the device responds “in form” if illegal command detection is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in Configuration Register 1 is logic 0. For mode code commands without data, the data structure contains only the Message Information Word and Time-Tag Word. Here is an example data structure for a receive mode command without data (mode code values 0x00 through 0x0F). Note: None of these receive mode commands are defined under MIL-STD-1553B but the device responds “in form” if illegal command detection is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in Configuration Register 1 is logic 0. Notice that the data pointer points to the data structure starting address, the message information word. The data pointer is located in the receive mode command’s Descriptor Block, fully described later: Data Buffer Hex Address Data pointer equals 0x0500 → 0x0500 0x0501 Word Description Word is Written By ... Message Information Word Device, after message completion Time-Tag Word “ “ “ “ D G ER AP R W ER CR T SY ER NR M ER ER R WR AS IL BS CY M D X MSB 15 14 13 12 11 10 9 8 X 7 X 6 5 4 3 2 1 0 LSB The following bits comprise the receive mode Message Information Word: Bit No. 15 14 Mnemonic ----IWDERR Function Not Used. Invalid Word Error. Assertion of this bit indicates Manchester error or parity error was observed in a received data word. Gap Error. 13 GAPERR Assertion of this bit indicates bus activity was detected immediately after a received mode data word or that a gap occurred before the data word was received. HOLT INTEGRATED CIRCUITS 74 S M ID C 4 M C 3 M C 2 M C 1 M C 0 BU IW HI-6120, HI-6121 Bit No. 12 Mnemonic WCTERR Function Word Count Error This bit is asserted if the command is received without expected mode data word, or with extra word. Sync Error. 11 SYNERR This bit is asserted when incorrect (command/status) sync type occurs in received mode data word. Message Error. 10 MERR This bit is asserted when message error status change occurs during command processing. See bits 11- 14 for details. Was Busy Status. 9 WASBSY This bit is asserted when the terminal responds to the mode command with BUSY status, due to global BUSY bit set in 1553 Status Bits Register, or command-specific MKBUSY bit set in the descriptor table Control Word. Illegal Command Received. 8 ILCMD This bit is asserted when the Illegalization Table bit corresponding to the received command equals one. The Illegalization Table should only contain nonzero values when “illegal command detection” is being applied. See section entitled Illegalization Table for further information. Not Used. Bus Identification. 5 BUSID If this bit equals zero, message was transacted on Bus A. If bit equals one, it was transacted on Bus B. Mode Code. This 5-bit field contains the mode code extracted from the command word. 7,6 ----- 4-0 MC4:0 11.2.2. Transmit Mode Command The transmit mode command data structure contains a Message Information Word, a Time-Tag word and may contain one Data Word. For mode commands with associated data word (mode codes 16-31 decimal) the host is responsible for loading the Mode Command Data Table before transmit mode commands are received (e.g., Transmit Vector Word mode code). Two mode codes have internally generated data words: MC18 “Transmit Last Command” and MC19 “Transmit BIT Word”. For these, the device automatically transmits the data word then copies the transmitted data value to the stored data structure. Here is an example data structure for a transmit mode command with data (mode code values 0x10 through 0x1F). This applies to MC16 “Transmit Vector Word”. Notice that the data pointer points to the data structure starting address, not the mode data word. The data pointer is located in the transmit mode command’s Descriptor Block, fully described later: HOLT INTEGRATED CIRCUITS 75 HI-6120, HI-6121 Data Buffer Hex Address Data pointer equals 0x0500 → 0x0500 0x0501 0x0502 Word Description Word is Written By ... Message Information Word Device, after message completion Time-Tag Word “ “ “ “ Mode Data Word Host, prior to terminal’s data transmit (except MC18, MC19 are written by the device after completion) Three transmit mode commands with data are not defined under MIL-STD-1553B. These are MC17, MC20 and MC21 (mode codes 0x11, 0x14 and 0x15 respectively). However the device responds “in form” if illegal command detection is not used (corresponding bits in Illegalization Table are logic 0) and the UMCINV bit in Configuration Register 1 is logic 0. For mode code commands without data, the data structure contains only the Message Information Word and Time-Tag Word. Here is an example data structure for a transmit mode command without data (mode code values 0x00 through 0x0F). Again, the data pointer points to the data structure starting address. The data pointer is located in the transmit mode command’s Descriptor Block, fully described later: Data Buffer Hex Address Data pointer equals 0x0500 → 0x0500 0x0501 Word Description Word is Written By ... Message Information Word Device, after message completion Time-Tag Word “ “ “ “ AP W ER CR TE R R M ER WR AS IL BS CY M D X X X 8 X 7 X 6 5 4 3 2 1 0 LSB MSB 15 14 13 12 11 10 9 The following bits comprise the mode transmit Message Information Word: Bit No. 15,14 13 Mnemonic ----GAPERR Function Not Used. Gap Error. This bit is high when bus activity was detected immediately after the mode command word, when a gap was expected. Word Count Error This bit is asserted if command is received with unexpected data word(s). Not Used. Message Error. 10 MERR This bit is asserted when message error status change occurs during command processing. See bits 12-13 for details. Was Busy Status. 9 WASBSY This bit is asserted when the terminal responds to the mode command with BUSY status, due to global BUSY bit set in 1553 Status Bits Register, or command-specific MKBUSY bit set in the descriptor table Control Word. No mode data word was transmitted. HOLT INTEGRATED CIRCUITS 76 12 11 WCTERR ----- BU S M ID C 4 M C 3 M C 2 M C 1 M C 0 G HI-6120, HI-6121 Bit No. Mnemonic Function Illegal Command Received. 8 ILCMD This bit is asserted when the Illegalization Table bit corresponding to the received command is logic 1. The Illegalization Table should only contain nonzero values when “illegal command detection” is being applied. See section entitled Illegalization Table for further information. Not Used. Bus Identification. 5 BUSID If this bit equals zero, message was transacted on Bus A. If bit equals one, it was transacted on Bus B. Mode Code. This 5-bit field contains the mode code extracted from the command word. 7,6 ----- 4-0 MC4:0 HOLT INTEGRATED CIRCUITS 77 HI-6120, HI-6121 11.3. Ping-Pong Data Buffering 11.3.1. Double Buffered (Ping-Pong) Mode Ping-pong buffer mode is a method for storing message and time-tag information and data associated with messages. Each unique MIL-STD-1553 subaddress and mode code is assigned a pair of data buffers for transmit commands and a pair of data buffers for receive commands. The device retrieves buffer data for transmit commands, or stores buffer data for receive commands. During ping-pong operation, the device alternates message storage between Data Buffer A and Data Buffer B, on a message-by-message basis. When a subaddress or mode command uses ping-pong data buffer mode, its 4-word descriptor block in the Descriptor Table is defined as follows: Descriptor Word 1 Descriptor Word 2 Descriptor Word 3 Descriptor Word 4 Control Word Data Pointer A Data Pointer B Broadcast Data Pointer 11.3.2. Ping-Pong Enable / Disable Handshake Because ping-pong messages and host buffer servicing are asynchronous, there is potential for “data collision”. Here is a data collision example: The host reads data from an earlier message while the device simultaneously writes new message data to the same buffer. The host reads a mix of new and old message data. Collisions can occur for both transmit and receive messages. A handshake scheme lets the external host asynchronously service ping-pong data buffers without data collision. To off-load or load a subaddress (or mode code) buffer, the application software performs the following sequence: a. Host asserts the Control Word STOPP bit to suspend ping-pong operation for the subaddress. When the device recognizes STOPP bit assertion, it negates the PPON bit to acknowledge ping-pong is disabled. While PPON remains low, the last written (or read) data buffer is protected against device updates. During this time, new messages use the active buffer indicated by the Control Word DPA bit. Recurring messages repeatedly use the same buffer until ping-pong resumes. b. Host services the last-used data buffer. If the Control Word DPB bit equals logic 1, the last command used Buffer A. The host application software off-loads or loads inactive Buffer A while the remote terminal uses active Buffer B for new message(s). If the DPB bit equals logic 0, the last command used Buffer B. The host application software off-loads or loads inactive Buffer B while the remote terminal uses active Buffer A for any new messages. Each new receive message overwrites buffer contents from the last receive message. To avoid possible data loss, host buffer servicing should be timed for completion before a second message can occur. c. Host negates the Control Word STOPP bit to resume ping-pong operation for the subaddress. When the RT recognizes the STOPP bit is reset, it sets the PPON bit to acknowledge ping-pong is again active. As long as PPON remains set, the device alternates between data buffers A and B for new messages. If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two words are stored at addresses N+2 and N+3. Prior to starting terminal operation, enable ping-pong buffering for any subaddress (or mode code) by asserting the PPEN bit and negating the STOPP bit in the descriptor Control Word. When the device detects pingpong is selected (PPEN = 1) and enabled (STOPP = 0), it asserts the Control Word PPON bit to confirm pingpong is active. During ping-pong operation, the RT determines the active data buffer at the beginning of message processing. The Control Word DPB bit indicates the data pointer to be used by the next command. DPB equals logic 0 means Data Pointer A is used next; DPB equals logic 1 means Data Pointer B is used next. For ping-pong, Data Pointers A and B are static values pointing to the first address in each buffer. At the conclusion of error-free message processing, the Control Word DPB bit is inverted so the next command “ping-pongs” to the other data buffer. Each new message to the subaddress or mode code overwrites message data and information words written two messages back. The DPB bit does not toggle when a message ends in error, or if the command was illegal, or if Busy status applied for the received command. In these cases, the next command will overwrite the same buffer. Figure 10 is a general illustration of ping-pong buffer mode. Figure 11 shows a specific example. HOLT INTEGRATED CIRCUITS 78 HI-6120, HI-6121 Data Word 32 Data Words 2-31 Data Word 1 Broadcast Message (if NOTICE2 is asserted) Time-Tag Word Message Info Word Subaddress Buffer Space for Broadcast (optional) Message #2 Message #4 Message #6 etc. Data Word 32 Data Words 2-31 Data Word 1 Time-Tag Word Message Info Word Assigned Subaddress Data Buffer B B’cast Data Pointer Increasing Memory Address Data Pointer A Data Pointer B Control Word Data Word 32 Data Words 2-31 Data Word 1 Descriptor Block for Subaddress Message #1 Message #3 Message #5 etc. Time-Tag Word Message Info Word Assigned Subaddress Data Buffer B Memory Address for the Applicable Subaddress Block is Derived From the Decoded Command Word Message processing alternates between Data Buffers A and B. Upon sucessful message completion, the DPB bit in Descriptor Control Word is updated so next message uses other buffer. Buffers are overwritten every other message. Separate buffer for broadcast messages is optional. There is no alternate buffer for successive broadcast messages. Figure 10. Illustration of Ping-Pong Buffer Mode HOLT INTEGRATED CIRCUITS 79 HI-6120, HI-6121 11.3.3. Broadcast Message Handling in PingPong Mode For MIL-STD-1553B Notice II compliance, a remote terminal should be capable of storing data from broadcast messages separately from non-broadcast message data. Some applications may not include this requirement. The standard does not stipulate where data separation should occur (e.g., within the RT or within the external host) so the device provides alternative strategies. When the NOTICE2 bit in Configuration Register 1 is 1 and the BCSTINV bit is 0, ping-pong mode subaddresses (or mode codes) will buffer data words from broadcast and non-broadcast messages separately. Broadcast message information and data are stored in the broadcast data buffer; non-broadcast message information and data are stored in ping-pong buffers A and B. Since there is just one broadcast data buffer, the NOTICE2 option treats broadcast messages as exceptions to normal ping-pong mode. When using the NOTICE2 option, broadcast data buffer servicing should have high priority, because a closely following broadcast message will overwrite the broadcast buffer. Every mode command and subaddress (including transmit subaddresses) must have an assigned valid broadcast data pointer when NOTICE2 is asserted. When the NOTICE2 bit in Configuration Register 1 is 1 and the BCSTINV bit is 0, reception of a broadcasttransmit message updates the Message Information and Time-Tag Words for the assigned broadcast buffer, but no data is transmitted on the bus. Since broadcasttransmit is not allowed, multiple transmit subaddresses may share a common “bit bucket” broadcast buffer. A two word buffer is sufficient for storing the MIW and Time-Tag Word. When using ping-pong mode, there are two ways to handle broadcast messages, when broadcast is enabled: Option 1 for Ping-Pong Mode Broadcast Messages: This option isolates broadcast message information in the broadcast data buffer. If the descriptor Control Word IBR bit and Interrupt Enable Register IBR bit are both set, reception of broadcast messages generates an INTMES host interrupt. To prevent data loss, the broadcast data buffer must be serviced before the next broadcast message occurs. Broadcast messages do not affect non-broadcast message ping-pong; the Control Word DPB bit does not toggle after broadcast message completion. Option 1 Setup: At initialization, host asserts the NOTICE2 bit in Configuration Register 1 and sets the HOLT INTEGRATED CIRCUITS 80 IBR (Interrupt Broadcast Received) bit in descriptor Control Word(s). The IBR bit is asserted in the Interrupt Enable Register. When a broadcast command is received, message information and data is stored in the broadcast data buffer and an INTMES interrupt is generated. The host must read the Interrupt Log to determine the originating subaddress (or mode code), then service the broadcast data buffer for that subaddress (or mode code) before another broadcast message to the same subaddress (or mode code) arrives. Option 2 for Ping-Pong Mode Broadcast Messages: The second alternative stores both broadcast and nonbroadcast message information in the ping-pong data buffers A and B. IWA interrupts can signal arrival of any new message. The RT handles broadcast messages just like non-broadcast messages, except the Message Information Word BCAST bit is asserted to identify broadcast messages during host buffer servicing. All messages toggle the Control Word DPB bit in message post-processing. For Notice II compliance, separation of broadcast and non-broadcast data occurs within the host. Option 2 Setup: At initialization, host negates the NOTICE2 bit in Configuration Register 1. If IWA interrupts are used, the host asserts the descriptor Control Word IWA (Interrupt When Accessed) bit 14 and the corresponding bit is asserted in the Interrupt Enable Register. Using this option, the IBR interrupt is probably not used. The host typically services the ping-pong data buffers A and B whenever a message is transacted. Using the setup above, this occurs whenever the subaddress IWA interrupt generates an INTMES interrupt output for the host. The host must read the Interrupt Log to determine the originating subaddress or mode code. The applicable data buffer is indicated by the DPB bit in the Receive Control Word. The Message Information Word BCAST bit is asserted if the message was broadcast. HI-6120, HI-6121 Data Word 32 Data Words 2-31 0x0565 0x0547 - 0x0564 0x0546 0x0545 0x0544 0x0543 0x0525 - 0x0542 0x0524 0x0523 0x0522 0x0521 0x0503 - 0x0520 0x0502 0x0501 0x0500 RAM Address Device sets Control Word BCAST bit (DPB bit remains static) IBR interrupt is generated Assigned Subaddress Broadcast Data Buffer Data Word 1 Time-Tag Word BC Msg Info Word BC Data Word 32 Data Words 2-31 Receive Message #2 Broadcast, 32 Data Words Device resets Control Word DPB and BCAST bits Assigned Subaddress Data Buffer B Data Word 1 Time-Tag Word B Msg Info Word B Data Word 32 Data Words 2-31 Receive Message #3 Non-Broadcast, 32 Data Words Device resets Control Word DPB bit Assigned Subaddress Data Buffer A Data Word 1 Time-Tag Word A Msg Info Word A Receive Message #1 Non-Broadcast, 32 Data Words Message #4 also uses this buffer, if not broadcast Increasing Memory Address B’cast Data Pointer Data Pointer B Data Pointer A Control Word Broadcast Data Pointer = 0x0544 start address in RAM Data Pointer B = 0x0522 Buffer B start address in RAM Data Pointer A = 0x0500 Buffer A start address in RAM Control Word = 0x2010 Ping-Pong Mode, IBR Interrupt Initialized Descriptor Values Descriptor Block for a Receive Subaddress Following reset (which resets Control Word DPB bit), the subaddress transacts 4 commands of 32 data words each. The NOTICE 2 option is enabled so the device segregates data from broadcast and non-broadcast messages. Message #2 is a broadcast command, while the other three messages are non-broadcast. Notice that the broadcast message does not affect DPB bit, but the following message resets BCAST bit. The interspersed broadcast command does not affect alternation between Buffer A and Buffer B. Figure 11. Ping-Pong Buffer Mode Example for a Receive Subaddress HOLT INTEGRATED CIRCUITS 81 HI-6120, HI-6121 11.4. Indexed Data Buffer Mode Also called “single buffer mode”, indexed buffering is one method for storing message and time-tag information and data associated with messages. Buffer mode is selected for each subaddress or mode code in the Descriptor Table Control Words. Indexed mode is enabled when Control Word PPEN, CIR1EN and CIR2EN bits are all zero. When a subaddress or mode command uses the indexed data buffer mode, its 4-word descriptor block in the Descriptor Table is defined as follows: Descriptor Word 1 Descriptor Word 2 Descriptor Word 3 Descriptor Word 4 Control Word Data Pointer A INDX Index Word Broadcast Data Pointer INDX equals zero, further commands will overwrite the last-written data buffer block and the data pointer value is not updated after successful message completion. When using Index Mode with a non-zero INDX value, the host must remember the initial Data Pointer A address. The Data Pointer A word is not automatically reinitialized to the buffer start address when INDX decrements from 1 to 0. 11.4.1. Single Message Mode When Index Mode is initialized with an INDX value of zero, the subaddress or mode code is operating in “Single Message Mode”. Here, the same data block is repeatedly over-read (for transmit data) or overwritten (for receive or broadcast data). The DPA pointer is not updated at the end of each message. The chief advantage of single message mode is simplicity. In comparison to other data buffering options, the single message buffer uses an absolute minimum amount of memory space. The IXEQZ interrupt cannot be used for this scheme (INDX is always zero) but IWA interrupts may be used. Single message mode is best suited to synchronous data transfer where the host processor can reliably read or write new message data prior to the start of the next message to the same subaddress or mode code. If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two words are stored at addresses N+2 and N+3. As the name implies, all message information and data is stored in a single buffer, indexed by descriptor word Data Pointer A. The descriptor Control Word DPB bit is “don’t care”. The host initializes the desired message count in descriptor INDX word. During message processing, the device retrieves or stores data words from the address specified by descriptor Data Pointer A, automatically incrementing the pointer address as words are read or stored. Data Pointer A is updated during command post-processing with the current buffer address unless the message index count in descriptor INDX (word 3 of descriptor block) decrements to zero upon completion of the message. Figure 12 is a general illustration of indexed single buffer mode. Figure 13 shows a specific example. To set up a terminal subaddress to buffer multiple messages, the host writes the desired index count (INDX) to subaddress descriptor word 3. The initial INDX value ranges from zero to 3FF hex (1023) messages. The device decrements the INDX count each time an error-free message is transacted, and the data pointer is updated to the first memory address to be used for the next message. If INDX decrements from one to zero and Control Word IXEQZ bit 15 is asserted, the IXEQZ bit is set in the Interrupt Pending Register. If the corresponding bit in the Interrupt Enable Register is asserted, an INTMES interrupt is generated when INDX decrements from one to zero. INDX counter decrement does not occur if the command was illegalized or if INDX already equals zero. Once 11.4.2. Broadcast Message Handling in Index Mode For MIL-STD-1553B Notice II compliance, a remote terminal should be capable of storing data from broadcast messages separately from non-broadcast message data. Some applications may not include this requirement. The standard does not stipulate where data separation should occur (e.g., within the RT or within the external host) so the device supports alternative strategies. When the NOTICE2 bit is logic 1 in Configuration Register 1, broadcast message data is stored in a broadcast data buffer assigned for the subaddress or mode command. Each subaddress or mode command must have an assigned, valid non-zero broadcast buffer address. Non-broadcast message data is stored in Data Buffer A. There are two ways to deal with broadcast messages in indexed buffer mode: Option 1 for Index Mode Broadcast Messages: The first alternative isolates broadcast message information in the broadcast data buffer. If the descriptor Control Word IBR bit and Interrupt Enable Register IBR bit are both set, reception of broadcast messages generates an INTMES interrupt to the host. The broadcast data buffer HOLT INTEGRATED CIRCUITS 82 HI-6120, HI-6121 must be processed before another broadcast message arrives to prevent loss of data. Broadcast messages do not decrement the INDX register, and Data Pointer A is not updated in message post-processing. This scheme may be well suited for Single Message Mode (INDX = 0) when the host can reliably service either the broadcast data buffer or data buffer A before the next receive message arrives for the same subaddress (or mode code). Option 1 Setup: At initialization, host asserts NOTICE2 bit in Configuration Register 1 and sets the Control Word IBR (Interrupt Broadcast Received) bit for each index mode descriptor block. The IBR bit is also asserted in the Interrupt Enable Register. When a broadcast command is received, message information and data are stored in the broadcast data buffer. If descriptor Control Word IBR bit is set, an INTMES interrupt is generated. The host must read the Interrupt Log to determine the originating subaddress (or mode code) then service the broadcast data buffer for that subaddress (or mode code) before the next broadcast message to the same subaddress (or mode code) arrives. Option 2 for Index Mode Broadcast Messages: The second alternative stores both broadcast and nonbroadcast message information in data buffer A. Optional IBR interrupts can signal arrival of broadcast messages. The RT handles broadcast messages just like non-broadcast messages, except the Message Information Word BCAST bit is asserted to identify broadcast messages during host buffer servicing. All messages decrement the INDX register and Data Pointer A is updated in message post-processing. This scheme is compatible with Single Message Mode or conventional Nmessage indexing. For Notice II compliance, separation of broadcast and non-broadcast data occurs within the host. Option 2 Setup: At initialization, host negates the NOTICE2 bit in Configuration Register 1. If broadcast interrupts are used, the Control Word IBR (Interrupt Broadcast Received) bit is asserted at each desired index mode descriptor block. The IBR bit is also asserted in the Interrupt Enable Register. Using option 2, the host has several options for servicing data buffer A: (a) when INDX decrements from one to zero (using the IXEQZ interrupt), (b) when a broadcast message occurs (using the IBR interrupt) or (c) when any message arrives (using the IWA interrupt). HOLT INTEGRATED CIRCUITS 83 HI-6120, HI-6121 Data Word N Data Word(s) Increasing Memory Address Data Word 1 Next Message Time-Tag Word Message Info Word Data Word N Data Word(s) Data Word N Data Word(s) Data Word 1 Time-Tag Word Message Info Word Subaddress Buffer Space for Broadcast (optional) Broadcast Message (if NOTICE2 is asserted) B’cast Data Pointer INDX Index Count Data Pointer A Control Word Descriptor Block for Subaddress Preceding Message Current Message Data Word 1 Time-Tag Word Message Info Word Data Word N Data Word(s) Data Word 1 Time-Tag Word Message Info Word Assigned Subaddress Buffer Space Memory Address for the Applicable Subaddress Block is Derived From the Decoded Command Word Upon successful message completion, if non-zero the INDX count in Descriptor Word 3 is decremented. If decremented result is non-zero, Data Pointer A is adjusted so next message is stored above just-completed message. If decremented INDX is zero, Data Pointer A remains static and IXEQZ interrupt occurs if enabled in Control Word. Figure 12. Illustration of Indexed Buffer Mode HOLT INTEGRATED CIRCUITS 84 HI-6120, HI-6121 Data Word 4 Data Word 3 Data Word 2 Data Word 1 Messages #2, #3, etc Receive 4 Words Time-Tag Word 1 Msg Info Word 1 Data Word 3 Data Word 2 Data Word 1 Messages #1 Receive 3 Words Time-Tag Word 1 Msg Info Word 1 Assigned Receive Subaddress Buffer 0x050A 0x0509 0x0508 0x0507 0x0506 0x0505 0x0504 0x0503 0x0502 0x0501 0x0500 RAM Address For Message #2, Index decrements to zero. Data Pointer A = 0x0505 (static) IXEQZ Interrupt is generated For Message #3 and beyond, the data buffer is overwritten. Index remains zero (static) Data Pointer A = 0x0505 (static) and no IXEQZ interrupt occurs. Index decrements to one Data Pointer A = 0x0505 Index equals two Increasing Memory Address B’cast Data Pointer INDX Index Count Data Pointer A Control Word Descriptor Block for a Receive Subaddress Broadcast Data Pointer = 0xXXXX Don’t Care Index = 0x0002 Initialize index for 2 messages Data Pointer A = 0x0500 Buffer Start Address in RAM Control Word = 0x8000 Index Mode, IXEQZ Interrupt Initialized Descriptor Values Figure 13. Indexed Buffer Mode Example for a Receive Subaddress (broadcast not enabled) HOLT INTEGRATED CIRCUITS 85 HI-6120, HI-6121 11.5. Circular Buffer Mode 1 The device offers two circular data buffer modes as alternatives to ping-pong and indexed buffering. These circular buffer options only apply for subaddress commands, not mode code commands. Circular buffering simplifies software servicing of the remote terminal when implementing bulk data transfers. A circular buffer mode can be selected for any subaddress by properly initializing its descriptor Control Word. Circular Buffer Mode 1 is selected when descriptor Control Word PPEN and CIR2EN bits are both 0, and the CIR1EN bit is logic 1. When a subaddress uses circular buffer mode 1, its four word block in the Descriptor Table is defined as follows: Descriptor Word 1 Descriptor Word 2 Descriptor Word 3 Descriptor Word 4 Control Word SA (Buffer Start Address) CA (Buffer Current Address) EA (Buffer End Address) circular buffer wraps to the start address after completing a message that results in CA being greater than or equal to EA. If CA increments past EA during message processing, the device will access memory addresses greater than the EA value. Reserve 33 address locations past the EA address to accommodate a worst-case 32 data word message with a record starting at address = EA minus 1. Each receive subaddress and transmit subaddress may have a unique circular buffer assignment. The RT decodes the command word T/R bit, subaddress field and word count / mode code field to select the unique command descriptor block containing the Control Word, SA pointer, CA pointer and EA pointer. For receive messages, the device stores the Message Information word to the address specified by CA, the Time-Tag word into CA+1 and the data into the next “N” locations starting with CA+2. For transmit messages, the device stores the Message Information word to the address specified by CA and the Time-Tag word into CA+1. Retrieval of data for transmission starts at address CA+2. When entering multiple transmit command data packets into the circular buffer, delimit each data packet with two reserved memory locations. The device stores the Message Information word and Time-Tag word into the reserved locations when processing the command. Message processing for all commands begins with the device reading the unique descriptor block for the subaddress or mode code specified by the T/R bit, subaddress and word count fields in the received command word. For receive messages, the device stores “N” received data words in the circular data buffer. The first data word received is stored at the location specified by the CA pointer +2. After message completion, the device stores the Message Information word and Time-Tag words to addresses CA and CA+1 respectively. If no errors were detected, the device updates descriptor CA register. If the next address location (last stored data word +1) is less than or equal to EA, CA is updated to (last stored address +1). If the next address location (last stored data word +1) is greater than EA, the data buffer is full (or empty); CA is updated to the SA value. If descriptor Control Word IXEQZ bit is asserted (and if Interrupt Enable Register IXEQZ bit is asserted) the device generates an interrupt to indicate full receive buffer by asserting the INTMES interrupt output. Although all messages store Message Information and Time-Tag words, no data is stored if the message ended with error, or if the Busy status bit was set or if the commend was illegal (example: illegalized word count). If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two words are stored at addresses N+2 and N+3. Figure 14 provides a generalized illustration of Circular Buffer Mode 1, while Figure 15 shows a specific example. Circular Buffer Mode 1 uses a single user-defined buffer that merges all transmit or receive data, along with message information. Two words (Message Information and Time-Tag) are stored at the beginning of the block for each message, followed by the message data word(s). The Mode 1 buffer pointers roll over (are reset to their base addresses) when the allocated data buffer memory is full. For each valid receive message, the device enters a Message Information word, Time-Tag word and data word(s) into the circular receive buffer. For each valid transmit message, the device enters a Message Information word and a Time-Tag word into reserved memory locations within the circular transmit buffer. The device automatically controls the wrap around of circular buffers. Two pointers define circular buffer length: start of buffer (lowest address) and end of buffer (highest address). User specifies the start of buffer (SA) by writing the lowest address value into the second word of a unique subaddress descriptor block. The user defines the bottom of the buffer (EA) by writing the highest address value to the fourth word of that unique descriptor block. Both SA and EA remain static during message processing. The third word in the descriptor block identifies the current address CA (i.e., last accessed address plus one). The HOLT INTEGRATED CIRCUITS 86 HI-6120, HI-6121 Such messages do not update CA, so the next message overwrites the same buffer space. For transmit commands, the device begins transmission of data retrieving the first data word stored at address CA+2. (Reminder: addresses CA and CA+1 are reserved for the Message Information and Time-Tag words.) When message processing is complete, the device writes the Message Information and Time-Tag words into the buffer. If no errors were detected, the device updates descriptor CA register. If the next address location (last retrieved data word +1) is less than or equal to EA, CA is updated to (last retrieved address +1). If the next address location (last retrieved data word +1) is greater than EA, the transmit data buffer is empty; CA is updated to the SA value. If the descriptor Control Word IXEQZ bit is asserted (and if the Interrupt Enable Register IXEQZ bit is asserted) the device indicates “transmit buffer empty” by asserting the INTMES interrupt output. Circular Buffer Mode 1 does not support NOTICE2 segregation of broadcast data, even when the NOTICE2 bit equals 1 in Configuration Register 1. Data from broadcast and non-broadcast receive commands is stored in the same buffer. The BCAST bit in the Message Information Word reflects broadcast or non-broadcast status for each stored message. If broadcast messages are not expected during data block transmission, the host can illegalize broadcast commands for the subaddress. Broadcast illegalization can be done either permanently, or only when data block transmission is scheduled. For transmit subaddresses using Circular Buffer Mode 1, occurrences of broadcast-transmit commands to RT31 do not result in bus transmission. However these messages update the Message Information Word addressed by the Current Address (CA) pointer (and following Time-Tag Word) but afterwards, the CA pointer remains unchanged. The next transmit command to the same subaddress, whether broadcast or not, overwrites the Message Information and Time-Tag Word locations written by the previous broadcast transmit command. HOLT INTEGRATED CIRCUITS 87 HI-6120, HI-6121 Data Word N Data Word(s) Data Word 1 Last Message in Data Block Time-Tag Word Message Info Word More Messages in Data Block Data Word N Data Word(s) Data Word 1 End Address Current Address Start Address Control Word Descriptor Block for Subaddress Current Message Time-Tag Word Message Info Word More Messages in Data Block Data Word N Data Word(s) Data Word 1 Memory Address for the Applicable Subaddress Block is Derived From the Decoded Command Word Increasing Memory Address Time-Tag Word FirstMessage in Data Block End Address Current Address Start Message Info Word Address Assigned Subaddress Circular Buffer Descriptor block is initialized so Current Address equals buffer Start Address. After each successful message transaction, Current Address is adjusted to point past last data word accessed. If adjusted Current Address points past End Address, the Current Address is reinitialized to match Start Address and an optional interrupt is generated to notify host that the pre-determined data block was fully transacted. Figure 14. Illustration of Circular Buffer Mode 1 HOLT INTEGRATED CIRCUITS 88 HI-6120, HI-6121 Data Word 32 Data Words 2-31 Buffer End Address Data Word 1 Time-Tag Word 3 Msg Info Word 3 Data Word 32 Data Words 2-31 Data Word 1 Time-Tag Word 2 Msg Info Word 2 Data Word 32 Data Words 2-31 Data Word 1 Time-Tag Word 1 Buffer Start Address Msg Info Word 1 0x0565 0x0547 - 0x0564 0x0546 0x0545 0x0544 0x0543 0x0525 - 0x0542 0x0524 0x0523 0x0522 0x0521 0x0503 - 0x0520 0x0502 0x0501 0x0500 RAM Address (1 + Data Word 32 address) ≥ End Address. Device updates Current Address to equal the Start Address, 0x0500. IXEQZ interrupt is generated. Receive Message #3 32 Data Words (1 + Data Word 32 address) < End Address. Device updates Current Address to 0x0544. Receive Message #3 32 Data Words (1 + Data Word 32 address) < End Address. Device updates Current Address to 0x0522. Receive Message #3 32 Data Words Unless serviced by host after Message #3 Interrupt, Message #4 will overwrite buffer, starting at 0x0500 Increasing Memory Address End Address Current Address Start Address Control Word End Address = 0x0545 Buffer end address in RAM Current Address = 0x0500 Buffer current address in RAM Start Address = 0x0500 Buffer start address in RAM Control Word = 0x8001 Circular Mode 1, IXEQZ Interrupt Initialized Descriptor Values Descriptor Block for a Receive Subaddress Unlike Indexed mode, Data Block completion is based on Buffer Full / Buffer Empty, not number of messages. Buffer size was purposely sized to yield remaining capacity after 2 full-count messages, to illustrate device behavior. The circular buffer should have a 33-word pad beyond its End Address to deal with buffer overrun without data loss. Figure 15. Circular Buffer Mode 1 Example for a Receive Subaddress HOLT INTEGRATED CIRCUITS 89 HI-6120, HI-6121 11.6. Circular Buffer Mode 2 Circular Buffer Mode 2 segregates message data and message information in separate host-defined buffers. Separating data from message information simplifies the host software that loads or unloads the data to or from the buffer. After a predetermined number of messages has been transacted, buffer address pointers for data and message information are automatically reset to their base addresses. Figure 16 is a generalized illustration of Circular Buffer Mode 2, while Figure 17 shows a specific example. Circular Buffer Mode 2 is selected when the Control Word PPEN bit is zero and the CIR2EN bit is logic 1. When the CIR2EN bit is high, the CIR1EN bit is don’t care. The descriptor Control Word DPB bit is not used. Any receive subaddress using circular buffer mode 2 has two circular buffers: a data storage buffer and a message information buffer. A separate buffer pair may be used for transmit commands to the same subaddress, if it also uses circular buffer mode 2. Each transmit and receive subaddress using circular buffer mode 2 may have unique data buffer and message info buffer assignments. Careful management (involving the bus controller) may allow buffer sharing, as long as multiple message sequences to a given subaddress are not interrupted by messages to other subaddresses that use the same buffer space. When a subaddress uses circular buffer mode 2, its Descriptor Table 4-word block is defined as follows: Descriptor Word 1 Control Word Descriptor Word 2 SA (Buffer Start Address) Descriptor Word 3 CA (Buffer Current Address) Descriptor Word 4 MIBA (Message Info Buffer Addr) If Descriptor Word 1 is stored at memory address N, Descriptor Word 2 is stored at address N+1, and the other two words are stored at addresses N+2 and N+3. The first word in the descriptor block is the Control Word. The second and third words in the descriptor are the Start Address (SA) and Current Address (CA) pointers. The Message Information Buffer Address (MIBA) points to the storage location for the Message Information Word from the next occurring message. Each time a message is completed, the device writes a new Message Information Word and Time-Tag Word in the MIB (Message Information Buffer) at the MIBA address and following location, respectively. The MIBA pointer is not updated if message error occurred, if the Busy status bit was set, or if the command was illegalized (for example an illegal word count expressed in the command word.) For these situations, the Message Information and Time-Tag words are still written, but MIB updates for the following message will overwrite the just-written Message Information and Time-Tag word addresses. For error-free receive messages, received data words are stored in the data buffer after message completion, starting at the CA address value. The CA value is then updated for next-message readiness. After writing the two MIB words, the device updates the MIBA value to show the buffer address to be used by the next message. Until the predetermined number of error-free messages is transacted, the MIBA value is double-incremented at each update. Before updating the MIBA in Descriptor Word 4, the pre-existing MIBA value is incremented once then checked for ‘full count,” occurring when all N low-order address bits initialized to zero (explained below) become N “one” bits. Full count means the predetermined number of successful messages was completed. When this occurs, the CA and MIB pointers are automatically written to their initialized values by the device. To preserve data integrity, the TRXDB bit should be set in Control Register 2 to avoid storing incomplete data from messages resulting in error. With TRXDB asserted, the host is not bothered by message retries caused by errors. The Buffer Empty/Full interrupt (if enabled) is generated only upon successful transaction of the entire N-message data block. To initialize Circular Buffer Mode 2, the host must know the number of messages to be transacted, always a power of two: 1, 2, 4, 8, 16, 32, 64, 128, 256 or 512 messages. The host writes descriptor Control Word bits 7:4 with an encoded 4-bit value to set the fixed number of messages to be transacted. This is illustrated in Table 8. The host initializes the descriptor block MIBA pointer with a Message Information Buffer starting address. Because the MIB stores two words for each message, the allocated MIB space should equal 2x the number of messages. The initially-loaded MIB base address value is restricted. Some lower bits of the starting address must be zero so the device can restore the MIBA pointer to the initial MIB base address after the predetermined message count is transacted. As illustrated in Table 8, the required number of logic-0 bits depends on the message count. Initializing the MIBA base address with more trailing zeros than indicated is acceptable; initializing less trailing zeros will cause malfunction. HOLT INTEGRATED CIRCUITS 90 HI-6120, HI-6121 Allocated space in the data buffer (see column 3, Table 8) assumes each message has the maximum 32 data words. If messages contain less than 32 words, the data buffer size can be reduced. Since Circular Buffer Mode 2 counts messages, values in all remaining Table 8 columns remain valid when message word count is reduced. The host may read the MIBA value to determine the number of messages that have occurred since initialization. By reading the initially-zeroed lower bits of the MIB Address, the host may determine the number of the next occurring message. From Table 8, a block of 128 messages requires 8 trailing zeros in the initial MIBA address, for example, 0x0F00. After each message is completed, the MIBA value is updated (0x0F02, 0x0F04, etc.) The device detects message block completion when all required initially-zero trailing address bits equal 1 after MIBA is incremented once. In our example, MIBA would increment from 0x0FFE to 0x0FFF. When “full count” occurs, the device updates MIBA to the original value (e.g., 0x0F00) and copies the SA starting address value to CA current address register, ready for buffer service by the host. The device optionally generates a “buffer empty-full” interrupt for the host when block transfer is completed. During block transfer, the host can read the MIBA value to determine the number of additional messages needed before the N-message data block is complete. Message processing for all commands begins with the RT reading the unique descriptor block for the subaddress specified by the T/R bit, subaddress and word count fields in the received command word. Table 8. Circular Buffer Mode 2 (Initialization factors based on message block size) Number of Messages 2 4 8 16 32 64 128 256 512 Control Word Bits 7:4 CIR2ZN Field 0010 (2) 0011 (3) 0100 (4) 0101 (5) 0110 (6) 0111 (7) 1000 (8) 1001 (9) 1010 (A) Required Data Space if 32 Words / Msg 64 128 256 512 1,024 2,048 4,096 8,192 16,384 Required MIB Space, 2 Words / Msg 4 8 16 32 64 128 256 512 1,024 Initial MIBA Value, Showing the Required Leading and Trailing Zeros 0xxxxxxxxxxxx00 0xxxxxxxxxxx000 0xxxxxxxxxx0000 0xxxxxxxxx00000 0xxxxxxxx000000 0xxxxxxx0000000 0xxxxxx00000000 0xxxxx000000000 0xxxx0000000000 HOLT INTEGRATED CIRCUITS 91 HI-6120, HI-6121 For receive subaddresses using Circular Buffer Mode 2, the device stores received data words in the circular data buffer. The first data word received for each message is stored at the location indicated by the CA pointer. After the correct number of words is received (as specified in the command word) the device writes Message Information and Time-Tag words in the Message Information Buffer then updates the descriptor CA Current Address and MIBA Message Information pointers for next-message readiness. If the predetermined total number of messages has not yet been transacted, MIBA points to the next location in the message information buffer and CA points to the next location in the data buffer. If the completed message is the last message in the block, the CA current (data) address and MIBA message Information pointers are reinitialized to their base address values. (Control Word bits 7:4 tell the device how many MIBA lower bits to reset.) If the descriptor Control Word IXEQZ bit is asserted (and if the Interrupt Enable Register IXEQZ bit is asserted) the device generates a Buffer Full / Empty interrupt, asserting the INTMES interrupt output. For transmit subaddresses using Circular Buffer Mode 2, the device transmits data from the assigned RAM buffer, starting at the location specified by the CA pointer. The first data word transmitted is stored at the location specified by the CA pointer. After all data words are transmitted (as specified in the command word) the device writes Message Information and Time-Tag words in the Message Information Buffer then updates the descriptor CA Current Address and MIBA Message Information pointers for next-message readiness. If the predetermined total number of messages has not yet been transacted, MIBA points to the next location in the message information buffer and CA points to the next location in the data buffer. If the completed message is the last message in the block, the CA current (data) address and MIBA message Information pointers are reinitialized to their base address values. (Control Word bits 7:4 tell the device how many MIBA lower bits to reset.) If the descriptor Control Word IXEQZ bit is asserted (and if the Interrupt Enable Register IXEQZ bit is asserted) the device generates a Buffer Full / Empty interrupt, asserting the INTMES interrupt output. Circular Buffer Mode 2 does not support NOTICE2 segregation of broadcast data, even when the NOTICE2 bit equals 1 in Configuration Register 1. Data words from broadcast receive commands are stored in the same buffer with data from non-broadcast receive commands. The BCAST bit in the Message Information Word reflects broadcast or non-broadcast status for each stored message. If broadcast messages to the subaddresss are not expected during data block transmission or will result in data block error, the host can illegalize broadcast commands for the subaddress, either permanently or only when block transmission is scheduled. For transmit subaddresses using Circular Buffer Mode 2, occurrences of broadcast-transmit commands to RT31 do not result in bus transmission. However these messages update the Message Information Word addressed by the Message information Block (MIB) pointer (and the following Time-Tag Word) but afterwards, the MIB and CA pointers remain unchanged. The next transmit command to the same subaddress, whether broadcast or not, overwrites the Message Information and Time-Tag Word locations written by the previous broadcast transmit command. HOLT INTEGRATED CIRCUITS 92 HI-6120, HI-6121 Data Word N Time-Tag Word Message Info Word Last Message in Data Block Last Message in Data Block Data Word(s) Data Word 1 Increasing Memory Address Time-Tag Word Message Info Word Current Message MIB Address Current Address Start Address Time-Tag Word Message Info Word Assigned Subaddress Message Info Buffer (MIB) FirstMessage in Data Block Control Word Descriptor Block for Subaddress FirstMessage in Data Block Memory Address for the Applicable Subaddress Block is Derived From the Decoded Command Word Current Message Data Word N Data Word(s) Data Word 1 Current Address Data Word N Data Word(s) Data Word 1 Assigned Subaddress Circular Data Buffer Start Address Segregated storage for data and message information simplifies host loading / offloading of buffered data. Descriptor MIB Address tracks number of messages. Full count occurs when N initialized 0-bits become N 1-bits. When full number of messages in block is transacted, an optional interrupt is generated to notify host. Figure 16. Illustration of Circular Buffer Mode 2 HOLT INTEGRATED CIRCUITS 93 HI-6120, HI-6121 Data Word 32 Data Words 2-31 Data Word 1 Data Word 32 Time-Tag Word 4 Msg Info Word 4 Time-Tag Word 3 Msg Info Word 3 Time-Tag Word 2 Msg Info Word 2 Time-Tag Word 1 Msg Info Word 1 Message Information Buffer (MIB) 0x0607 0x0606 0x0605 0x0604 0x0603 0x0602 0x0601 0x0600 RAM Address Data Words 2-31 Data Word 1 Data Word 32 Data Words 2-31 Data Word 1 Data Word 32 Data Words 2-31 Data Word 1 Data Word Buffer 0x057F 0x0561 - 0x057E 0x0560 0x055F 0x0541 - 0x055E 0x0540 0x053F 0x0521 - 0x053E 0x0520 0x051F 0x0501 - 0x051E 0x0500 RAM Address Msg Count increments to 4, full count, data block complete. Device updates CA to equal buffer Start Address 0x0500. Device updates MIBA to equal MIB Start Address 0x0600. IXEQZ interrupt is generated. Receive Message #4 32 Data Words Msg Count increments to 3. Device updates CA to 0x0560 and updates MIBA to 0x0606. Receive Message #3 32 Data Words Msg Count increments to 2. Device updates CA to 0x0540 and updates MIBA to 0x0604. Receive Message #2 32 Data Words Msg Count increments to 1. Device updates CA to 0x0520 and updates MIBA to 0x0602. Receive Message #1 32 Data Words MIB Address Current Address Increasing Memory Address Start Address Control Word MIB Address = 0x0600 MIB start address in RAM Current Address = 0x0500 Buffer current address in RAM Start Address = 0x0500 Buffer start address in RAM Control Word = 0x8042 Circular Mode 2, 4 messages, IXEQZ Interrupt Initialized Descriptor Values Descriptor Block for a Receive Subaddress Data Block completion is based on number of messages, not Buffer Full or Buffer Empty. Example is set to successfully transact four 32 data word receive messages, then generate IXEQZ interrupt for host. The data buffer requires minimal processing by host because message information words are stored separately in MIB. Figure 17. Circular Buffer Mode 2 Example for a Receive Subaddress HOLT INTEGRATED CIRCUITS 94 HI-6120, HI-6121 12. MODE COMMAND PROCESSING 12.1. General Considerations The device provides decoding for all mode code combinations, consistent with MIL-STD-1553B requirements. Several mode command options are provided to suit any application requirement: In Configuration Register 1, the option bit UMCINV (Undefined Mode Codes Invalid) globally defines whether undefined mode code commands are treated as valid (default) or invalid commands. This bit applies only to the following 22 mode code commands that are undefined in MIL-STD-1553B: Mode Codes 0 through 15 with T/R bit = 0 Mode Codes16, 18 and19 withT/R bit = 0 Mode Codes 17, 20 and 21 with T/R bit = 1 If the UMCINV bit is low (default after MR reset) undefined mode code commands are considered valid and RT response is based on individual mode command settings in the Illegalization Table: If the command’s table bit equals 0, the mode command is legal; the RT responds “in form” and updates status. If the command’s table bit equals 1 the mode command is illegal, the RT asserts Message Error status and (if non-broadcast) transmits only its Status Word without associated data word. Table 9 describes explicit terminal response for each mode code value and command T/R bit state, based on various option settings. If UMCINV is asserted, the 22 undefined mode code commands are treated as invalid: There is no terminal recognition of the command. No command response occurs and status remains unchanged for the benefit of following “transmit status” or “transmit last command” mode commands. If UMCINV is low, the device determines legal vs. illegal status of commands from the Illegalization Table. If the terminal does not use illegal command detection, the Illegalization Table should be left in its post-reset default state, all values equal logic 0. In this case, the terminal provides “in form” response to all valid commands. The terminal responds with clear status and a transmitted mode data word for mode commands 16-31 with T/R bit equals 1. Assigned data buffer locations can be initialized to provide predictable “in form” responses for all transmit mode codes 16-31. (If UMCINV is asserted, the terminal will not respond or update status for received mode codes 17, 20 and 21 with T/R = 1.) To use illegal command detection, the host modifies the Illegalization Table to make illegal any combination subaddress and mode code commands. This may include undefined mode codes, reserved mode codes, and/or mode codes not implemented in the application. Note: Mode command MC0 “dynamic bus control” cannot be implemented in the device since the HI-6120/21 cannot act as a Bus Controller. Therefore, the “dynamic bus control acceptance” status bit cannot be set in the outgoing status word from this device. 12.2. Mode Command Interrupts For mode commands, interrupt generation is programmed by the top three bits in the descriptor table Control Word. Notice that broadcast-transmit interrupts can be enabled for mode code values in the range of 0 - 15, but broadcast-transmit mode codes 16 - 31 are not allowed. When a mode command is received and the IWA interrupt bit is asserted in its descriptor Control Word, that command will generate a host interrupt if the IWA bit is high in the Interrupt Enable Register. The IWA bit is asserted in the Pending Interrupt Register and the INTMES interrupt output is asserted. Before INTMES interrupt assertion, the device updates the Interrupt Log buffer, writing a new IIW Interrupt Information Word and a new IAW Interrupt Address Word. The IWA (interrupt when accessed) bit is asserted in the new IIW to indicate interrupt type. The IAW contains the Descriptor Table address for the mode command’s Control Word, based on mode code value and command word T/R bit state. The host reads the IAW to determine the command that caused the interrupt. 12.3. Mode Command Data Words Mode commands having mode code values from 0 through 15 (decimal) do not have an associated data word. These are received as Command Word only, never having a contiguous data word. The terminal response to valid mode commands 0-15 always consists of Status Word only, assuming command was not broadcast. Mode commands having mode code values from 16 through 31 (decimal) always have an associated data word. When the command word T/R bit equals 0, the terminal receives a data word, contiguously following the Command Word. When valid legal mode commands 1631 arrive with T/R bit equal to 1, the terminal responds by transmitting its status word with a single data word. When the SMCP option bit in Configuration register 1 is zero, individual data words for mode codes 16-31 decimal are stored in an indexed or ping-pong buffer assigned by the mode command’s Descriptor Table entry. HOLT INTEGRATED CIRCUITS 95 HI-6120, HI-6121 Circular buffer methods are not available for mode code commands. When the SMCP option bit in Configuration register 1 is asserted, individual data words for mode codes 16-31 decimal are stored within the Descriptor Table itself. This is explained next. Table 9. Mode Code Command Summary Command T/R bit 0 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 Mode Code Binary 00000 to 01111 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 to 01111 10000 10000 10001 10001 10010 10010 10011 10011 10100 10100 10101 Dec. 0 to 15 0 1 2 3 4 5 6 7 8 9 to 15 16 16 17 17 18 18 19 19 20 20 21 MIL-STD-1553 Defined Function Undefined mode commands 0 - 15 when T/R bit = 0 Dynamic Bus Control Synchronize (without data) Transmit Status Word Initiate Self-Test Transmitter Shutdown Override Transmitter Shutdown Inhibit Terminal Flag Override Inhibit Terminal Flag Reset Remote Terminal Reserved Mode Commands 9 - 15 with T/R bit = 1 Undefined Mode Command Transmit Vector Word Synchronize With Data Undefined Mode Command Undefined Mode Command Transmit Last Command Undefined Mode Command Transmit Built-In Test Word Selected Transmitter Shutdown Undefined Mode Command Override Selected Transmitter Shutdown Associated Data Word No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Broadcast Allowed No No Yes No Yes Yes Yes Yes Yes Yes Yes No No Yes No No No No No Yes No Yes (1) (1) (1) (1) (2) (1) See Note (1) (3) HOLT INTEGRATED CIRCUITS 96 HI-6120, HI-6121 Command T/R bit 1 0 Mode Code Binary 10101 01001 to 01111 01001 to 01111 Dec. 21 22 to 31 22 to 31 MIL-STD-1553 Defined Function Undefined Mode Command Reserved Mode Commands 22 - 31 with T/R bit = 0 Reserved Mode Commands 22 - 31 with T/R bit = 1 Associated Data Word Yes Yes Broadcast Allowed No Yes See Note (1) (2) 1 NOTES: Yes No (2) 1. The 22 undefined mode commands can be rendered invalid by setting the UMCINV (undefined mode codes invalid) option bit in Configuration Register1. If UMCINV is asserted, there is no recognition of the undefined command by the terminal. If UMCINV is zero, the commands are considered valid. Terminal response when UMCINV equals 0 is wholly determined by the Illegalization Table: a. If a command’s bit in the Illegalization Table equals zero, the terminal responds “in form” with Clear Status. Mode commands 17, 20 and 21 are undefined when T/R bit equals one, but will transmit a contiguous data word. Mode commands 16, 18 or 19 are undefined when T/R bit equals 0, but will receive a contiguous data word. b. If a command’s bit in the Illegalization Table equals one, the command is considered illegal. The Message Error (ME) status bit is asserted and the terminal transmits status without data word. Illegal mode commands 16-31 will not transmit or receive a mode data word. 2. Response to the reserved mode commands is fully defined by Illegalization Table settings. As described in (a) and (b) above, the terminal illegalizes any reserved mode command having Illegalization Table bit equal to 1, and responds “in form” when the Table bit equals zero. The “in form” response for reserved mode commands 16 through 31 transacts a received or transmitted data word. 3. HI-6120/21 cannot fulfill Bus Control duties. HOLT INTEGRATED CIRCUITS 97 HI-6120, HI-6121 12.4. Standard Mode Command Processing Data buffer options for mode commands differ from buffer options for subaddress commands. Mode commands can use ping-pong buffering or indexed buffering. When mode commands use indexed buffers, “single message mode” (INDX = 0) is recommended. When using indexed or ping-pong buffers for mode commands: • For mode commands without associated data word (mode codes 0-15 decimal), only the Message Information and Time-Tag words are updated in the mode command’s assigned data buffer in RAM. For mode commands 16-31 (decimal) that receive a data word, indexed and ping-pong buffer methods copy the received mode data word to the mode command’s assigned data buffer in shared RAM, after the message is transacted. The Message Information and Time-Tag words are also updated. For most mode commands 16-31 (decimal) that transmit a data word, the device reads the data word for transmit from the buffer location assigned in the Descriptor Table. Exceptions occur for MC18 “transmit last command” and for MC19 “transmit BIT word.” The MC18 data word is automatically provided by the device, based on recent command transactions. The MC19 data word comes from register 0x14 or 0x15, depending on the state of the ALTBITW option in Configuration Register 2. For both MC18 and MC19, the transmitted data word is automatically recorded in the mode command’s assigned data buffer in RAM, after message completion. The Message Information and Time-Tag words are also updated. Descriptor Word 1 Mode Command Control Word Descriptor Word 2 Message Information Word Descriptor Word 3 Time-Tag Word Descriptor Word 4 Mode Data Word Descriptor Word 1 contains the receive or transmit mode command Control Word. When SMCP is used, just two Control Word bits are used: DBAC (descriptor block accessed) and BCAST (broadcast). When SMCP is enabled, the host need not initialize the mode code command segments in the Descriptor Table. When Simplified Mode Command Processing is selected, the host does not write Descriptor Words 2-3 in the Descriptor Table entries for mode commands. For mode code values 0 to 15 decimal, the Descriptor Word 4 serves no function because these mode codes do not have an associated data word. For transmit mode code values 16 to 31, the host may initialize Descriptor Word 4. The default transmit value is 0x0000. Mode command MC16 “transmit vector word” is one of the three defined mode commands that transmit a data word: MC16, MC18 and MC19. Its Descriptor Word 4 should be initialized if a value other than 0x0000 is needed. MC18 and MC19 are discussed below. • For mode commands without associated data word (mode codes 0-15 decimal), Simplified Mode Command Processing updates the Message Information and Time-Tag words in Descriptor Words 2 and 3, and Descriptor Word 1 (bits 9,11). For these commands, SMCP does not update Descriptor Word 4, which may be non-zero if written earlier by the host. For receive mode commands 16-31 (decimal) that receive a data word, Simplified Mode Command Processing copies the received mode data word to Descriptor Word 4. The Message Information and Time-Tag words in Descriptor Words 2 and 3, and Descriptor Word 1 (bits 9, 11) are also updated. For most transmit mode codes 16-31 (decimal), the device reads the data word for transmission from each command’s Descriptor Word 4. Exceptions occur for MC18 “transmit last command” and for MC19 “transmit built-in test word”. The MC18 data word is automatically provided, based on the last command transacted. The MC19 data word comes from register 0x14 or 0x15, depending on the state of the ALTBITW option in Configuration Register 2. For MC18 and MC19, the transmitted data value is automatically copied to the mode command’s Descriptor Word 4 after message completion. The Message Information and Time-Tag words in • • 12.5. Simplified Mode Command Processing Mode commands have a buffer alternative that is unavailable for subaddress commands. The SMCP bit in Configuration Register 1 selects Simplified Mode Command Processing, a global option applying to all mode commands. When the SMCP bit is high, mode command descriptor blocks (in the Descriptor Table) do not contain data pointers to reserved buffers elsewhere in the shared RAM. Instead, each 4-word descriptor block itself contains the message information word, the timetag word and the data from the most recent occurrence of each mode command: • • HOLT INTEGRATED CIRCUITS 98 HI-6120, HI-6121 Descriptor Words 2 and 3, and Descriptor Word 1 (bits 9, 11) are also updated. Section 16 Appendix shows terminal response to all possible subaddress and mode code command combinations. The table summarizes terminal response for the full range of message conditions, including errors, incomplete messages, etc. The table explicitly describes terminal response and impact on terminal Status Word, Descriptor Control Words and data buffer Message Information Words. The table includes effects for all pertinent setup options and identifies all interrupt options available. Bold text blocks indicate error-free messages or “in form” Clear Status responses when the terminal is not using “illegal command detection”. 13.2. Host Interrupt Generation Interrupts are output signals notifying the host when predetermined events have occurred during terminal operation; the interrupt-causing events are fully programmable. The host defines message-specific interruptcausing events when initializing the Descriptor Table. Other hardware-based interrupts are configured when internal device registers are initialized. To manage host interrupts, the device architecture involves an Interrupt Log buffer, three control registers, two interrupt output pins and two interrupt acknowledge input pins. The three internal registers are the Pending Interrupt Register, the Interrupt Enable Register and the Interrupt Log Address Register. The Pending Interrupt Register contains information identifying events programmed by the host to generate interrupts. The Interrupt Enable register lets the host enable or disable interrupt generation for different interrupt-causing events. The Interrupt Log Buffer is a 32-word ring buffer located in shared RAM address range 0x0040 to 0x005F. Separate interrupt outputs are provided for hardware interrupts (INTHW) and message interrupts (INTMES). The host programs both pins as either pulsed interrupt outputs or level-sensitive outputs, by writing the INTSEL bit in Configuration Register 1. The states are summarized in Table 10. 13. INTERRUPT MANAGEMENT 13.1. Host Message Detection Options Upon receiving messages, the host has several options. The individual descriptor table Control Words have enable flags for generating interrupts. Interrupts can be enabled on a subaddress or mode code basis. For any subaddress, interrupts can be enabled for (a) every command occurrence, (b) upon occurrence of broadcast commands, (c) at end of multiple message block transfers (index mode or circular buffer modes only), or (d) no interrupts at all. Some subaddress commands may not require immediate host servicing. If the number of legal subaddresses is small, the host can poll descriptor table Control Words for the legal subaddresses to detect message activity. The Control Word’s DBAC bit (descriptor block accessed) is set whenever a message is processed. This bit is automatically reset by any host read cycle to the descriptor Control Word. Whenever the DBAC bit reads high, the subaddress transacted a message since the last Control Word read cycle. Another interrupt alternative that works for any number of legal subaddresses (or when illegal command detection is not used) is to poll the device ACTIVE pin. This pin is high whenever a command is being processed. After the ACTIVE pin goes low, the host can read the Current Command Register to determine the processed command word, or may fetch the command’s descriptor table address from the Current Control Word Address register. Both registers maintain their loaded values until the next valid command to the terminal is decoded. Table 10. Summary of Interrupt Outputs. Config. Register 1 Bit INTSEL 0 1 Interrupt Output Pins INTHW INTMES Pulsed Output Active Low Level Output Active Low Interrupt Acknowledge Input Pins ACKHW ACKMES The ACK pins are not used Active High (Internal pull-downs) Pulsed outputs have brief (~250ns) duration, sufficient to drive edge-triggered host inputs. In the level mode of operation, asserted interrupts remain low until acknowledged by the host. There are two ways the host can acknowledge level interrupts: (1) assert the ACKHW or ACKMES input pin to clear the respective interrupt INTHW or INTMES output, or (2) read the Pending Interrupt Register to clear both INTHW and INTMES output pins to the high state. Assertion of the INTHW interrupt indicates an interruptcausing hardware event that is enabled in the Interrupt HOLT INTEGRATED CIRCUITS 99 HI-6120, HI-6121 Enable Register. Defined interrupt-causing events are listed in Table 11. When the INTHW output is asserted, one or more bits are set in the Pending Interrupt Register, to identify the interrrupt event(s). Assertion of the INTMES interrupt after a message is completed indicates a predetermined message event occurred that is (1) globally enabled in the Interrupt Enable Register and (2) specifically enabled for the last command transacted. The Descriptor Table Control Word for each command is programmed by the host to enable events that generate message interrupts. The type of INTMES event is reflected in the IXEQZ, IWA, IBR, ILCMD and MERR bits within the Pending Interrupt Register. The interrupt architecture maintains information for the last 16 interrupts in a 32-word ring buffer. The device automatically handles interrupt-logging overhead. Each interrupt generates two words of information to help the host perform interrupt processing. The Interrupt Identification Word (IIW) identifies the type(s) of interrupt that occurred. The Interrupt Address Word (IAW) identifies the interrupt source (e.g., subaddress Descriptor Block) using a 16-bit address. Table 11. Interrupt Identification Word IIW - Interrupt Identification Word Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt IXEQZ IWA IBR --------------MERR -------ILCMD SPIFAIL LBFA LBFB TTINT1 TTINT0 RTAPF EECKF RAMIF Origin Message Message Message --------------Message -------Message Hardware Hardware Hardware Hardware Hardware Hardware Hardware Hardware IAW contains 0x0000 IAW contains the Command Word Descriptor Table Address IAW - Interrupt Address Word 13.2.1. Interrupt Log Address Register Bits 7:0 in this register indicate the IIW storage address within the buffer for the next occurring interrupt, 0x0040 to 0x005E. Bits 15:8 indicate the number of interrupts since the register was last read. For further details, see the full description of the Interrupt Log Address Register. 13.2.2. Interrupt Address Word (IAW) Stored in the Interrupt Log Buffer, Interrupt Address Words (IAW) identify interrupt-causing messages by storing the descriptor block address for the subaddress or mode code command that generated each message interrupt. 13.2.3. Interrupt Identification Word (IIW) Stored in the Interrupt Log Buffer, Interrupt Identification Words identify type of interrupt event. Bit assignments match those used in the Pending Interrupt Register. The host or subsystem reads the IIW to determine which type of interrupt occurred. The Interrupt Identification Word is defined in Table 11. HOLT INTEGRATED CIRCUITS 100 HI-6120, HI-6121 14. RESET AND INITIALIZATION This section describes the hardware and software reset mechanisms. Hardware Master Reset returns the device to the uninitialized state, requiring register/RAM initialization before terminal execution can begin. Initialization can be performed by the host after MR reset, or automatically, at the user’s option, by reading configuration data from an external serial EEPROM. Software reset is asserted by setting the SRST bit in Configuration Register 1. Software reset has minimal effect on previously initialized registers and RAM structures that define terminal behavior. However some reinitialization may be needed for some applications, after SRST reset is complete. a. The device asserts the READY output pin. This state change indicates the host can begin postMR reset initialization of registers and RAM structures. b. Upon READY assertion, the host should initialize configuration and option registers, the Descriptor Table(s) and the Illegalization Table. Initialization may include data written into the various transmit subaddress buffers assigned by the initialized Descriptor Table. c. After the host completes initialization, it must assert the STEX (start execution) bit in Configuration Register 1 to begin Remote Terminal operation. 14.1. Master Reset using the MR pin and Optional Auto-Initialization Hardware master reset is initiated by a low to high transition on the MR pin; it should be applied after power-up, but may be used anytime afterward. When asserted, the MR input pin causes immediate, unconditional hardware reset. Command processing is terminated, the bus decoders and encoder are cleared, the Time-Tag count is reset. The Message Error, Busy and Broadcast Command Received status bits are reset and Terminal Flag bit is enabled for assertion. All internal logic is cleared. Registers and RAM structures are restored to the states shown in Table 12. The READY, ACTIVE, INTMES and INTHW output pins are negated if previously asserted. After MR pin low to high transition, these steps occur: 1. After 200ns, the states of the following input pins are latched into the Operational Status register: RTA4RTA0, RTAP, AUTOEN, LOCK and INTSEL. Before READY assertion, a host read cycle to any address returns the value in the Operational Status register. 2. If the MTSTOFF pin is logic zero, the device performs a memory test (< 985us). If memory error occurs, the BMTF bit is set in the BIT Word Register 0x0014. If the MTSTOFF pin is logic one, the memory test is bypassed. This option might be chosen if a faster reset process is needed. Regardless of MTSTOFF state, all RAM locations above address 0x001F are cleared to 0x0000. 3. After internal processes are initialized, the device checks the latched state of the AUTOEN bit in the Operational Status register: If the Operational Status register AUTOEN bit reads low, auto-initialization is bypassed. The host must initialize the terminal as follows: If the Operational Status register AUTOEN bit reads high, the device initializes itself from an external serial EEPROM via the dedicated EEPROM SPI port: The READY output pin remains low while automatic self-initialization proceeds. The device reads initialization data from the external serial EEPROM memory, using the dedicated EEPROM SPI port. Initialization includes all registers, all tables (including secondary Descriptor Tables, if used) and can include initial data written to transmit subaddress data buffers allocated by the Descriptor Table. If the EE1K pin is low, initialization covers the full 32K address range 0x0 to 0x7FFF, including the entire RAM. Therefore it can initialize secondary Descriptor Tables and transmit subaddress buffers in the upper RAM space. (Note: Typical auto-initialization time is 63ms). If the EE1K pin is high, initialization covers just the 1K address range 0x0 to 0x003F. This covers all registers and the minimum set of required tables, including the default Descriptor Table from 0x00200 to 0x003FF. For many applications, this is the only Descriptor Table. (Note: Typical autoinitialization time is 1.97ms). During auto-initialization, the written value for each register or RAM location is read back for confirmation. If the read-back value does not match the corresponding value from EEPROM, an initialization error is saved. This error results in action (described below) that occurs when the initialization process is finished. While performing initialization, a running checksum is tallied as follows, using EEPROM data read from the 1K or 32K address range. A properly configured serial EEPROM contains a 16-bit checksum value stored at the pair of EEPROM locations correspond- HOLT INTEGRATED CIRCUITS 101 HI-6120, HI-6121 ing to RAM address 0x0020. The stored checksum is tallied as if RAM address 0x0020 equals 0x0000 and five registers are excluded from checksum computation: Operational Status register 0x0002, Pending Interrupt register 0x0006, Time-Tag register 0x0008 and BIT Word register 0x0014. The stored value is actually the twos-complement of the 16-bit memory checksum, (CHECKSUM + 1). During initialization, byte pairs are sequentially read from EEPROM, then merged to a 16-bit value that is both written to device RAM (or register) and added (running tally) to the twos-complemented checksum value. When the full 1K or 32K EEPROM range is tallied, the running checksum tally should equal zero, indicating error-free checksum tally. After initialization (at READY assertion), the 16-bit twoscomplement checksum value is copied from EEPROM to device RAM address 0x0020. This is part of the Temporary Receive Data Buffer, which does not interfere with terminal initialization. When the device completes auto-initialization, the READY output pin is asserted to the high state. If an initialization error occurred, the following events take place immediately after READY assertion: 1. The INTHW interrupt output pin is asserted. 2. The Operational Status Register 0x0002 is written to indicate the type of error. The EECKF or RAMIF bit is set to show checksum failure or read-back data mismatch between RAM and EEPROM. 3. The EELF bit is set in the Built-In Test Word Register 0x0014. 4. If RAMIF read-back error occurred, the address of the first occurring instance is written to register address 0x001F. Additional locations beyond the saved address may have mismatch, but only the first instance is logged. The STEX bit in Configuration Register 1 is still zero. If the STEX bit in the initialization EEPROM is high, and if the EECKF, RAMIF and RTAPF bits are reset in the Operational Status Register 0x0002, the device now sets the STEX bit to start Remote Terminal operation. This means: (1) auto-initialization was error-free and (2) the RT address in Operational Status Register bits 15-10 has correct parity. The register’s terminal address bits reflect input pin states if the LOCK pin is high, or were overwritten by values from the initialization EEPROM, if the LOCK pin is low. If automatic STEX assertion was blocked because EECKF or RAMIF bits were written high after READY assertion, the host can write STEX high, overriding the error condition. If STEX assertion was blocked because of RT address parity error, the STEX bit cannot be asserted until the parity error is corrected. The host may overwrite the Operational Status Register RTAP4-0 and RTAP bits to correct the error, then assert the STEX bit in Configuration Register 1. If the STEX bit in the initialization EEPROM is low, the STEX bit in Configuration Register 1 is not asserted at this time. The device awaits STEX assertion by a host write to Configuration Register 1 before starting Remote Terminal operation. The STEX bit may be written any time after the READY output pin goes high. After any MR master reset, the state of certain input pins (AUTOEN, LOCK and terminal address pins RTA4 to RTA0 and RTAP) are latched into Operational Status Register 0x0002. Because auto-initialization follows master reset, the mirrored pin states may be overwritten by the values stored in the initialization EEPROM bytes corresponding to register address 0x0002, only if the LOCK input pin is low. A method for programming the EEPROM itself from a fully configured terminal is explained in a following section entitled “Serial EEPROM Programming Utility”. If a different method is used for writing the serial EEPROM, the twos-complemented checksum (described earlier) must be saved in EEPROM locations corresponding to device RAM address 0x0020. A compatible serial EEPROM uses a SPI interface for byte-access read and write operations. Sixteen-bit register and RAM values in the HI-612X are stored as upper and lower bytes in the EEPROM, in “big endian” fashion. For example, the upper byte for register address 0x0000 is stored at EEPROM address 0x0000 while the lower byte is stored at EEPROM address 0x0001. A 64K x 8 EEPROM is required to store the entire 32K x 16 address range. Serial EEPROM data mapping follows the device memory map shown in Figure 2. The single exception: two EEPROM locations corresponding to device RAM address 0x0020 must contain the expected checksum value. The serial EEPROM used for auto-initialization should be fully written to cover the HI-6120/21 upper address limit of 0x7FFF (or 0x03FF, depending on the state of the EE1K input pin). Ideally the EEPROM image will reflect a post-MR reset followed by fresh initialization with nothing written to reset-cleared registers or RAM as a result of command processing. HOLT INTEGRATED CIRCUITS 102 HI-6120, HI-6121 Table 12. Summary of Changes Due to MR Master Reset or SRST Software Reset Hex Address 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B-0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x0020-0x001F Device Register Configuration Register 1 Configuration Register 2 Operational Status Register Current Command Register Current Control Word Address Register Descriptor Table Base Address Register Pending Interrupt Register 1553 Status Word Bits Register Time-Tag Register Interrupt Log Address Register Current Message Information Word Register Reserved Memory Address Pointer (HI-6121 Only) Interrupt Enable Register Time-Tag Utility Register Bus A Select Register Bus B Select Register Built-In Test (BIT) Word Register Alternate BIT Word Register Test Control Register BIST Control Register Loopback Test Transmit Data Register Loopback Test Receive Data Register Reserved Contents after MR Reset 0x0000 0x0000 bits 7:0 reset to 0x00 bits 15:8 match pins 0x0000 0x0000 0x0200 0x0000 0x0000 0x0000 0x0040 0x0000 0x0000 0x0000 0x0007 0x0000 0x0000 0x0000 See Note 1 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Contents after SRST Reset no change no change no change no change no change 0x0200 no change 0x0000 0x0000 no change no change no change no change no change no change no change no change 0x0000 no change 0x0000 0x0000 0x0000 0x0000 no change HOLT INTEGRATED CIRCUITS 103 HI-6120, HI-6121 Contents after MR Reset all 0x0000 all 0x0000 all 0x0000 all 0x0000 all 0x0000 all 0x0000 all 0x0000 Contents after SRST Reset no change no change no change no change See Note 2 no change no change Contents after SRST Reset reset reset reset reset overridden overridden set negated (high) Hex Address 0x0020-0x003F 0x0040-0x005F 0x0060-0x00FF 0x0100-0x01FF 0x0200-0x03FF 0x0400-0x7FFF RAM Structure Temporary Receive Data Buffer, 32 Words Interrupt Log Buffer, 32 Words Unallocated RAM, 160 Words Illegalization Table, 256 Words Descriptor Table (Primary), 512 Words Host-Assigned Data Buffers Secondary Descriptor Tables, if used Terminal Function Hardware Bus Decoders Hardware Encoders and Transmitters Command Processing & ACTIVE Output Terminal Status (incl ME & BCR bits) Prior Bus Shutdown by Mode Cmd MC4 or MC20 Prior Terminal Flag Inhibit by Mode Cmd MC6 READY Output INTMES & INTHW Interrupt Outputs NOTES: Contents after MR Reset reset reset reset reset overridden overridden reset negated (high) 1. After Master Reset, bits 15, 14 and 2 in the BIT Word Register depend on input pin settings. See register description. If the MTSTOFF input pin is low, register bit 3 (BMTF) depends on memory test outcome. The remaining bits are unconditionally reset. However if auto-initialization is enabled and EEPROM load failure occurs during the subsequent initialization process, register bit 1 (EELF) will be set. 2. Upon SRST reset, the DBAC, DPB, MKBUSY and BCAST bits are reset for each of the 128 Control Words in the primary Descriptor Table which starts at address 0x0200. If secondary Descriptor Tables are used (above address 0x0400), the host must perform any necessary table reconfiguration after SRST reset. HOLT INTEGRATED CIRCUITS 104 HI-6120, HI-6121 14.2. Software Reset Software reset is initiated by a host write that sets the SRST bit in Configuration Register 1. This bit is set automatically when a “Reset Remote Terminal” mode command is received while the MCOPT0 bit is set in Configuration Register 2 (0x0002). Software reset causes immediate reset without overwriting registers or tables that were initialized by the host to define terminal behavior. Changes to registers and RAM are summarized in Table 12. Software reset cannot initiate automatic selfinitialization from serial EEPROM. Once the SRST bit in Configuration Register 1 is asserted, the following steps are performed: 1. The READY, ACTIVE, INTMES and INTHW output pins are negated. Terminal execution stops while SRST reset is underway. Command processing is terminated. The hardware bus decoders and hardware encoder are cleared. The Message Error and Broadcast Command Received flags in the internal status register used for MC2 or MC18 mode command responses are not affected by SRST. 2. The Descriptor Base Address register (0x0005) is reinitialized to the base address 0x0200. The following registers are cleared: the 1553 Status Word Bits register (0x0007), the Time-Tag register (0x0008) and test registers 0x0016 to 0x0019. 3. The BIT Word Register (0x0014) is cleared, except the contained RTAPF bit is not changed. This reinstates any bus previously shutdown by mode code commands MC4 or MC20 (decimal). If the Terminal Flag status bit was previously inhibited by mode command MC6, inhibit is cleared: The Terminal Flag status bit will be transmitted whenever bit 0 is set in the 1553 Status Word Bits Register. 4. All 128 descriptor table Control Words are modified to reset the DBAC, DPB, MKBUSY and BCAST bits. Subaddresses or mode codes using ping-pong or single message index mode (INDX = 0) are ready for immediate operation after SRST reset is complete. However the device cannot reinitialize the Descriptor Table to restore multi-message block transfers, for indexed buffer mode when initial INDX value was non-zero, or for either circular buffer mode. 5. The device asserts the READY output pin. Terminal operation automatically resumes if the STEX bit in Configuration Register 1 was set before SRST occurred. 6. After READY assertion, the host may reset STEX, then reinitialize all or part of the Descriptor Table. The host can reinitialize the Descriptor Table for subaddresses using multi-message block transfers (Circular Buffer Mode 1, Circular Buffer Mode 2 or Indexed Buffer Mode with initial non-zero INDX.) The host can also reinitialize transmit data in the assigned transmit subaddress data buffers. Data buffers in RAM contain data values loaded before SRST occurred. The host can clear or overwrite this old data. The host can then assert the STEX bit in Configuration Register 1 to restart terminal operation. 14.3. Reset Remote Terminal Mode Code Mode code MC8 with T/R bit = 1 should reset the Remote Terminal. After Status Word transmission, the device automatically resets the status Message Error (ME) and Broadcast Command received (BCR) bits in its internal status register. Bits 0, 14 and 15 are reset in the BIT Word register at address 0x0014. If either transmitter was shutdown by a previous mode code MC4 or MC20, the shutdown condition is overridden. If the Terminal Flag (TF) status bit was inhibited, the inhibit is reset. This command does not reset any of the hostprogrammed registers that configure the terminal for operation. To complete the reset process, the host must assert either MR master reset (with or without auto-initialization) or assert the SRST bit in Configuration Register 1 to execute software reset. Since MC8 requires host interaction, most applications will probably utilize the IWA interrupt to alert the host when valid MC8 is received. Per MIL-STD-1553B appendix 30.4.3, any reset initiated by the “Reset Remote Terminal” mode command should be completed within 5 ms following transmission of the Status Word. Overall reset time includes internal device initialization, either host initialization or auto-initialization. Overall time to complete reset initiated by the “Reset Remote Terminal” mode command MC8 is affected by host response speed and application complexity. 14.4. Serial EEPROM Programming Utility The HI-6120 or HI-6121 can program a serial EEPROM via the dedicated EEPROM SPI port for subsequent auto-initialization events. The device copies host-configured registers and RAM (configuration tables and possibly data buffers) to serial EEPROM. Compatible SPI serial EEPROMs are 3.3V, operate in SPI modes 1 or 3 and and have 128-byte pages. The serial SPI data is clocked at 8.3 MHz SCK frequency. A 2K x 8 EEPROM can restore the lower 1K x 16 device address space. A 64K x 8 EEPROM can restore the entire 32K x 16 device address space. HOLT INTEGRATED CIRCUITS 105 HI-6120, HI-6121 A deliberate series of events initiates copy of data from HI-6120 or HI-6121 to serial EEPROM. This reduces the likelihood of accidental EEPROM overwrites. This series of events must occur to initiate programming: 1. If using a fresh host initialization immediately following MR master reset as the basis for EEPROM copy: With the AUTOEN, TXINHA and TXINHB pins in logic zero state, apply MR master reset and wait for READY output assertion. Verify that the INTHW output does not pulse low at READY assertion, indicating likely RT address parity error at the RTA4:0 and RTAP pins. Using known good parameters, the host initializes device registers, the RAM descriptor table and transmit data buffers (if necessary). Do not assert STEX. Go to step 3. OR 2. If using the existing EEPROM configuration as the baseline for a new EEPROM configuration: With the AUTOEN pin in logic 1 state and the TXINHA and TXINHB pins in logic zero state, apply MR master reset and wait for READY output assertion. Verify that the INTHW output does not pulse low (or go and remain low) at READY assertion. Confirm that the RTAPF, EECKF and RAMIF bits are all logic 0 in the Operational Status Register 0x0002. If the STEX bit in Configuration Register 1 was set by auto-initialization, reset it now. Modify register and RAM values to reflect the new changes. Go to Step 3. 3. IMPORTANT: Any processing of valid bus commands between MR master reset and this point will cause auto-initialization checksum failure later, due to non-zero values written to read-only registers as a result of command processing. The device will not enter EEPROM copy mode at step 4 if valid command reception caused ACTIVE output assertion after MR reset occurred. If set, the STEX bit in Configuration Register 1 also locks-out EEPROM copy mode at programming step 4. 4. The host writes one of two 2-part “unlock codes” to RAM address 0x0020. The two unlock codes perform identical EEPROM programming with the exception of the programmed state for the STEX bit in Configuration Register 1. If auto-initialize should program Configuration Register 1 STEX bit to logic 0, RAM address 0x0020 is first written 0xA5F0, then a second load to 0x0020 overwrites the value just written with 0x5F0A. If auto-initialize should program Configuration Register 1 STEX bit to logic 1, RAM address 0x0020 is first written 0x5A0F, then a second load to 0x0020 overwrites the value just written with 0xA0F5. In either case, the two unlock writes must occur without intervening access to other device addresses, except Memory Address Pointer 0x000F for HI6121. 5. The EECOPY input pin is driven high for at least 1 ms, then driven low. In response, the READY output goes low while EEPROM memory is written. Programming commences. The unlock code at address 0x0020 is cleared, then device register and RAM contents are written to the serial EEPROM. During programming, the twos-complemented checksum is tallied for the entire address range being programmed (1K or 32K words), excluding addresses 0x0002, 0x0006, 0x0008, 0x0014 and 0x0020. At EEPROM programming completion, the final checksum is stored in the pair of EEPROM locations corresponding to device RAM address 0x0020. The value written to EEPROM is actually the twos-complement of the memory checksum, (CHECKSUM + 1). The value in EEPROM is used for error detection when performing auto-initialization. (The host can only access the stored value immediately after an auto-initialization sequence is performed. The twoscomplement EEPROM checksum value will be copied into RAM address 0x0020.) 6. When the READY output goes high, EEPROM copy is complete. The STEX bit is reset in device Configuration Register 1. 7. The address range copied during EEPROM programming depends on the state of the EE1K input pin when rising edge occurs on the EECOPY input: If EE1K is high when EECOPY is asserted, the lower 1K x 16 address range from 0x0 to 0x03FF is copied from device registers and RAM to EEPROM. This includes all registers, all configuration tables in RAM and the primary Descriptor Table in RAM at address 0x0200 to 0x03FF. The 1K x 16 write to EEPROM requires up to 83 ms. If EE1K is low when EECOPY is asserted, the entire 32K x 16 address range from 0x0 to 0x7FFF is copied from device registers and RAM to EEPROM. This range covers all registers, all configuration tables in RAM, the primary Descriptor Table in RAM at address 0x0200 to 0x03FF. As long as EE1K remains low when auto-initialization occurs, the 32K x 16 programming option can initialize secondary Descriptor Tables above address 0x0400, if used. The 32K x 16 write to EEPROM requires up to 2.64 seconds. HOLT INTEGRATED CIRCUITS 106 HI-6120, HI-6121 The 32K x 16 programming option (EE1K equals zero) can also initialize fixed data for any subset of the 32 possible transmit subaddress buffers, using any of the defined data buffer schemes. To enable EEPROM copy for transmit subaddress data buffers, the buffer space must be pre-loaded with the desired data. Be sure to reserve space for Message Information and Time-Tag Word locations, as required for the transmit subaddress buffer method. ured for 8-bit width, that is, when BWID equals 0. When BENDI is low, “little endian” is chosen; the low order byte (bits 7:0) is transacted before the high order byte (bits 15:8). When BENDI is high, “big endian” is chosen and the high order byte is transacted on the host bus before the low order byte. In 8-bit mode, all transacted data uses bus data bits 7:0 and bus data bits 15:8 are not used. Further, bus address bit A0 (LB) always equals 0 during the first byte read/write access, and equals 1 during the second byte access When the BWID pin is connected high or left unconnected, 16-bit bus width is used. For 16-bit bus operation, the A0 (LB) address pin is not used and the BENDI input pin is “don’t care.” 15. HOST INTERFACE 15.1. HI-6120 Host Bus Interface The HI-6120 uses a parallel bus interface for communications with the host. Host interface to registers and RAM is enabled through the Chip Enable (CE) pin, and accessed via 16-bit data bus and several host-originated control signals described below. Timing is identical for register operations and RAM operations via the host bus interface, but read and write operations have different signal timing. The HI-6120 parallel host bus interface is capable of faster communication than the HI-6121 Serial Peripheral Interface. Depending on the chosen microprocessor family, the processor’s hardware bus interface may be described as an “external bus interface,” “memory interface” or may have a different name. The user can also implement a software controlled “bit-banged” interface to the HI-6120, at the cost of substantially slower RAM and register read/write times. The bus interface is compatible with the two prevalent bus control signal methods: “Intel style” interface, characterized by separate strobes for read and write operations (OE and WE), and “Motorola style” interface, characterized by a single read/write strobe (STR) and a data direction signal (R/W). Bus control style is selected using the BTYPE configuration pin, which sets the function of two other input pins to serve as either OE and WE, or STR and R/W. The BWID configuration pin selects either 8- or 16-bit bus widths. When the BWID pin is connected to ground, 8-bit mode is selected; two bytes are sequentially transferred for each 16-bit word operation. In 8-bit mode only, the BENDI configuration pin selects bus “endianness.” This is the system attribute that indicates whether integers are represented with the most significant byte stored at the lowest address (big endian) or at the highest address (little endian). Internal device storage is “big endian”. For processor compatibility, the BENDI pin sets the order for byte accesses when the host bus is config- 15.1.1. Bus Wait States and Data Prefetch The HI-6120 has a WAIT output pin that tells the host to add wait states when additional access time is needed during bus read cycles. For compatibility with different host processors, the state of the WPOL input pin sets the WAIT output as active high or active low. The WAIT output can be ignored when the host processor read cycle time is always slow enough to work with the HI6120 bus. When using fast host processors, cycle time is sometimes slowed down by configuring the processor to add one or more wait states during every read or write cycle, but slow-down affects all cycles, even when unnecessary. Data prefetch is a technique used by the HI-6120 to speed up host multi-word read access to registers or RAM by eliminating wait states. Prefetching occurs when HI-6120 logic requests data before it is actually needed. Because register or RAM locations are often read sequentially, performance improves when data is prefetched in address sequence order. For every host read cycle, the device first reads the addressed location, then prefetches the following address, to speed up access in the likely event that the following word will be read next. For the HI-6120, WAIT is always asserted for the first word fetched in any read sequence. The first read cycle has a long access time because there is no prefetch. This may be the first byte read in 8-bit mode, or the first word read in 16-bit mode. After each word (or byte) is fetched for a read operation, the next word (or byte) is prefetched to speed-up the read cycle time when sequential address read sequences occur. After the first word read, the following words read in sequence are accessed without WAIT, resulting in faster overall multiword read timing. As long as bytes or words are read in address order, additional wait states are unnecessary. HOLT INTEGRATED CIRCUITS 107 HI-6120, HI-6121 Data prefetch during read cycles is blocked when the next RAM address is a Control Word in the Descriptor Table. The table base address (set by the value in register 0x0005) and every fourth word thereafter is a Control Word. This consists of table addresses having these address offsets from the table start address of 0, 4, 8, 0xC… 0x1F8 and 0x1FC. If allowed, prefetch (like any other read) would reset the Control Word DBAC status bit, so prefetch is disallowed in this range. Thus for HI-6120, multi-word sequential read sequences will assert WAIT every fourth word when reading RAM within the 512-word Descriptor Table address range. For fastest read access under all conditions, the user can set host processor bus timing (by adjusting processor wait states for the chip select assigned to the HI6120) to match the faster read cycle time for prefetched data, while the HI-6120 WAIT output adds one or more additional wait states for the slower initial read cycle. Timing diagrams for bus read and write operations are shown in Section 17.5. Separate diagrams show “Intel style” and “Motorola style” control interfaces. 15.2.1. Serial Peripheral Interface (SPI) Basics The HI-6121 uses an SPI synchronous serial interface for host access to registers and RAM. Host serial communication is enabled through the Chip Enable (CE) pin, and is accessed via a three-wire interface consisting of Serial Data Input (SI) from the host, Serial Data Output (SO) to the host and Serial Clock (SCK). All programming cycles are completely self-timed, and no erase cycle is required before write. The SPI (Serial Peripheral Interface) protocol specifies master and slave operation; the HI-6121 operates as an SPI slave. The SPI protocol defines two parameters, CPOL (clock polarity) and CPHA (clock phase). The possible CPOLCPHA combinations define four possible “SPI Modes.” Without describing details of the SPI modes, the HI6121 operates in the two modes where input data for each device (master and slave) is clocked on the rising edge of SCK, and output data for each device changes on the falling edge. These are known as SPI Mode 0 (CPHA = 0, CPOL = 0) and SPI Mode 3 (CPHA = 1, CPOL = 1). Be sure to set the host SPI logic for one of these modes. 15.2. HI-6121 Serial Peripheral Interface In the HI-6121, internal RAM and registers occupy a 32K x 16 address space. The lowest 32 addresses access registers and the remaining addresses access RAM locations. Timing is identical for register operations and RAM operations via the serial interface, and read and write operations have likewise identical timing. SCK (SPI Mode 0) 0 1 2 3 4 5 6 7 SCK (SPI Mode 3) 0 1 2 3 4 5 6 7 SI High Z MSB LSB High Z SO MSB LSB CE Figure 18. Generalized Single-Byte Transfer Using SPI Protocol. SCK is Shown for SPI Modes 0 and 3 HOLT INTEGRATED CIRCUITS 108 HI-6120, HI-6121 The difference between SPI Modes 0 and 3 is the idle state for the SCK signal, which is logic 0 for Mode 0 state and logic 1 for Mode 3 state (see Figure 18). There is no configuration setting in the HI-6121 to select SPI Mode 0 or Mode 3 because compatibility is automatic. Beyond this point, the HI-6121 data sheet only shows the SPI Mode 0 SCK signal in timing diagrams. The SPI protocol transfers serial data as 8-bit bytes. Once CE chip enable is asserted, the next 8 rising edges on SCK latch input data into the master and slave devices, starting with each byte’s most-significant bit. The HI-6121 SPI can be clocked at 16 MHz. Multiple bytes may be transferred when the host holds CE low after the first byte transferred, and continues to clock SCK in multiples of 8 clocks. A rising edge on CE chip enable terminates the serial transfer and reinitializes the HI-6121 SPI for the next transfer. If CE goes high before a full byte is clocked by SCK, the incomplete byte clocked into the device SI pin is discarded. Two byte transfers are needed for SPI exchange of 16bit register values or RAM data. “Big endian” byte order is used for SPI data transfers. The high order byte (bits 15:8) is transferred before the low order byte (bits 7:0). In the general case, both master and slave simultaneously send and receive serial data (full duplex) per Figure 18 below. However the HI-6121 operates half duplex, maintaining high impedance on the SO output, except when actually transmitting serial data. When the HI-6121 is sending data on SO during read operations, activity on its SI input is ignored. Figure 19 and Figure 20 show actual behavior for the HI-6121 SO output. W-0-R-R-R-R-0-0 where RRRR is the 4-bit register address, and the most significant bit, W signifies Write when 1, or Read when 0. These fast-access commands appear in Table 13. Figure 19 and Figure 20 show read and write timing as it appears for fast-access register operations. The command byte is immediately followed by two data bytes comprising the 16-bit data word read or written. For a register read or write, CE is negated after the 2-byte data word is transferred. 15.2.4. Indirect Addressing of RAM and Registers Refer to the HI-6121 SPI command set shown in Table 14. SPI commands other than fast-access use an address pointer to indicate the address for read or write transactions. This “memory address pointer” resides at register address 15, and must be initialized before any read or write operation, other than fast-access. To set the address pointer, use a fast-access write to register 15, consisting of command byte 0xBC followed by the desired 16-bit memory or register address. The pointer uses a 15-bit value to access any location in the 32K address range. The current address pointer value can be read using a fast-access read command byte 0x3C. After a 2-byte read/write completion, the internal address pointer automatically increments to the following register address. The host can extend the read or write operation to the next register address by continuing to hold CE low while clocking SCK 16 additional times. This auto-increment feature can be used to access one or more sequential register addresses above the command address. Auto-increment applies (ranging to the top of the address space) as long as SCK continues to be clocked under continuous CE assertion. Caution: When the primary address pointer is used for autoincrementing multi-word read/write and reaches the top of the address range (0x7FFF) the next increment will roll over the pointer value to 0x0000. The host should avoid this situation. 15.2.2. HI-6121 SPI Commands For the HI-6121, each SPI read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion of CE. Since HI-6121 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte. The HI-6121 SPI command set uses the most significant command bit to specify whether the command is Read or Write. The command byte MSB is zero for read commands, and one for write commands. 15.2.3. Fast-Access Commands for Registers 0-15 The SPI command set includes directly-addressed read and write commands for registers 0 through 15. The 8-bit pattern for these commands has the general form HOLT INTEGRATED CIRCUITS 109 HI-6120, HI-6121 SCK SPI Mode 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 MSB LSB SI High Z Command Byte MSB LSB MSB LSB SO High Z Data Byte 0 CE Data Byte 1 Host may continue to assert CE here to read sequential word(s). Each word needs 16 SCK clocks. Figure 19. Single-Word (2-Byte) Read From RAM or a Register SCK SPI Mode 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 MSB LSB MSB LSB MSB LSB SI Command Byte SO High Z Data Byte 0 Data Byte 1 CE Host may continue to assert CE here to write sequential word(s). Each word needs 16 SCK clocks. Figure 20. Single-Word (2-Byte) Write To RAM or a Register HOLT INTEGRATED CIRCUITS 110 HI-6120, HI-6121 Three single-byte SPI commands modify the current address pointer value in register 15: Command Address Pointer Operation 0xD0 0xD8 0xE0 add 1 to the current pointer value add 2 to the current pointer value add 4 to the current pointer value 15.2.5. Data Prefetch for SPI Read Cycles Data prefetch is a technique used by the HI-6121 to speed up host multi-word read access to registers or RAM. Prefetching occurs when HI-6121 logic accesses data before it is actually needed. Because register or RAM locations are often read sequentially, performance improves when data is prefetched in address sequence order. For any SPI read cycle, the HI-6121 first fetches the addressed location, then increments the memory address pointer and prefetches the following address, to speed up access in the likely event that the following word will be read next. For the HI-6121, read cycle prefetch allows the SPI host to read sequential locations back-to-back, continuing as long as the host asserts chip select and provides SPI clock. This is described as the Memory Address Pointer “auto-increment” feature. There is an exception: read cycle prefetch is blocked when the next RAM address is a Control Word in the Descriptor Table. If allowed, pre-fetch (like any other read) would reset the Control Word DBAC status bit. To preserve DBAC status bit function, prefetch is disabled when reading Control Words within Descriptor Table address range. The table base address (set by the value in register 0x0005) and every fourth word thereafter is a Control Word. This consists of table addresses having these offsets from the table start address: 0, 4, 8, 0xC through and including 0x1F8 and 0x1FC. See further information in Section 15.2.7. These two commands can be used to read or write a single location, or may be used to start a multi-word read or write that uses the pointer’s auto-increment feature. The “Add 4” command may be useful when sequentially accessing the same word (for example, the Control Word) in a series of 4-word Descriptor Table entries. The “Add 2” command might be useful for reading the Interrupt Log Buffer, comprised of 2-word log entries. In both cases, the Add command would be probably followed by Read command 0x40 to read the location addressed by the current pointer value. Similarly, Write command 0xC0 writes the location addressed by the current pointer value. Two command bytes cannot be “chained”; CE must be negated after the Add command, then reasserted for the following Read or Write command. The memory address pointer is not affected by fastaccess read/writes to registers 0-14 because fastaccess SPI commands use a separate, internal pointer not directly accessible to the host. Just two single-byte SPI commands use the current address pointer value in register 15 without first loading or otherwise modifying it: Command Read Operation 0x40 read location addressed by pointer value Command Write Operation 0xC0 write location addressed by pointer value Either of these commands can be used to read or write a single location, or may be used when starting a multiword read or write by using the pointer’s auto-increment feature. Two single-byte SPI commands increment the current address pointer value in register 15, then perform a read or write: Command Read Operation 0x48 add 1 to pointer then read addressed location 15.2.6. Special Purpose Commands Several other HI-6121 SPI commands load or otherwise modify the primary address pointer before initiating a read or write process. These commands were tailored to the specific needs of HI-6121 Remote Terminal host software. Using a single-byte SPI command, the address pointer can be directly loaded with the memory address for the descriptor table Control Word corresponding to the last completed MIL-STD-1553 command. The Control Word is then read. Command Read Operation 0x50 Copy Current Control Word Address register 13 to address pointer register 15. Read the location addressed by the new pointer value. Command Write Operation 0xC8 add 1 to pointer then write addressed location This command can be used to read just the current HOLT INTEGRATED CIRCUITS 111 HI-6120, HI-6121 Control Word, or may be used to start a multi-word read because memory pointer auto-increment occurs after the Control Word is read. Six single-byte SPI commands add an offset to the current address pointer value, then read the addressed memory location; the read value is then written to the address pointer register 15. The new pointer value is used to start a read or write operation: Command Read Operation 0x68 Read the location addressed by the memory address pointer. Write the value just read into the memory address pointer. Then read. Add 1 to the memory address pointer. Read value at newly addressed location and write it into the memory address pointer. Then read. Add 2 to the memory address pointer. Read value at newly addressed location and write it into the memory address pointer. Then read. When some or all subaddress or mode commands are not programmed to trigger host interrupts, a different single-byte SPI command may be useful if polling the Descriptor Table for message activity. In this situation, the host may poll a series of Descriptor Table Control Words looking for instances where the DBAC activity bit is set. The DBAC (Descriptor Block Accessed) flag is set in the Control Word each time the corresponding command is completed. The process of reading the Control Word automatically resets the register’s DBAC bit so the host can detect activity the next time the DBAC flag is set by the device. Since Descriptor Table Control Words are spaced four words apart, this command is useful when polling a series of descriptor table Control Words: Command Read Operation 0x60 read addressed location then add 4 to pointer 0x70 0x78 Primary use occurs when the address pointer initially points to the first Descriptor Table Control Word in a series of Control Words to be polled (every fourth word). After 8 SCK clocks for the SPI command, each instance of this command reads a single location using 16 SCK clocks. If CS remains low after 24 clocks and SCK continues, a multi-word read begins, using the address pointer’s auto-increment feature. The second word read is at (Control Word address + 4), the next Control Word in the table. Another single-byte SPI command is useful when servicing interrupts. When enabled interrupts occur, two words are written to the circular 32-word Interrupt Log Buffer, and the Interrupt Log Address register 9 is updated to show the storage address where interrupt information words will be stored for the next occurring interrupt. Buffer starting address is 0x0040 and ending address is 0x005F. Because two words are written to the buffer for each interrupt, the Interrupt Log Address register always contains an even value in the range of 0x0040 to 0x005E. When servicing an interrupt that just occurred, the host wants timely information on that interrupt. An SPI command is provided to simplify interrupt handling: Command Write Operation 0xE8 Read the location addressed by the memory address pointer. Write the value just read into the memory address pointer. Then write. Add 1 to the memory address pointer. Read value at newly addressed location and write it into the memory address pointer. Then write. Add 2 to the memory address pointer. Read value at newly addressed location and write it into the memory address pointer. Then write. 0xF0 0xF8 Primary use occurs when a Descriptor Table Control Word was just read. For example, the last op code performed was 0x50, reading the Control Word for the last command. After reading the Control Word, the memory pointer has automatically incremented. The host can examine flag bits contained in the just-read Control Word to determine the applicable data buffer (e.g., Data Buffer A, Data Buffer B or the Broadcast Data Buffer) then directly service that buffer using these op codes; the three data buffer pointers occur in the three words following the initially read Control Word. These six commands can be used to read or write a single location, or may be used to start a multi-word read or write that uses the pointer’s auto-increment feature. HOLT INTEGRATED CIRCUITS 112 HI-6120, HI-6121 Command Read Operation write memory address pointer 0x000F with current value in Interrupt Log Address register minus 1. If the Log Address register contains 0x0040 then 0x005F is written to memory pointer register. Then read the addressed RAM location, containing the last-written Interrupt Address Word. Then decrement the memory address pointer, addressing the corresponding Interrupt Information Word. addressed word is transferred by SPI to the host, the HI6121 continues to read and transmit words from sequential RAM memory addresses, as long as the host continuously asserts chip select while providing SCK serial clock pulses. After fetching each new word, the device increments the Memory Address Pointer and prefetches the data contained in the newly addressed location. The next word is prefetched even when the host does not ultimately read the following address. For HI-6121, sequential reads from Descriptor Table that rely on MAP auto-increment will stop advancing when the next address contains a table Control Word. Properly designed SPI transfers overcome this behavior. Using SPI command op codes, the HI-6121 host must consider prefetch and pointer behavior when reading data from the Descriptor Table. Applied outside the Descriptor Table, the following SPI sequence would read data from six successive memory addresses. But below, applied within the table, the sequence gets stuck at the fourth word read. Here we assume the Descriptor Table starts at default base address, 0x0200. The host first uses SPI op code 0xBC to store the table start address 0x0200 in the Memory Address Pointer, then uses op code 0x40 (and MAP auto-increment) to read the MAP-addressed location and successive locations. 0x58 This command can be used to read a single location, or may be used to start a multi-word read in which the memory address pointer automatically decrements after each word read. This is the only SPI op code that decrements the memory pointer for multi-word operations. Repeated memory pointer decrements will wrap around the 0x0040 to 0x005F log buffer boundary. 15.2.7. Descriptor Table Prefetch Exceptions For the SPI-interface HI-6121, the Memory Address Pointer (register 0x000F) contains the address for each new word read by the host. When starting a read access, the host usually writes the memory address pointer with the address for the first word to read. The host then uses an SPI op code to initiate the read process. After the Notice: There is no MAP auto-increment or data prefetch when MAP equals 0x0203, so the final two read cycles repeat the previous read value and address. FROM HOST ===== 0xBC 0x0200 0x40 ------------------FROM HI-6121 ======= --------- COMMENT ========================================== SPI op code writes memory address pointer (MAP). The table start address written to MAP. SPI op code to “read location addressed by MAP” data from 0x0200 (SCK continues afterward) data from 0x0201 (SCK continues afterward) data from 0x0202 (SCK continues afterward) data from 0x0203 (SCK continues afterward, Control Word next) data from 0x0203 (SCK continues afterward, Control Word next) data from 0x0203 (SCK stops and /CS is then negated) HOLT INTEGRATED CIRCUITS 113 HI-6120, HI-6121 Using a different SPI op code, the host can sequentially read the entire Descriptor Table. FROM FROM HOST HI-6121 ===== ======= 0xBC ---0x01FF ---0x48 ------------0x48 ------------0x48 --------------- --- --- COMMENT ========================================== op code writes memory address pointer (MAP) decremented table start addr 0x0200 - 1 written to MAP op code pre-increment data from 0x0200 (SCK data from 0x0201 (SCK data from 0x0202 (SCK data from 0x0203 (SCK op code pre-increment data from 0x0204 (SCK data from 0x0205 (SCK data from 0x0206 (SCK data from 0x0207 (SCK op code pre-increment data from 0x0208 (SCK data from 0x0209 (SCK data from 0x020A (SCK data from 0x020B (SCK MAP then read addressed location continues afterward) continues afterward) continues afterward) stops and /CS is negated) MAP then read addressed location continues afterward) continues afterward) continues afterward) stops and /CS is negated) MAP then read addressed location continues afterward) continues afterward) continues afterward) stops and /CS is negated) The host may repeat this sequence until the entire Descriptor Table is read. The repeating read process is not shown, but the sequence could end like this, continuing beyond the table boundary… 0x48 --------------- op code pre-increment data from 0x03FC (SCK data from 0x03FD (SCK data from 0x03FE (SCK data from 0x03FF (SCK MAP then read addressed location continues afterward) continues afterward) continues afterward) continues afterward) TABLE ENDS HOLT INTEGRATED CIRCUITS 114 HI-6120, HI-6121 Table 13. Fast-Access SPI Commands for Registers 0-15 Command Bits 5:2 Convey the 4-Bit Register Address. Command Bits 76543210 00000000 00000100 00001000 00001100 00010000 00010100 00011000 00011100 00100000 00100100 00101000 00101100 00110000 00110100 00111000 00111100 HEX Byte 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C Fast-Access Read Read Register 0 Read Register 1 Read Register 2 Read Register 3 Read Register 4 Read Register 5 Read Register 6 Read Register 7 Read Register 8 Read Register 9 Read Register 10 Read Register 11 Read Register 12 Read Register 13 Read Register 14 Read Register 15 Command Bits 76543210 10000000 10000100 10001000 10001100 10010000 10010100 10011000 10011100 10100000 10100100 10101000 10101100 10110000 10110100 10111000 10111100 HEX Byte 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 Fast-Access Write Write Register 0 Write Register 1 Write Register 2 Write Register 3 Write Register 4 Write Register 5 Write Register 6 Write Register 7 Write Register 8 Write Register 9 Write Register 10 0xAC Write Register 11 0xB0 0xB4 0xB8 Write Register 12 Write Register 13 Write Register 14 0xBC Write Register 15 HOLT INTEGRATED CIRCUITS 115 HI-6120, HI-6121 Table 14. SPI Commands using Address Pointer Register Hex Byte Read or Read Write Address Pointer Operations (no data is written or read, no pointer auto-increment) 0xD0 0xD8 0xE0 ------------------Add 1 to the current address pointer value in register 15 Add 2 to the current address pointer value in register 15 Add 4 to the current address pointer value in register 15 Read / Write RAM or Register Location Using Current Address Pointer Value 0x40 0xC0 R W Read location addressed by current address pointer value in register 15 Write location addressed by current address pointer value in register 15 Increment Address Pointer Then Read / Write Addressed RAM or Register Location 0x48 0xC8 R W Read addressed location after incrementing pointer in register 15 Write addressed location after incrementing pointer in register 15 Special Purpose Commands 0x50 0x68 0x70 0x78 0xE8 0xF0 0xF8 0x60 0x58 R R R R W W W R R Copy register 13 (current Control Word address) to address pointer in register 15, then read the location addressed by the new pointer value (read the current Control Word) Add 0 to the current address pointer value in register 15. Then . . . Add 1 to the current address pointer value in register 15. Then . . . Add 2 to the current address pointer value in register 15. Then copy value from newly addressed location to address pointer in register 15 then read newly addressed location. Add 0 to the current address pointer value in register 15. Then . . . Add 1 to the current address pointer value in register 15. Then . . . Add 2 to the current address pointer value in register 15. Then copy value from newly addressed location to address pointer in register 15 then write newly addressed location. Read then add 4 to the current address pointer value in register 15. Write storage address of last-written Interrupt Address Word to the address pointer in register 15, then read the Interrupt Address Word from the Interrupt Log buffer. Decrement memory address pointer after read operation. HOLT INTEGRATED CIRCUITS 116 HI-6120, HI-6121 16. APPENDIX: RT MESSAGES RESPONSES, OPTIONS & EXCEPTIONS Circumstances for Received Message Terminal Response to Received Command Bits Updated in Descriptor Control Word No change Bits Updated in Data Buffer Msg Info Word No Message Info Word is written Interrupt Options None Invalid Command No terminal response, Word (Manchester, the message is ignored. parity or bit count error) No Status Word change. Any valid command to RT31 (broadcast). when the BCSTINV bit in Configuration Register 1 equals 1. RT Address Parity Error based on RTA and RTAP bits in the Operational Status Register Any valid non-mode (subaddress 1-30) transmit command to RT31 (undefined broadcast transmit). Any valid non-mode (subaddress 1-30) transmit command except for RT31. The corresponding bit in the Illegalization Table equals 0.* Any valid non-mode (subaddress 1-30) transmit command except for RT31. The corresponding bit in the Illegalization Table equals 1. ** Any valid non-mode (subaddress 1-30) receive command. The corresponding bit in the Illegalization Table equals 0. * No terminal response, the message is ignored. No Status Word change. (Broadcast commands are rendered invalid.) For commands to the RT’s own address or to broadcast address RT31: No terminal response, message is ignored. No Status Word change. No terminal response, Set Message Error (ME) and BCR status bits. Normal Status Word response (Clear Status). Data words for transmit are read from the RAM data buffer assigned by the Descriptor Table entry for the transmit subaddress. No change No Message Info Word is written None No change No Message Info Word is written RTAPF (not optional) DBAC bit set. DPB bit toggles. BCAST bit set. MERR bit set. BUSID bit updated. IWA IBR (IXEQZ) Normal CS update: BUSID bit updated. DBAC bit set. MERR bit reset. DPB bit toggles. ILCMD bit reset. BCAST bit reset. RTRT bit updated. (Other error bits reset). ILCMD bit set. DBAC bit set. BUSID bit updated. DPB bit toggles. MERR bit set. BCAST bit reset. RTRT bit updated. (Other error bits reset). Normal update: BUSID bit updated. DBAC bit set. MERR bit reset. DPB bit toggles. ILCMD bit reset. BCAST bit reset. RTRT bit updated. (Other error bits reset). IWA IBR (IXEQZ) Assert Message Error (ME) status, then transmit ME Status Word without following data words. Normal Status Word response (Clear Status). After message completion, the data words received are stored in the data buffer RAM location assigned by the Descriptor Table entry for the receive subaddress. ILCMD IWA IWA IBR (IXEQZ) * Terminal is using “illegal command detection” and command is legal OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). ** Terminal is using “illegal command detection” and command is illegal. HOLT INTEGRATED CIRCUITS 117 HI-6120, HI-6121 Circumstances for Received Message Any valid non-mode (subaddress 1-30) receive command. The corresponding bit in the Illegalization Table equals 1. ** Valid receive command followed by invalid data word (Manchester, parity or bit count error). Valid receive command followed by one or more good data words, then a data word having Command Sync. Any valid command followed by wrong number of data words (too few or too many words) RT-RT where CW1 is a valid non-mode receive command. CW2 is a non-mode transmit command valid for different RT. (Normal RT-RT receive message) RT-RT where CW1 is a valid non-mode receive command. Transmit command CW2 has an error: T/R bit = 0, or CW2 subaddress equals 0 or 31 (mode code), or CW2 has same RT address as CW1. Terminal Response to Received Command Assert Message Error (ME) status and set BCR if broadcast. Any received data words are ignored and are not saved. When data reception stops, transmit Status Word. No terminal response. Set Message Error (ME) status. If broadcast (RT31), also set the BCR status bit. Bits Updated in Descriptor Control Word DBAC bit set. DPB bit toggles. BCAST bit updated. Bits Updated in Data Buffer Msg Info Word ILCMD bit set. BUSID bit updated. MERR bit set. RTRT bit updated. (Other error bits reset) MERR bit set. BUSID bit updated. IWDERR bit set. ILCMD bit reset. RTRT bit updated (Other error bits reset). MERR bit set. BUSID bit updated. SYNERR bit set. ILCMD bit reset. (Other error bits reset). Interrupt Options ILCMD IWA IBR (IXEQZ) DBAC bit set. BCAST bit updated. DPB bit toggles. MERR IWA IBR No terminal response. Set Message Error (ME) status. If broadcast (RT31), also set the BCR status bit. DBAC bit set. BCAST bit updated. DPB bit toggles. MERR IWA IBR No terminal response. Set Message Error (ME) status. If broadcast (RT31), also set the BCR status bit. DBAC bit set. BCAST bit updated. DPB bit toggles. MERR bit set. BUSID bit updated. Set WCTERR (too few) MERR or GAPERR (too IWA many). IBR ILCMD bit reset. RTRT bit updated. (Other error bits reset). Normal CS update: BUSID bit updated. RTRT bit set. RTCWERR bit reset. ILCMD bit reset. (All error bits reset). Normal Status Word response (Clear Status). If RT-RT Command Word 1 is broadcast (RT31) set the BCR status bit. DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR (IXEQZ) No terminal response. Set Message Error (ME) status. If RT-RT Command Word 1 is broadcast (RT31) also set the BCR status bit, DBAC bit set. BCAST bit updated. DPB bit toggles. MERR bit set. BUSID bit updated. RTRT bit set. RTRTCWERR bit set. ILCMD bit reset. (Other error bits reset). MERR IWA IBR HOLT INTEGRATED CIRCUITS 118 HI-6120, HI-6121 Circumstances for Received Message RT-RT where CW1 is a valid non-mode receive command. CW2 is valid for different RT but transmitting RT does not respond in time. RT-RT receive command (CW1 is valid). The transmitting RT response has one of these errors: invalid word (Manchester, (sync, bit count, parity or word count error). Also includes transmitting RT response with Message Error or Busy status followed by no data words. RT-RT command where CW2 is a valid non-mode (subaddress 1-30) transmit command. CW1 is a non-mode receive command for RT31. (Normal broadcast RT-RT transmit) Valid mode code command to RT31 (broadcast). The BCSTINV bit in Configuration Register 1 equals 1. Valid undefined mode code command. The UMCINV bit in Configuration Register 1 equals 1. Terminal Response to Received Command No terminal response. Set Message Error (ME) status. If RT-RT Command Word 1 is broadcast (RT31), also set the BCR status bit. Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated DPB bit toggles. Bits Updated in Data Buffer Msg Info Word MERR bit set. BUSID bit updated. RTRT bit set. TMOERR bit set. ILCMD bit reset. (Other error bits reset). Interrupt Options MERR IWA IBR MERR bit set. BUISID bit reset. No terminal response. RTRT bit set. Set Message Error (ME) status. DBAC bit set. IWDERR bit set, If RT-RT Command Word 1 is BCAST bit reset. or WCTERR bit set broadcast (RT31) also set DPB bit toggles. for Tx RT Busy case. the BCR status bit. ILCMD bit reset. (Other error bits reset). MERR IWA IBR Normal Status Word response. Clear status is transmitted with the commanded number of data words. Data words for transmit are read from the RAM data buffer assigned in the Descriptor Table entry for the transmit subaddress. Normal CS update: BUSID bit updated. DBAC bit set. MERR bit reset. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit set. (All error bits reset). IWA (IXEQZ) No terminal response, the message is ignored. No Status Word change. No terminal response, the message is ignored. No Status Word change. NOTE: This only applies for the undefined mode codes: MC0 to MC15 with T/R = 0 MC16,18 & 19 with T/R = 0 MC17,20 & 21 with T/R = 1 No change No Message Info Word is written None No change No Message Info Word is written None HOLT INTEGRATED CIRCUITS 119 HI-6120, HI-6121 Circumstances for Received Message Terminal Response to Received Command If MC2 (transmit status) or MC18 (transmit last command) status word from last command is transmitted. If MC18, data word transmitted is read from an internal register. OR If not MC2 or MC18, normal Status Word response. If broadcast, assert Status Word BCR bit. For mode codes 16-31 with T/R bit = 1 which transmit a data word, the word for transmit is read from the Mode Command Data Table. AND For all mode commands with mode data word (mode codes 16-31), the transmitted or received data word is written to command’s Descriptor Word 4. Set Message Error (ME) status. If not broadcast (RT31), transmit. Status Word without a following mode data word. If broadcast (RT31), also assert the BCR status bit. AND For mode commands with a mode data word (mode codes 16-31), no updates are made to the Mode Command Data Table or to the command’s Word 4 in Descriptor Table. Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options Valid defined mode code command (including reserved mode code) not “illegalized” by Illegalization Table (table bit equals 0 *) DBAC bit set. BCAST bit updated. DPB bit toggles. Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) IWA IBR (IXEQZ) Valid defined mode code command that is “illegalized” by the IllegalizationTable (table bit equals 1 **) DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD bit set. BUSID bit updated. MERR bit reset. RTRT bit reset. (Other error bits reset.) ILCMD IWA IBR * Terminal is using “illegal command detection” and command is legal OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). ** Terminal is using “illegal command detection” and command is illegal. HOLT INTEGRATED CIRCUITS 120 HI-6120, HI-6121 Circumstances for Received Message Terminal Response to Received Command If bit in Illegalization Table that corresponds to the undefined mode code command equals 1 ** Set Message Error (ME) status, If not broadcast (RT31), transmit Status Word without a following mode data word. If broadcast (RT31), also assert the BCR status bit. OR If bit in Illegalization Table that corresponds to the undefined mode code command equals 0* Normal Status Word (Clear Status) response. If command was broadcast (RT31), assert the BCR status bit. AND For mode codes 16-31 with T/R bit = 1 which transmit a data word, the word for transmit is read from the Mode Command Data Table. AND For all mode commands with mode data word (mode codes 16-31), the transmitted or received data word is written to command’s Descriptor Word 4. Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated. DPB bit toggles. Bits Updated in Data Buffer Msg Info Word ILCMD bit set. BUSID bit updated. MERR bit reset. RTRT bit reset. (Other error bits reset.) Interrupt Options ILCMD IWA IBR Valid undefined mode code command. The UMCINV bit in Configuration Register 1 equals 0. DBAC bit set. BCAST bit updated. DPB bit toggles. Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) IWA IBR (IXEQZ) * Terminal is using “illegal command detection” and command is legal OR terminal is not using “illegal command detection” and command may be legal or illegal (in form response). ** Terminal is using “illegal command detection” and command is illegal. HOLT INTEGRATED CIRCUITS 121 HI-6120, HI-6121 Circumstances for Received Message Valid receive command followed by invalid data word (Manchester, parity or bit count error). Superseded Message: Terminal receives an incomplete message interrupted by a gap of at least 3.5 us, followed by a new valid command on the same bus or on the other bus OR Terminal is transacting a transmit message on one bus and receives the start of a valid command on the other bus. Terminal is Busy for a valid receive command either globally (BUSY bit set in Status Word Bits register) or in response to a particular valid receive command (MKBUSY bit set in the command’s Descriptor Table control word.) Terminal is Busy for a valid transmit command either globally (BUSY bit set in Status Word Bits register) or in response to a particular valid receive command (MKBUSY bit set in the command’s Descriptor Table control word.) Terminal Response to Received Command No terminal response. Set Status Word ME bit, If broadcast, also set Status Word BCR bit. Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated. DPB bit toggles. No change to superseded command’s Control Word. For superseding command’s Control Word: DBAC bit set. BCAST bit updated DPB bit toggles. Bits Updated in Data Buffer Msg Info Word MERR bit set. BUSID bit updated. IWDERR bit set. ILCMD bit reset. RTRT bit updated. (Other error bits reset.) No Msg Info Word written for the superseded command. For superseding command’s data buffer, a normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit updated. (All error bits reset.) Interrupt Options MERR IWA IBR Terminal aborts processing for first message and responds in full to the second (superseding) message. The Status Word BCR bit reflects broadcast status for: the second command, unless second command is MC2 (transmit status) or MC18 (transmit last command). None for superseded command IWA IBR (IXEQZ) Busy bit is set in the 1553 Status Bits register. Status Word is transmitted, unless broadcast. If broadcast, the BCR bit in Status Word is also set. After message completion, data words received are stored in the data buffer assigned by the receive subaddress Descriptor Table entry. DBAC bit set. BCAST bit updated. DPB bit toggles. WASBSY bit set. BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit updated. (All error bits reset.) IWA IBR Busy bit is set in the 1553 Status Bits register. If not broadcast, Status Word is transmitted without data. If broadcast, the BCR bit in Status Word is also set. DBAC bit set. BCAST bit updated, (mode commands with T/R = 1) DPB bit toggles WASBSY bit set. BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit updated. (All error bits reset.) IWA IBR HOLT INTEGRATED CIRCUITS 122 HI-6120, HI-6121 Circumstances for Received Message DYNAMIC BUS CONTROL (MC0): Mode code command with mode code 00000 and T/R bit equals 1 The mode code’s bit in Illegalization Table equals 0 * OR The mode code’s bit in Illegalization Table equals 1 ** Terminal Response to Received Command HI-6110 is not equipped to accept bus control duties. The host must initialize device to respond using either of the two following methods: RT is not using “illegal command detection.” Respond “in form”: Reset Message Error (ME) status and transmit Status Word. OR RT is using “illegal command detection”and mode code is illegalized. Set Message Error (ME) status and transmit Status Word. DBAC bit set. Normal CS update: BCAST bit reset. BUSID bit updated. DPB bit toggles. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) DBAC bit set. ILCMD bit set. BCAST bit reset. BUSID bit updated. DPB bit toggles. MERR bit reset. RTRT bit reset. (Other error bits reset.) IWA Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options ILCMD IWA MC0 EXCEPTIONS: Broadcast address RT31 (broadcast not allowed) No Status Word transmit. Set the Message Error (ME) and BCR status bits. DBAC bit set. BCAST bit set. DPB toggles. MERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) MERR IWA IBR Mode code command word is followed by a contiguous data word Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** No Status Word transmit. Set the Message Error (ME) status bit. No terminal response, the message is ignored. No Status Word change. (MC0 is not ndefined when T/R bit equals 0) MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD, RTRT bits DPB bit toggles. reset. (Other error bits reset.) No Message Info Word is written MERR IWA No Change None * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 123 HI-6120, HI-6121 Circumstances for Received Message T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 0. Illegalization Table bit equals 0 * T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 0. Illegalization Table bit equals 1 ** Terminal Response to Received Command Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) Interrupt Options Respond “In form”: DBAC bit set. Reset Message Error BCAST bit reset. (ME) status and transmit Status DPB bit toggles. Word. IWA IBR ILCMD bit set. Set Message Error DBAC bit set. MERR bit set. (ME) status and transmit Status BCAST bit reset. BUSID bit updated. Word. DPB bit toggles. RTRT bit reset. (Other error bits reset.) ILCMD IWA IBR * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” HOLT INTEGRATED CIRCUITS 124 HI-6120, HI-6121 Circumstances for Received Message SYNCHRONIZE WITHOUT DATA (MC1): Mode code command with mode code 00001 and T/R bit equals 1 MC1 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. The Time Tag counter is not reset. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. The Time Tag counter is not reset. No Status Word transmit. Set the Message Error (ME) status bit. No Message Info Word is written Terminal Response to Received Command Default response: Reset Message Error (ME) status then transmit Status Word. If broadcast, set the Status Word BCR bit and suppress Status Word transmit. Reset the Time Tag counter to 0x0000. Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Normal update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) Interrupt Options DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. Normal update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) IWA IBR T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) MERR bit set. WCTERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD IWA IBR Mode code command word is followed by a contiguous data word DBAC bit set. BCAST bit updated. DPB bit toggles. MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 125 HI-6120, HI-6121 Circumstances for Received Message TRANSMIT STATUS (MC2): Mode code command with mode code 00010 and T/R bit equals 1 MC2 EXCEPTIONS: Broadcast address No Status Word transmit. RT31 Set the Message Error (broadcast not allowed) (ME) and BCR status bits. Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0 The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0 The Illegalization Table. bit equals 1 ** Mode code command word is followed by a contiguous data word No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Time Tag counter is not reset. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. DBAC bit set. BCAST bit set. DPB bit toggles. MERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) No Message Info Word is written MERR IWA IBR Terminal Response to Received Command No Status Word updates, Transmit Status from last valid command (assuming last command was not a “Transmit Status” or a “Transmit last Command” mode command. Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options Normal CS update: BUSID bit updated. DBAC bit set. MERR bit reset. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (All error bits reset.) IWA No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. DBAC bit set. WCTERR bit set. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 126 HI-6120, HI-6121 Circumstances for Received Message Terminal Response to Received Command Default response: Reset Message Error (ME) status then transmit Status Word. If broadcast, set the Status Word BCR bit and suppress status transmit. Host should initiate selftest then update Built-In Test word at shared RAM address 0x0093. Resume terminal execution. Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options INITIATE SELF TEST (MC3): Mode code command with mode code 00011 and T/R bit equals 1 DBAC bit reset. BCAST bit updated. DPB bit toggles. Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) IWA IBR MC3 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 127 HI-6120, HI-6121 Circumstances for Received Message TRANSMITTER SHUTDOWN (MC4): Mode code command with mode code 00100 and T/R bit equals 1 Terminal Response to Received Command Default response: Reset Message Error (ME) status then transmit Status Word. If broadcast, set Status Word BCR bit and suppress status. transmit. After Status transmission, inhibit the inactive bus: Bits Updated in Descriptor Control Word DBAC bit reset. BCAST bit updated. DPB bit toggles. Bits Updated in Data Buffer Msg Info Word Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) Interrupt Options IWA IBR The device automatically shuts down either transmit and receive or transmit only for the inactive bus, depending on the state of the SDSEL bit in Configuration Register 2. (See description of SDSEL and MCOPT4 bits in Configuration Register 2 for further information. When a bus transmitter (or transmitter and receiver) is shut down by mode command, bus status is reflected by assertion of a TXASD or TXBSD bit in the Built-In Test Register at register address 0x0014. If SDSEL equals logic 0, an RXASD or RXBSD bit will also be asserted. See Built-In Test Register description for further information. Once shutdown, the inactive bus transmitter (or transmitter and receiver can only be reactivated by an “Override Transmitter Shutdown” MC5 or MC21 or “Reset Remote Terminal” MC8 mode code command, or by software reset (by setting the SRST bit in Configuration Register 1) or by hardware reset initiated by asserting the MR master reset input pin. MC4 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 128 HI-6120, HI-6121 Circumstances for Received Message Terminal Response to Received Command Default response: Reset Message Error (ME) status then transmit Status Word. If broadcast, set the Status Word BCR bit and suppress status transmit. This command is only used with dual redundant buses. After Status transmission, reactivate inactive bus: Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options OVERRIDE TRANSMITTER SHUTDOWN (MC5): Mode code command with mode code 00101 and T/R bit equals 1 DBAC bit reset. BCAST bit updated. DPB bit toggles. Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) IWA IBR The device automatically re-enables transmit and receive for the inactive bus, regardless of the state of the SDSEL bit in Configuration Register 2. The device affirms reenabled bus status by resetting all four TXASD, TXBSD, RXASD and/or RXBSD bits in the Built-In Test Register at register address 0x0014. Note: If the TXINHA or TXINHB input pins are asserted, the device cannot override the resulting hardware transmit inhibit for the affected bus. In this case, the corresponding TXASD and/or TXBSD bits remain high. See Built-In Test Register description for further information. MC5 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 129 HI-6120, HI-6121 Circumstances for Received Message INHIBIT TERMINAL FLAG BIT (MC6): Mode code command with mode code 00110 and T/R bit equals 1 Terminal Response to Received Command Default response: Reset Message Error (ME) status then transmit Status Word. If broadcast, set the Status Word BCR bit and suppress status transmit. Bits Updated in Descriptor Control Word DBAC bit reset. BCAST bit updated. DPB bit toggles. Bits Updated in Data Buffer Msg Info Word Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) Interrupt Options IWA IBR The device automatically sets the TF Inhibit bit in the BIT Word register at address 0x0013. While the TF inhibit bit is set, the device disregards assertion of the Terminal Flag (TF) bit in the 1553 Status Bits register (0x0006) and only transmits status with the Terminal Flag status bit reset. Once the Terminal Flag has been inhibited, it can be reactivated by an “Override Inhibit Terminal Flag” MC7 or “Reset Remote Terminal” MC8 mode command, by software reset (asserting the SRST bit in Configuration Register 1) or by asserting the MR master reset input pin. MC6 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 130 HI-6120, HI-6121 Circumstances for Received Message OVERRIDE INHIBIT TERMINAL FLAG BIT (MC7): Mode code command with mode code 00111 and T/R bit equals 1 Terminal Response to Received Command Default response: Reset Message Error (ME) status then transmit Status Word. If broadcast, set the Status Word BCR bit and suppress status transmit. Bits Updated in Descriptor Control Word DBAC bit reset. BCAST bit updated. DPB bit toggles. Bits Updated in Data Buffer Msg Info Word Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) Interrupt Options IWA IBR The device automatically resets the TF Inhibit bit in the BIT Word register at address 0x0013. While the TF inhibit bit is reset, the device transmits status with the Terminal Flag status bit set if the Terminal Flag (TF) bit is asserted in the 1553 Status Bits register (0x0006). MC7 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 131 HI-6120, HI-6121 Circumstances for Received Message RESET REMOTE TERMINAL (MC8): Mode code command with mode code 01000 and T/R bit equals 1 Terminal Response to Received Command Default response: Reset Message Error (ME) status. If not broadcast, transmit Status Word. Bits Updated in Descriptor Control Word DBAC bit reset. BCAST bit updated. DPB bit toggles. Bits Updated in Data Buffer Msg Info Word Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) Interrupt Options IWA IBR After Status transmission, the device automatically resets the status Message Error (ME) Busy and Broadcast Command received (BCR) bits in its internal status register. The BIT Word at shared RAM address is reset to 0x0000. If either transmitter was shutdown, the shutdown condition is overridden. If the Terminal Flag (TF) status bit was inhibited, the inhibit is reset. This command does not reset any of the host-programmed registers that configure the terminal for operation. To complete the terminal reset process, the host must assert either MR hardware master reset (with or without autoinitialization) or assert the SRST bit in Configuration Register 1 to execute software reset. See following section entitled Reset and Initialization for additional details. Because MC8 requires host interaction, most applications will probably utilize the IWA interrupt to alert the host when received. MC8 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. GAPERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 132 HI-6120, HI-6121 Circumstances for Received Message RESERVED MODE CODES MC9 - MC15: Mode code command with mode codes 01001 through 01111 and T/R bit equals 1 The mode code’s bit in Illegalization Table equals 0 * OR The mode code’s bit in Illegalization Table equals 1 ** Terminal Response to Received Command The reserved mode code commands do not have defined terminal actions. Host must initialize device to respond using either of the two following methods: RT is not using “illegal command detection.” Respond “in form”: Reset Message Error (ME) status and transmit Status Word. OR RT is using “illegal command detection”and mode code is illegalized. Set Message Error (ME) status and transmit Status Word. DBAC bit set. BCAST bit updated. DPB bit toggles. Normal CS update: BUSID bit reset. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) ILCMD bit set. BUSID bit updated. MERR bit set. RTRT bit reset. (Other error bits reset.) IWA Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA MC9 - MC15 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 133 HI-6120, HI-6121 Circumstances for Received Message Terminal Response to Received Command Default CS response: Reset Message Error (ME) and BCR status bits. then transmit Status Word followed by the data word stored in the assigned index or ping-pong data buffer (or in Descriptor Word 4 for SMCP Simplified Mode Command Processing). Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options TRANSMIT VECTOR WORD (MC16): Mode code command with mode code 10000 and T/R bit equals 1 Normal CS update: BUSID bit updated. DBAC bit reset. MERR bit reset. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (All error bits reset.) IWA MC16 EXCEPTIONS: Broadcast address RT31 (broadcast not allowed) Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No Status Word transmit. Set the Message Error (ME) and BCR status bits. No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. DBAC bit set. BCAST bit set. DPB toggles. MERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) MERR IWA IBR No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA IBR * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 134 HI-6120, HI-6121 Circumstances for Received Message SYNCHRONIZE WITH DATA WORD (MC17): Mode code command with mode code 10001 and T/R bit equals 1 Terminal Response to Received Command Default response: Reset Message Error (ME) status. and transmit Status Word. If broadcast, set BCR status bit and suppress Status response. Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options Normal CS update: BUSID bit updated. DBAC bit reset. MERR bit reset. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (All error bits reset.) IWA Device stores received data word in the assigned ping-pong or index data buffer (or in Descriptor Word 4 for SMCP Simplified Mode Command Processing). Configuration Register 2 MCOPT2 and MCOPT3 bits allow automatic Time-Tag count loading using the data word received. If MCOPT2 equals 1, the received data word is automatically loaded to the Time-Tag counter if the low order bit of the received data word (bit 0 equals 0. If MCOPT3 equals 1, the received data word is automatically loaded to the Time-Tag counter if the low order bit of the received data word (bit 0) equals 1. If both bits are set, the received data word is unconditionally loaded into the Time-Tag counter. For non-broadcast commands, counter load occurs before status word transmission. MC17 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word not followed by a contiguous data word (missing data word) Mode code command word followed by data word with Manchester encoding or parity error (bad data word) No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) DBAC bit set. BCAST bit updated. DPB bit toggles. MERR bit set. IWDERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) MERR IWA IBR MERR IWA IBR * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 135 HI-6120, HI-6121 Circumstances for Received Message Terminal Response to Received Command Default response: Status is not updated. Transmit Status Word from the previous command, with data word containing the last valid command word (assuming it was not a “Transmit Status” or a “Transmit Last Command” mode command. Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options TRANSMIT LAST COMMAND (MC18): Mode code command with mode code 10010 and T/R bit equals 1 Normal CS update: BUSID bit updated. DBAC bit reset. MERR bit reset. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (All error bits reset.) IWA Transmitted data word is automatically provided from an internal register, and is copied to assigned index or pingpong buffer (or to Descriptor Word 4 for SMCP Simplified Mode Command Processing) MC18 EXCEPTIONS: Broadcast address RT31 (broadcast not allowed) Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No Status Word transmit. Set the Message Error (ME) and BCR status bits. No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. DBAC bit set. BCAST bit set. DPB toggles. MERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) MERR IWA IBR No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA IBR * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 136 HI-6120, HI-6121 Circumstances for Received Message Terminal Response to Received Command Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options Default response: Reset Message Error (ME) and TRANSMIT BIT WORD BCR status bits. then (MC19): transmit Status Word Mode code command followed by data word from with mode code either BIT Word Register or 10011 Alternate BIT Word Register, and T/R bit equals 1 depending on Configuration Reg. 2 option bit ALTBITW. Normal CS update: BUSID bit reset. DBAC bit reset. MERR bit reset. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (All error bits reset.) IWA Transmitted data word is automatically copied to the assigned index or ping-pong buffer (or to Descriptor Word 4 for SMCP Simplified Mode Command Processing) MC19 EXCEPTIONS: Broadcast address RT31 (broadcast not allowed) Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word is followed by a contiguous data word No Status Word transmit. Set the Message Error (ME) and BCR status bits. No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. DBAC bit set. BCAST bit set. DPB toggles. MERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) MERR IWA IBR No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR MERR bit set. WCTERR bit set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (Other error bits reset.) MERR IWA IBR * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 137 HI-6120, HI-6121 Circumstances for Received Message Terminal Response to Received Command Default response: Reset Message Error (ME) status. and transmit Status Word. If broadcast, set BCR status bit and suppress Status response. This command is intended for use in 1553 systems with more than one dual redundant bus. Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options SELECTED TRANSMITTER SHUTDOWN (MC20): Mode code command with mode code 10100 and T/R bit equals 1 Normal CS update: BUSID bit updated. DBAC bit reset. MERR bit reset. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (All error bits reset.) IWA After Status Word transmission, the device stores received data word in the assigned index or ping-pong buffer (or in Descriptor Word 4 if SMCP Simplified Mode Command Processing applies). If the MCOPT4 bit in Configuration Register 2 equals 0, the received data word is compared to the value in the Bus Select Register corresponding to the inactive bus. For example, if the command is received on Bus A, the comparison uses the Bus B Select Register value. If the compared values match, the device automatically shuts down either transmit and receive or transmit only for the inactive bus, depending on the state of the SDSEL bit in Configuration Register 2. (See description of SDSEL and MCOPT4 bits in Configuration Register 2 for further information. When a bus transmitter (or transmitter and receiver) is shut down by this mode command, bus status is reflected by assertion of a TXASD or TXBSD bit in the Built-In Test Register at register address 0x0014. If SDSEL equals logic 0, an RXASD or RXBSD bit will also be asserted. See Built-In Test Register description for further information. If MCOPT4 bit in Configuration Register 2 equals 1, the IWA interrupt is typically used to alert the host when an MC20 command is received. The host must evaluate whether the received mode data word matches the bus selection criteria. If bus selection criteria is met, the host fulfills bus shutdown command using one of two options: 1. set the bus shutdown bit INHBUSA or INHBUSB for the inactive bus in Configuration Register 1 to inhibit both transmit and receive, OR 2. assert the transmit shutdown input pin TXINHA or TXINHB for the inactive bus to inhibit only transmit. The inactive bus receiver is still active and all valid commands are heeded without transmit. This option is rarely applied. Once shutdown, the inactive bus transmitter (or transmitter and receiver) can only be reactivated by an “Override Transmitter Shutdown” MC5 or MC21 or “Reset Remote Terminal” MC8 mode code command, or by software reset (by setting the SRST bit in Configuration Register 1) or by hardware reset initiated by asserting the MR master reset input pin. MC20 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) No Message Info Word is written No Change None HOLT INTEGRATED CIRCUITS 138 HI-6120, HI-6121 Circumstances for Received Message T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word not followed by a contiguous data word (missing data word) Mode code command word followed by data word with Manchester encoding or parity error (bad data word) Terminal Response to Received Command Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated. DPB bit toggles. Bits Updated in Data Buffer Msg Info Word Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) MERR bit set. WCTERR bit updated. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) MERR bit set. IWDERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) Interrupt Options IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. ILCMD IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. MERR IWA IBR No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. DBAC bit set. BCAST bit updated. DPB bit toggles. MERR IWA IBR * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 139 HI-6120, HI-6121 Circumstances for Received Message OVERRIDE SELECTED TRANSMITTER SHUTDOWN (MC21): Mode code command with mode code 10101 and T/R bit equals 1 Terminal Response to Received Command Default response: Reset Message Error (ME) status. and transmit Status Word. If broadcast, set the BCR status bit and suppress Status response. Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options Normal CS update: BUSID bit updated. DBAC bit reset. MERR bit reset. BCAST bit reset. ILCMD bit reset. DPB bit toggles. RTRT bit reset. (All error bits reset.) IWA After Status Word transmission, the device stores received data word in the assigned index or ping-pong buffer (or in Descriptor Word 4 if SMCP Simplified Mode Command Processing applies). If the MCOPT4 bit in Configuration Register 2 equals 0, the received data word is compared to the value in the Bus Select Register corresponding to the inactive bus. For example, if the command is received on Bus A, the comparison uses the Bus B Select Register value. If the compared values match, the device automatically re-enables transmit and receive for the inactive bus, regardless of the state of the SDSEL bit in Configuration Register 2. The device affirms fully reenabled bus status by resetting all four TXASD, TXBSD, RXASD and/ or RXBSD bits in the Built-In Test Register at register address 0x0014. Note: If the TXINHA or TXINHB input pins are asserted, the device cannot override the resulting hardware transmit inhibit for the affected bus. In this case, the corresponding TXASD and/or TXBSD bits remain high. See Built-In Test Register description for further information. If MCOPT4 bit in Configuration Register 2 equals 1, the IWA interrupt is typically used to alert the host when an MC21 command is received. The host must evaluate whether the received mode data word matches the bus selection criteria. If bus selection criteria is met, the host fulfills the “override shutdown” command using one of two options: 1. reset the bus shutdown bit INHBUSA or INHBUSB for the inactive bus in Configuration Register 1 to reenable both transmit and receive, if the host used this bit to shut down transmit and receive for an earlier MC4 or MC20 command. (Resetting this shutdown bit does not restore bus transmit capability if a TXINHA or TXINHB input pin is asserted.) OR 2. reset the transmit shutdown input pin TXINHA or TXINHB for the inactive bus to re-enable transmit if the host used this pin to shut down transmit only for an earlier MC4 or MC20 command. MC21 EXCEPTIONS: Invalid command word. OR T/R bit equals 0 and UMCINV bit in Config. Register 1 equals 1 *** T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 0 * No terminal response, the message is ignored. No Status Word change. (mode code is undefined when T/R bit equals 0) Respond “In form”: Reset Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, set the BCR status bit and suppress status response. No Message Info Word is written Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) No Change None DBAC bit set. BCAST bit updated. DPB bit toggles. IWA IBR HOLT INTEGRATED CIRCUITS 140 HI-6120, HI-6121 Circumstances for Received Message T/R bit equals 0 AND UMCINV bit in Config. Register 1 equals 0. The Illegalization Table bit equals 1 ** Mode code command word not followed by a contiguous data word (missing data word) Mode code command word followed by data word with Manchester encoding or parity error (bad data word) Terminal Response to Received Command Set Message Error (ME) status. If not broadcast, transmit Status Word. If broadcast, also set Status Word BCR bit and suppress Status response. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated. DPB bit toggles. Bits Updated in Data Buffer Msg Info Word ILCMD bit set. MERR bit set. BUSID bit updated. RTRT bit reset. (Other error bits reset.) MERR bit set. WCTERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) MERR bit set. IWDERR bit set. BUSID bit updated. ILCMD bit reset. RTRT bit reset. (Other error bits reset.) Interrupt Options ILCMD IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. MERR IWA IBR No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. DBAC bit set. BCAST bit updated. DPB bit toggles. MERR IWA IBR * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” *** Undefined mode command rendered invalid by UMCINV option bit. Command’s bit in Illegalization Table is “don’t care”. HOLT INTEGRATED CIRCUITS 141 HI-6120, HI-6121 Circumstances for Received Message RESERVED MODE CODES MC22 - MC31: Mode code commands having mode codes 10110 through 11111 The mode code’s bit in Illegalization Table equals 1 ** (RT is using “illegal command detection”) OR The mode code’s bit in Illegalization Table equals 0 * (RT not using “illegal command detection,” respond “in form”) Terminal Response to Received Command The reserved mode code commands do not have defined actions. Host must initialize device to respond using either of the two following methods: Mode code is illegalized. Set Message Error (ME) status and transmit Status Word. If T/R bit equals 1, suppress data word transmission. OR If T/R bit equals 1, Reset Message Error (ME) status. Transmit Status Word with contiguous data word read from assigned index or pingpong buffer (or from Descriptor Word 4 if the SMCP option applies.) If T/R bit equals 0, Reset Message Error (ME) status and transmit Status. If broadcast, also set BCR status and suppress Status transmit. Device stores received data word in assigned index or pingpong buffer (or in Descriptor Word 4 if SMCP Simplified Mode Command Processing applies). MC22 - MC31 EXCEPTIONS: Invalid command word. T/R bit equals 0 and mode code command word is not followed by a contiguous data word (missing data word) No terminal response, the message is ignored. No Status Word change. No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. No Change No Message Info Word is written MERR bit set. WCTERR bit set. BUSID bit updated. ILCMD, RTRT bits reset. (Other error bits reset.) None DBAC bit set. Normal CS update: BCAST bit reset. BUSID bit updated. DPB bit toggles. MERR bit reset. ILCMD bit reset. RTRT bit reset. (All error bits reset.) IWA DBAC bit set. ILCMD bit set. BCAST bit reset. MERR bit set. DPB bit toggles. BUSID bit updated. RTRT bit reset. (Other error bits reset.) ILCMD IWA Bits Updated in Descriptor Control Word Bits Updated in Data Buffer Msg Info Word Interrupt Options DBAC bit reset. BCAST bit updated. DPB bit toggles. Normal CS update: BUSID bit updated. MERR bit reset. ILCMD bit reset. RTRT bit reset (All error bits reset.) IWA IBR DBAC bit set. BCAST bit updated. DPB bit toggles. MERR IWA IBR HOLT INTEGRATED CIRCUITS 142 HI-6120, HI-6121 Circumstances for Received Message T/R bit equals 0 and command word is followed by data word with Manchester or parity error (bad data word) T/R bit equals 1 and mode code command word is followed by a contiguous data word Terminal Response to Received Command No Status Word transmit. Set the Message Error (ME) status bit. If broadcast, set the BCR status bit. Bits Updated in Descriptor Control Word DBAC bit set. BCAST bit updated. DPB bit toggles. Bits Updated in Data Buffer Msg Info Word MERR bit set. IWDERR bit set. BUSID bit updated. ILCMD, RTRT bits reset. (Other error bits reset.) Interrupt Options MERR IWA IBR No Status Word transmit. Set the Message Error (ME) status bit. MERR, WCTERR bits set. DBAC bit set. BUSID bit updated. BCAST bit reset. ILCMD, RTRT bits DPB bit toggles. reset. (Other error bits reset.) DBAC bit set. BCAST bit set. DPB bit toggles. MERR bit set. BUSID bit updated. ILCMD, RTRT bits reset. (Other error bits reset.) MERR IWA T/R bit equals 1 and mode code command is addressed to RT31 No Status Word transmit. Set the Message Error (ME) and BCR status bits. MERR IWA IBR * Command is illegal but terminal is not using “illegal command detection” (in form response). ** Command is illegal and terminal is using “illegal command detection” HOLT INTEGRATED CIRCUITS 143 HI-6120, HI-6121 17. ELECTRICAL CHARACTERISTICS 17.1. Absolute Maximum Ratings Supply voltage (VDD) Logic input voltage range Receiver differential voltage Driver peak output current Power dissipation at 25°C Solder Temperature Junction Temperature Storage Temperature -0.3 V to +5.0 V -0.3 V to +3.6 V 10 Vp-p +1.0 A 1.0 W 275oC for 10 sec. 175oC -65oC to +150oC 17.2. Recommended Operating Conditions Operating Supply voltage (VDD) Industrial Extended 3.3 VDC ± 5% Operating Temperature Range -40oC to +85oC -55oC to +125oC NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. 17.3. DC Electrical Characteristics VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise stated) Parameters Operating Voltage Symbol VDD ICC1 Test Conditions Limits Min 3.15 - Typ 3.3 4 Max 3.45 10 Unit V mA Not Transmitting Continuous supply current while one bus transmits @ 100% duty cycle, 70Ω resistive load Not Transmitting Transmit one bus @ 100% duty cycle, 70Ω resistive load Digital Inputs Digital Inputs Digital Inputs Digital Inputs Digital Inputs and Data Bus IOUT = -1.0mA, Digital outputs IOUT = 1.0mA, Digital outputs Power Supply Current See Note 1 on next page ICC2 PD1 PD2 VIH VIL IIH IIL IPUD VOH VIH - 720 760 mA Power Dissipation See Note 2 on next page Min. Input Voltage (HI) Max. Input Voltage (LO) Min. Input Current (HI) Max. Input Current (LO) Pull Up / Pull Down Current Min. Output Voltage (HI) Max. Output Voltage (LO) 70% -20 90% - 420 275 - 60 550 30% 20 10% mW mW VDD VDD IDD IDD IDD VDD VDD RECEIVER (Measured at Point “AD” in Figure 26 unless otherwise specified) Input Resistance Input Capacitance Common Mode Rejection Ratio Input Level RIN CIN CMRR VIN Differential Differential Differential 20 40 5 9 kΩ pF dB Vp-p HOLT INTEGRATED CIRCUITS 144 HI-6120, HI-6121 Parameters Input Common Mode Voltage Threshold Voltage (Direct-Coupled) Threshold Voltage (Transformer-Coupled) Detect No Detect Detect No Detect Symbol VICM VTHD VTHND VTHD VTHND Test Conditions Limits Min -5 1.15 0.86 - Typ - Max +5 20.0 0.28 14.0 0.2 Unit V-pk Vp-p Vp-p Vp-p Vp-p 1 Mhz Sine Wave (Measured at Point “AD“ in Figure 26) 1 Mhz Sine Wave (Measured at Point “AT“ in Figure 27) TRANSMITTER (Measured at Point “AD” in Figure 26 unless otherwise specified) Direct Coupled Output Voltage Transformer Coupled VOUT VOUT VON Direct Coupled Output Dynamic Offset Voltage Transformer Coupled VDYN VDYN ROUT COUT 35Ω Load 70Ω Load (Measured at Point “AT“ in Figure 27) Differential, inhibited 35Ω Load 70Ω Load (Measured at Point “AT“ in Figure 27) Differential, not transmitting 1 MHz sine wave 6.0 18.0 -90 -250 10 9.0 27.0 10.0 90 250 15 Vp-p Vp-p mVp-p mV mV kΩ pF Output Noise Output Resistance Output Capacitance Note 1: In actual use, the highest practical transmit duty cycle is 96%, occurring when a Remote Terminal responds to a series of 32 data word transmit commands (RT to BC) repeating with minimum intermessage gap of 4μs (2μs dead time) and typical HI6110 RT response delay of 5μs. Note 2: While one bus continuously transmits, the power delivered by the 3.3V power supply is 3.3V × 720mA typical = 2.4W. Of this, 420mW is dissipated in the device, the remainder in the load. 17.4. AC Electrical Characteristics ― HI-6121 Host Bus Interface Timing VDD = 3.3V, GND = 0V, TA = Operating Temperature Range (unless otherwise stated) Limits Min Typ Max Parameters HI-6121 INTERFACE TIMING (SPI Host Bus Interface) SCK clock Period CE set-up time to first SCK rising edge CE hold time after last SCK falling edge CE inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SCK high time SCK low time SO valid after SCK falling edge SO high-impedance after CE inactive Symbol Units tCYC tCES tCEH tCPH tDS tDH tSCKH tSCKL tDV tCHZ 50 25 25 100 10 10 25 100 - - 20 75 ns ns ns ns ns ns ns ns ns ns HOLT INTEGRATED CIRCUITS 145 HI-6120, HI-6121 SERIAL INPUT TIMING DIAGRAM t CPH CE t CEH t CES SCLK t DS SI MSB t DH LSB SERIAL OUTPUT TIMING DIAGRAM t CPH CE SCLK SO t SCKH t SCKL t DV t CHZ MSB LSB Hi Impedance Hi Impedance Figure 21. HI-6121 Host Bus Interface Timing Diagram 17.5. AC Electrical Characteristics ― HI-6120 Host Bus Interface Timing Parameters HI-6120 INTERFACE TIMING (Parallel Host Bus Interface) Write cycle Read/Write inactive time Non-sequential read time 8-bit sequential read time 16-bit sequential read time Wait assertion time Wait time tWR tINACT tNSR tSR8 tSR16 tWAS tW 55 25 110 55 65 20 130 ns ns ns ns ns ns ns Symbol Limits Min Typ Max Units HOLT INTEGRATED CIRCUITS 146 HI-6120, HI-6121 HOST WRITE IN DUAL-BYTE MODE (8-BIT BUS WIDTH) using BTYPE = 1 (“Intel Style” - OE Output Enable and WE Write Enable) showing 2 bytes written for a single 16-bit word A15:1 A0 LB CS OE WE WAIT D7:0 BYTE 0 BYTE 1 tWR tINACT tWR tINACT OE or WE assertion for the next Read or Write ADDRESS All timing intervals equal 0 ns MIN unless otherwise indicated. HOST WRITE IN WORD MODE (16-BIT BUS WIDTH) using BTYPE = 1 (”Intel Style” - OE Output Enable and WE Write Enable) showing a one-word write cycle. Successive writes to sequential addresses have same timing. A15:1 CS OE WE WAIT D15:0 ADDRESS tINACT tWR OE or WE assertion for the next Read or Write WORD All timing intervals equal 0 ns MIN unless otherwise indicated. Figure 22. Register and RAM Write Operations for BTYPE = 1 HOLT INTEGRATED CIRCUITS 147 HI-6120, HI-6121 HOST WRITE IN DUAL-BYTE MODE (8-BIT BUS WIDTH) using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe STR and R/W Direction Select) showing 2 bytes written for a single 16-bit word A15:1 A0 LB CS R/W STR WAIT D7:0 BYTE 0 BYTE 1 tWR tINACT tWR tINACT STR assertion for the next Read or Write ADDRESS All timing intervals equal 0 ns MIN unless otherwise indicated. HOST WRITE IN WORD MODE (16-BIT BUS WIDTH) using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe STR and R/W Direction Select) showing a one-word write cycle. Successive writes to sequential addresses have same timing. A15:1 CS R/W STR WAIT D15:0 WORD All timing intervals equal 0 ns MIN unless otherwise indicated. tWR tINACT STR assertion for the next Read or Write ADDRESS Figure 23. Register and RAM Write Operations for BTYPE = 0 HOLT INTEGRATED CIRCUITS 148 HI-6120, HI-6121 HOST READ IN DUAL-BYTE MODE (8-BIT BUS WIDTH) using BTYPE = 1 (”Intel Style” - OE Output Enable and WE Write Enable) showing 2 bytes read for a single 16-bit word A15:1 A0 LB CS WE OE WAIT D7:0 tWAS tNSR tINACT tSR8 tINACT WE or OE assertion for the next Write or Read ADDRESS tW High-Z BYTE 0 High-Z BYTE 1 High-Z All timing intervals equal 0 ns MIN unless otherwise indicated. After first byte is read, prefetch allows faster access times for successive reads, as long as addresses are sequential. WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted. HOST READ IN WORD MODE (16-BIT BUS WIDTH) using BTYPE = 1 (”Intel Style” - OE Output Enable and WE Write Enable) showing two successive words read from sequential addresses ADDRESS ADDRESS + 1 A15:1 CS WE OE WAIT D15:0 tWAS tINACT tNSR tINACT tSR16 WE or OE assertion for the next Write or Read tW High-Z WORD High-Z WORD High-Z All timing intervals equal 0 ns MIN unless otherwise indicated. After first word is read, prefetch allows faster access times for successive reads, as long as addresses are sequential. WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted. Figure 24. Register and RAM Read Operations for BTYPE = 1 HOLT INTEGRATED CIRCUITS 149 HI-6120, HI-6121 HOST READ IN DUAL-BYTE MODE (8-BIT BUS WIDTH) using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe STR and R/W Direction Select) showing 2 bytes read for a single 16-bit word A15:1 A0 LB CS R/W STR WAIT D7:0 tWAS tNSR tINACT tSR8 tINACT STR assertion for the next Read or Write ADDRESS tW High-Z BYTE 0 High-Z BYTE 1 High-Z All timing intervals equal 0 ns MIN unless otherwise indicated. After first byte is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential. WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted. HOST READ IN WORD MODE (16-BIT BUS WIDTH) using BTYPE = 0 (”Motorola Style” - Single Read/Write Strobe STR and R/W Direction Select) showing two successive words read from sequential addresses A15:1 CS R/W STR WAIT D15:0 tWAS tW tNSR tINACT tSR16 tINACT STR assertion for the next Read or Write ADDRESS ADDRESS + 1 High-Z WORD High-Z WORD High-Z All timing intervals equal 0 ns MIN unless otherwise indicated. After first word is read, prefetch allows faster access times for successive reads, as long as read addresses are sequential. WAIT is always asserted during the first read cycle, is never asserted for successive read cycles to sequential adresses. This allows default host bus configuration for the HI-6120 chip select to match the timing characteristics of the faster successive cycles, while the slower initial cycle is handled on a WAIT-controlled exception basis. WAIT can be optionally inverted. Figure 25. Register and RAM Read Operations for BTYPE = 0 HOLT INTEGRATED CIRCUITS 150 HI-6120, HI-6121 18. MIL-STD-1553 BUS INTERFACE TRANSMITTER Tx Data from Manchester Encoder TXINHA/B BUSA/B 1:2.5 55Ω 35Ω BUSA/B Isolation Transformer 2.5:1 55Ω Point “AD” 55Ω Point “AD” 35Ω 55Ω RECEIVER Rx Data to Manchester Decoder Isolation Transformer Figure 26. MIL-STD-1553 Direct Coupled Test Circuits TRANSMITTER Tx Data from Manchester Encoder TXINHA/B 52.5Ω (.75 Zo) 35Ω (.5 Zo) 52.5Ω (.75 Zo) Coupling Transformer 1.4:1 BUSA/B 1:2.5 Point “AT” 1:1.4 52.5Ω (.75 Zo) 35Ω (.5 Zo) BUSA/B Isolation Transformer Point “AT” 2.5:1 Coupling Transformer 52.5Ω (.75 Zo) RECEIVER Rx Data to Manchester Decoder Isolation Transformer Figure 27. MIL-STD-1553 Transformer Coupled Test Circuits HOLT INTEGRATED CIRCUITS 151 HI-6120, HI-6121 19. THERMAL CHARACTERISTICS Part Number HI-6120PQx HI-6121PQx Package Style 100-pin PQFP 52-pin PQFP Condition Mounted on circuit board Mounted on circuit board Heat sink pad unsoldered Heat sink pad soldered θja ( C/W) 52.7 60.9 31.1 22.8 o Junction Temp, Tj (oC) TA = 25oC 56 56 41 37 TA = 85oC 116 116 101 97 TA = 125oC 156 156 141 137 HI-6121PCx 64-pin QFN 20. ADDITIONAL PIN / PACKAGE CONFIGURATIONS Notes: 1. All VCC, VCCP and GND pins must be connected. 2. See page 1 for HI-6121, 52-Pin PQFP Package Configuration. 20.1. HI-6121PCx (64-pin QFN) 64 VCC 63 TXINHB 62 TXINHA GND COMP CE MODE SI SCK SO VCC MCLK GND RTA0 RTA1 RTA2 MR RTA3 RTA4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 61 60 59 58 57 56 55 54 53 52 51 50 49 48 BENDI 47 TEST 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LOCK MTSTOFF BUSA VCCP VCCP BUSA BUSB VCCP VCCP BUSB TEST0 TEST1 TEST2 TEST3 RTAP MISO MOSI VCC VCC GND GND ECS EECOPY ESCK EE1K TEST7 TEST6 TEST5 TEST4 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 HOLT INTEGRATED CIRCUITS 152 AUTOEN VCC GND SSYSF ACTIVE READY TTCLK ACKMES ACKHW INTHMES INTHW VCC GND HI-6121PCx TOP VIEW HI-6120, HI-6121 20.2. HI-6120PQx (100-pin QFN) 100 - D11 99 - D10 98 - D9 97 - TXINHB 96 - TXINHA 95 - AUTOEN 94 - D8 93 - D7 92 - D6 91 - VCC 90 - GND 89 - D5 88 - D4 87 - D3 86 - SSYSF 85 - ACTIVE 84 - READY 83 - TTCLK 82 - ACKMES 81 - ACKHW 80 - INTMES 79 - INTHW 78 - VCC 77 - GND 76 - D2 VCC - 1 GND - 2 D12 - 3 D13 - 4 D14 - 5 D15 - 6 COMP - 7 CE - 8 MODE - 9 STR - 10 VCC - 11 BTYPE - 12 MCLK - 13 GND - 14 WAIT - 15 R / W - 16 RTA0 - 17 RTA1 - 18 RTA2 - 19 MR - 20 RTA3 - 21 RTA4 - 22 A0 - 23 A1 - 24 A2 - 25 75 - D1 74 - D0 73 - BENDI 72 - TEST 71 - LOCK 70 - MTSTOFF 69 - BUSA 68 - BUSA 67 - VCCP 66 - VCCP 65 - BUSA 64 - BUSA 63 - BUSB 62 - BUSB 61 - VCCP 60 - VCCP 59 - BUSB 58 - BUSB 57 - TEST0 56 - TEST1 55 - TEST2 54 - TEST3 53 - BWID 52 - WPOL 51 - A15 A3 - 26 A4 - 27 A5 - 28 A6 - 29 RTAP - 30 MISO - 31 MOSI - 32 A7 - 33 A8 - 34 A9 - 35 VCC - 36 GND - 37 ECS - 38 EECOPY - 39 ESCK - 40 A10 - 41 A11 - 42 A12 - 43 EE1K - 44 TEST7 - 45 TEST6 - 46 TEST5 - 47 TEST4 - 48 A13 - 49 A14 - 50 TOP VIEW HOLT INTEGRATED CIRCUITS 153 HI-6120, HI-6121 21. ORDERING INFORMATION HI - 6120 PQ x x PART NUMBER Blank F PART NUMBER I T M PART NUMBER PQ LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE -40 C to +85 C -55oC to +125oC -55 C to +125 C PACKAGE DESCRIPTION 100 PIN PLASTIC QUAD FLAT PACK, PQFP (100PQS) o o o o FLOW I T M BURN IN No No Yes HI - 6121 Px x x PART NUMBER Blank F PART NUMBER I T M PART NUMBER PC PQ LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE -40 C to +85 C -55oC to +125oC -55 C to +125 C PACKAGE DESCRIPTION 64 PIN PLASTIC CHIP-SCALE PACKAGE, 9 x 9mm QFN (64PCS) 52 PIN PLASTIC QUAD FLAT PACK, PQFP (52PTQS) o o o o FLOW I T M BURN IN No No Yes HOLT INTEGRATED CIRCUITS 154 HI-6120, HI-6121 22. REVISION HISTORY Revision DS6120, Rev. NEW Date 11/24/09 Description of Change Initial Release Datasheet format change (Table of Contents, List of Figures, List of Tables and crossreferences added). Inserted new sections to clarify Data Prefetch operations. Minor typos corrected. Rev. B 11/18/10 Corrected Power Supply Current and device Power Dissipation values and added explanatory notes. Rev. A 6/15/10 HOLT INTEGRATED CIRCUITS 155 HI-6120, HI-6121 23. PACKAGE DIMENSIONS 52-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: 52PTQS .0256 BSC (.65) .520 BSC SQ (13.2) .394 BSC SQ (10.0) .015 ± .003 (.375 ± .075) .035 ± .006 (.88 ± .15) .063 typ (1.6) See Detail A .063 MAX. (1.6) .055 ± .002 (1.4 ± .05) .008 min (.20) .005 (.13) R min 0° 7° BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .005 R min (.13) DETAIL A 64-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) Heat sink pad on bottom of package. Heat sink must be left floating or connected to VDD. DO NOT connect to GND. inches (millimeters) Package Type: 64PCS .354 BSC (9.00) .281 ± .006 (7.15 ± .15) .0197 BSC (0.50) .354 BSC (9.00) Top View .281 ± .006 (7.15 ± .15) Bottom View .010 typ (0.25) .016 ± .004 (0.40 ± .10) .008 typ (0.20) .039 max (1.00) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 156 HI-6120, HI-6121 100-PIN PLASTIC QUAD FLAT PACK (PQFP) inches (millimeters) Package Type: 100PQS .0197 BSC (0.50) .630 BSC SQ (16.0) .551 BSC SQ (14.0) .009 ± .002 (.22 ± .05) .024 ± .006 (.60 ± .15) .039 typ (1.0) .008 min (0.20) .008 R max (0.20) See Detail A .059 ± .004 (1.50 ± .10) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .055 ± .002 (1.40 ± .05) .003 R min (0.08) 0° 7° Detail A HOLT INTEGRATED CIRCUITS 157