HI-8282

HI-8282 September 2006 ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER FEATURES ! ARINC specification 429 compliant ! 16-Bit parallel data bus ! Direct receiver interface to ARINC bus ! Timing control 10 times the data rate ! Selectable data clocks ! Receiver error rejection per ARINC specification 429 ! Automatic transmitter data timing ! Self test mode ! Parity functions ! Low power, single 5 volt supply ! Industrial & full military temperature ranges GENERAL DESCRIPTION The HI-8282 is a silicon gate CMOS device for interfacing the ARINC 429 serial data bus to a 16-bit parallel data bus. Two receivers and an independent transmitter are provided. The receiver input circuitry and logic are designed to meet the ARINC 429 specifications for loading, level detection, timing, and protocol. The transmitter section provides the ARINC 429 communication protocol. An external line driver such as the Holt HI-8585 or HI-3182 is required to translate the 5 volt logic outputs to ARINC 429 drive levels. The 16-bit parallel data bus exchanges the 32-bit ARINC data word in two steps when either loading the transmitter or interrogating the receivers. The data bus interfaces with CMOS and TTL. Timing of all the circuitry begins with the master clock input, CLK. For ARINC 429 applications, the master clock frequency is 1 MHz. Each independent receiver monitors the data stream with a sampling rate 10 times the data rate. The sampling rate is software selectable at either 1MHz or 125KHz. The results of a parity check are available as the 32nd ARINC bit. The HI-8282 examines the null and data timings and will reject erroneous patterns. For example, with a 125 KHz clock selection, the data frequency must be between 10.4 KHz and 15.6 KHz. The transmitter has a First In, First Out (FIFO) memory to store 8 ARINC words for transmission. The data rate of the transmitter is software selectable by dividing the master clock, CLK, by either 10 or 80. The master clock is used to set the timing of the ARINC transmission within the required resolution. ! DSCC SMD part number PIN CONFIGURATION (Top View) Vcc (REC. 1 INPUT) 429DI1(A) (REC.1 INPUT) 429DI1(B) (REC. 2 INPUT) 429DI2(A) (REC. 2 INPUT) 429DI2(B) (REC.1 DATA FLAG) D/R1 (REC.2 DATA FLAG) D/R2 (REC. BYTE SELECT) SEL (REC. 1 OUTPUT ENABLE) EN1 (REC. 2 OUTPUT ENABLE) EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC MR CLK NC NC CWSTR (CONTROL WORD STROBE) ENTX (ENABLE XMIT) 429DO (XMIT DATA) 429DO (XMIT DATA) TX/R PL2 PL1 BD00 BD01 BD02 BD03 BD04 BD05 GND (XMIT READY FLAG) (XMIT BYTE 2 LE) (XMIT BYTE 1 LE) (MASTER RESET) (MASTER CLK IN) TX CLK (XMIT CLOCK OUT) APPLICATIONS ! Avionics data communication ! Serial to parallel conversion ! Parallel to serial conversion HI-8282C / CT / CM-01 / CM-03 SMD # 5962-8688002QA 40-Pin Ceramic Side-Brazed DIP (See page 10 for additional Package Pin Configurations) (DS8282 Rev. E) HOLT INTEGRATED CIRCUITS www.holtic.com 09/06 HI-8282 PIN DESCRIPTION SYMBOL VCC 429DI1 (A) 429DI1 (B) 429DI2 (A) 429DI2 (B) D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 GND BD05 BD04 BD03 BD02 BD01 BD00 PL1 PL2 TX/R 429DO 429DO ENTX CWSTR CLK TX CLK MR FUNCTION POWER INPUT INPUT INPUT INPUT OUTPUT OUTPUT INPUT INPUT INPUT I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O POWER I/O I/O I/O I/O I/O I/O INPUT INPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT OUTPUT INPUT +5V ±5% DESCRIPTION ARINC receiver 1 positive input ARINC receiver 1 negative input ARINC receiver 2 positive input ARINC receiver 2 negative input Receiver 1 data ready flag Receiver 2 data ready flag Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2) Data Bus control, enables receiver 1 data to outputs Data Bus control, enables receiver 2 data to outputs if EN1 is high Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus 0V Data Bus Data Bus Data Bus Data Bus Data Bus Data Bus Latch enable for byte 1 entered from data bus to transmitter FIFO. Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1. Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high after transmission and FIFO empty. "ONES" data output from transmitter. "ZEROES" data output from transmitter. Enable Transmission Clock for control word register Master Clock input Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80. Master Reset, active low HOLT INTEGRATED CIRCUITS 2 HI-8282 FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-8282 contains 10 data flip flops whose D inputs are connected to the data bus and clocks connected to CWSTR. Each flip flop provides options to the user as follows: DATA BUS ARINC 429 DATA FORMAT The following table shows the bit positions in exchanging data with the receiver or the transmitter. ARINC bit 1 is the first bit transmitted or received. BYTE 1 BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 13 12 11 10 9 31 30 32 1 2 3 4 5 6 7 8 DATA BUS PIN BDO5 FUNCTION CONTROL DESCRIPTION If enabled, an internal connection is made passing 429DO and 429DO to the receiver logic inputs If enabled, ARINC bits 9 and, 10 must match the next two control word bits If Receiver 1 Decoder is enabled, the ARINC bit 9 must match this bit If Receiver 1 Decoder is enabled, the ARINC bit 10 must match this bit If enabled, ARINC bits 9 and 10 must match the next two control word bits If Receiver 2 Decoder is enabled, then ARINC bit 9 must match this bit If Receiver 2 Decoder is enabled, then ARINC bit 10 must match this bit Logic 0 enables normal odd parity and Logic 1 enables even parity output in transmitter 32nd bit CLK is divided either by 10 or 80 to obtain XMTR data clock CLK is divided either by 10 or 80 to obtain RCVR data clock ARINC BIT SELF TEST 0 = ENABLE BYTE 2 DATA BUS ARINC BIT BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 BDO6 RECEIVER 1 DECODER 1 = ENABLE BDO7 - - THE RECEIVERS ARINC BUS INTERFACE Figure 1 shows the input circuit for each receiver. The ARINC 429 specification requires the following detection levels: BDO8 - - BDO9 RECEIVER 2 DECODER 1 = ENABLE BD10 - - STATE ONE NULL ZERO DIFFERENTIAL VOLTAGE +6.5 Volts to +13 Volts +2.5 Volts to -2.5 Volts -6.5 Volts to -13 Volts BD11 - - BD12 INVERT XMTR PARITY XMTR DATA CLK SELECT RCVR DTA CLK SELECT 1 = ENABLE The HI-8282 guarantees recognition of these levels with a common mode Voltage with respect to GND less than ±4V for the worst case condition (4.75V supply and 13v signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. BD13 0 = ÷10 1 = ÷80 0 = ÷10 1 = ÷80 BD14 vcc 429DI1 (A) OR DIFFERENTIAL AMPLIFIERS COMPARATORS ONES 429DI2 (A) GND NULL vcc 429DI1 (B) OR ZEROES 429DI2 (B) GND FIGURE 1. ARINC RECEIVER INPUT HOLT INTEGRATED CIRCUITS 3 HI-8282 FUNCTIONAL DESCRIPTION (cont.) RECEIVER LOGIC OPERATION Figure 2 shows a block diagram of the logic section of each receiver. BIT TIMING The ARINC 429 specification contains the following timing specification for the received data: HIGH SPEED LOW SPEED 100K BPS ± 1% 12K -14.5K BPS BIT RATE 10 ± 5 µsec PULSE RISE TIME 1.5 ± 0.5 µsec 10 ± 5 µsec PULSE FALL TIME 1.5 ± 0.5 µsec 5 µsec ± 5% 34.5 to 41.7 µsec PULSE WIDTH The HI-8282 accepts signals that meet these specifications and rejects outside the tolerances. The way the logic operation achieves this is described below: 1. Key to the performance of the timing checking logic is an accurate 1MHz clock source. Less than 0.1% error is recommended. 2. The sampling shift registers are 10 bits long and must show three consecutive Ones, Zeros or Nulls to be considered valid data. Additionally, for data bits, the One or Zero in the upper bits of the sampling shift registers must be followed by a Null in the lower bits within the data bit time. For a Null in the word gap, three consecutive Nulls must be found in both the upper and lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed. 3. Each data bit must follow its predecessor by not less than 8 samples and no more than 12 samples. In this manner the bit rate is checked. With exactly 1MHz input clock frequency, the acceptable data bit rates are as follows: HIGH SPEED DATA BIT RATE MIN DATA BIT RATE MAX 83K BPS 125K BPS LOW SPEED 10.4K BPS 15.6K BPS 4. The Word Gap timer samples the Null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. If the Null is present, the Word Gap counter is incremented. A count of 3 will enable the next reception. RECEIVER PARITY The receiver parity circuit counts Ones received, including the parity bit, ARINC bit 32. If the result is odd, then "0" will appear in the 32nd bit. RETRIEVING DATA Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). If the receiver decoder is enabled and the 9th and 10th ARINC bits match the control word program bits or if the receiver decoder is disabled, then EOS clocks the data ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The data flag for a receiver will remain low until after both ARINC bytes from that receiver are retrieved. This is accomplished by activating EN with SEL, the byte selector, low to retrieve the first byte and activating EN with SEL high to retrieve the second byte. EN1 retrieves data from receiver 1 and EN2 retrieves data from receiver 2. If another ARINC word is received and a new EOS occurs before the two bytes are retrieved, the data is overwritten by the new word. TO PINS SEL EN D/R DECODER CONTROL BITS MUX CONTROL 32 TO 16 DRIVER CONTROL BIT BD14 CLOCK OPTION CLOCK CLK / LATCH ENABLE CONTROL BITS 9 & 10 32 BIT LATCH BIT COUNTER AND END OF SEQUENCE 32 BIT SHIFT REGISTER DATA PARITY CHECK 32ND BIT BIT CLOCK EOS EOS ONES WORD GAP WORD GAP TIMER BIT CLOCK SHIFT REGISTER START END NULL SHIFT REGISTER SEQUENCE CONTROL ZEROS SHIFT REGISTER ERROR ERROR DETECTION CLOCK FIGURE 2. RECEIVER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 4 HI-8282 FUNCTIONAL DESCRIPTION (cont.) TRANSMITTER A block diagram of the transmitter section is shown in Figure 3. TRANSMITTER PARITY The parity generator counts the ONES in the 31-bit word. If the BD12 control word bit is set low, the 32nd bit transmitted will make parity odd. If the control bit is high, the parity is even. FIFO OPERATION The FIFO is loaded sequentially by first pulsing PL1 to load byte 1 and then PL2 to load byte 2. The control logic automatically loads the 31 bit word in the next available position of the FIFO. If TX/R, the transmitter ready flag, is high (FIFO empty), then 8 words, each 31 bits long, may be loaded. If TX/R is low, then only the available positions may be loaded. If all 8 positions are full, the FIFO ignores further attempts to load data. SELF TEST If the BD05 control word bit is set low, the digital outputs of the transmitter are internally connected to the logic inputs of the receivers, bypassing the analog bus interface circuitry. Data to Receiver 1 is as transmitted and data to Receiver 2 is the complement. All data transmitted during self test is also present on the TXA(OUT) and TXB(OUT) line driver outputs. SYSTEM OPERATION The two receivers are independent of the transmitter. Therefore, control of data exchanges is strictly at the option of the user. The only restrictions are: 1. The received data may be overwritten if not retrieved within one ARINC word cycle. 2. The FIFO can store 8 words maximum and ignores attempts to load addition data if full. 3. Byte 1 of the transmitter data must be loaded first. 4. Either byte of the received data may be retrieved first. Both bytes must be retrieved to clear the data ready flag. 5. After ENTX, transmission enable, goes high it cannot go low until TX/R, transmitter ready flag, goes high. Otherwise, one ARINC word is lost during transmission. BIT BD12 DATA TRANSMISSION When ENTX goes high, enabling transmission, the FIFO positions are incremented with the top register loading into the data transmission shift register. Within 2.5 data clocks the first data bit appears at either 429DO or 429DO. The 31 bits in the data transmission shift register are presented sequentially to the outputs in the ARINC 429 format with the following timing: HIGH SPEED 10 Clocks 5 Clocks 5 Clocks 40 Clocks LOW SPEED 80 Clocks 40 Clocks 40 Clocks 320 Clocks ARINC DATA BIT TIME DATA BIT TIME NULL BIT TIME WORD GAP TIME The word counter detects when all loaded positions are transmitted and sets the transmitter ready flag, TX/R, high. 31 BIT PARALLEL LOAD SHIFT REGISTER BIT CLOCK PARITY GENERATOR DATA AND NULL TIMER SEQUENCER 429DO 429DO WORD CLOCK BIT AND WORD GAP COUNTER START SEQUENCE 8 X 31 FIFO ADDRESS LOAD WORD COUNTER AND FIFO CONTROL INCREMENT WORD COUNT TX/R ENTX FIFO LOADING SEQUENCER PL1 PL2 DATA BUS DATA CLOCK DATA CLOCK DIVIDER CLK TX CLK FIGURE 3. TRANSMITTER BLOCK DIAGRAM CONTROL BIT BD13 HOLT INTEGRATED CIRCUITS 5 HI-8282 FUNCTIONAL DESCRIPTION (cont.) REPEATER OPERATION he repeater mode of operation allows a data word that has been received by the HI-8282 to be placed directly into its FIFO for transmission. After a 32-bit word has been shifted into Tthe receiver shift register, the D/R flag will go low. A logic "0" is placed on the SEL line and EN is strobed. This is the same procedure as for normal receiver operation and it places the lower byte (16) of the data word on the data bus. By strobing PL1 at the same time as EN , the byte will also be placed into the transmitter FIFO. SEL is then taken high and EN is strobed again to place the upper byte of the data word on the data bus. By strobing PL2 at the same time as EN, the second byte will also be placed into the FIFO. The data word is now ready to be transmitted according to the parity programmed into the control word register. In normal operation, either byte of a received data word may be read from the receiver latches first by use of SEL input. During repeater operation however, the lower byte of the data word must be read first. This is necessary because, as the data is being read, it is also being loaded into the FIFO and the transmitter FIFO is always loaded with the lower byte of the data word first. MASTER RESET (MR) On a Master Reset data transmission and reception are immediately terminated, all three FIFOs are cleared as are the FIFO flags at the device pins and in the Status Register. The Control Register is not affected by a Master Reset. TIMING DIAGRAMS DATA RATE - EXAMPLE PATTERN 429DO ARINC BIT 429DO DATA NULL DATA NULL DATA NULL BIT 30 BIT 31 BIT 32 WORD GAP BIT 1 NEXT WORD LOADING CONTROL WORD DATA BUS VALID tCWSET tCWHLD CWSTR tCWSTR RECEIVER OPERATON ARINC DATA BIT 31 BIT 32 DATA READY FLAG D/R tD/R BYTE SELECT SEL DON'T CARE DON'T CARE tEND/R tEN tSELEN tENEN tDATAEN BYTE 1 VALID BYTE 2 VALID DON'T CARE tSELEN ENABLE BYTE ON BUS EN tENSEL tENSEL tD/REN DATA BUS tDATAEN tENDATA tENDATA HOLT INTEGRATED CIRCUITS 6 HI-8282 TIMING DIAGRAMS (cont.) TRANSMITTER OPERATION DATA BUS BYTE 1 VALID BYTE 2 VALID tDWSET PL1 tDWHLD tDWSET tDWHLD tPL21 tPL PL2 tPL12 TX/R tPL tTX/R TRANSMITTING DATA PL2 tDTX/R tPL2EN TX/R ENTX tENDAT 429DO or 429DO ARINC BIT tENTX/R DATA BIT 2 DATA BIT 32 DATA BIT 1 REPEATER OPERATION TIMING 429DI BIT 32 tEND/R D/R tD/R EN tD/REN tEN tENEN tEN tSELEN SEL DON'T CARE tENSEL DON'T CARE tENPL PL1 tPLEN tENPL tSELEN tENSEL tPLEN PL2 tTX/R TX/R tTX/REN ENTX tENTX/R tENDAT 429DO BIT 1 tDTX/R BIT 32 tNULL HOLT INTEGRATED CIRCUITS 7 HI-8282 ABSOLUTE MAXIMUM RATINGS Supply Voltage Vcc Voltage at ARINC input pins Voltage at any other pin DC Current Drain per input pin -0.3V to +7V -29V to +29V -0.3V to Vcc +0.3V 10mA Power Dissipation Operating Temperature Range: (Industrial) (Military) Storage Temperature Range: 500mW -40°C to +85°C -55°C to +125°C -65°C to +150°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Vcc = 5V ±5%, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). LIMITS PARAMETER ARINC INPUTS Differential Input Voltage: ONE ZERO NULL Differential To GND To Vcc Input Sink Input Source Differential To GND To Vcc VIH VIL VNUL RI RG RH IIH IIL CI CG CH Pins 2 to 3, 4 to 5 Pins 2 to 3, 4 to 5: Common mode voltage less than ±4V with respect to GND 6.5 -13.0 -2.5 12 12 12 10.0 -10.0 0 13.0 -6.5 2.5 V V V KW KW kW 200 -450 20 20 20 µA µA pF pF pF SYMBOL CONDITIONS MIN TYP MAX UNIT Input Resistance: 27 27 Input Current: Input Capacitance: (Guaranteed but not tested) BI-DIRECTIONAL INPUTS Input Voltage: Input Current: ALL OTHER INPUTS Input Voltage: Input Current: OUTPUTS Output Voltage: Output Current: (Bi-directional Pins) Output Current: (All Other Outputs) Output Capacitance: SUPPLY INPUT Standby Supply Current: Operating Supply Current: Input Voltage HI Input Voltage LO Input Sink Input Source VIH VIL IIH IIL 2.1 0.7 1.5 -1.5 V V µA µA Input Voltage HI Input Voltage LO Input Sink Input Source VIH VIL IIH IIL 3.5 0.7 10 -20 V V µA µA Logic "1" Output Voltage Logic "0" Output Voltage Output Sink Output Source Output Sink Output Source VOH VOL IOL IOH IOL IOH CO IOH = -1.5mA IOL = 1.8mA VOUT = 0.4V VOUT = VCC - 0.4V VOUT = 0.4V VOUT = VCC - 0.4V 2.7 0.4 3.0 1.5 3.6 1.5 15 V V mA mA mA mA pF ICC1 ICC2 20 20 mA mA HOLT INTEGRATED CIRCUITS 9 HI-8282 AC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1MHz +0.1% with 60/40 duty cycle PARAMETER CONTROL WORD TIMING Pulse Width - CWSTR Setup - DATA BUS Valid to CWSTR HIGH Hold - CWSTR HIGH to DATA BUS Hi-Z RECEIVER TIMING Delay - Start ARINC 32nd Bit to D/R LOW: High Speed Low Speed Delay - D/R LOW to EN L0W Delay - EN LOW to D/R HIGH Setup - SEL to EN L0W Hold - SEL to EN HIGH Delay - EN L0W to DATA BUS Valid Delay - EN HIGH to DATA BUS Hi-Z Pulse Width - EN1 or EN2 Spacing - EN HIGH to next EN L0W FIFO TIMING Pulse Width - PL1 or PL2 Setup - DATA BUS Valid to PL HIGH Hold - PL HIGH to DATA BUS Hi-Z Spacing - PL1 to PL2 Spacing - PL2 to PL1 Delay - PL2 HIGH to TX/R LOW TRANSMISSION TIMING Spacing - PL2 HIGH to ENTX HIGH Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed Delay - 32nd ARINC Bit to TX/R HIGH Spacing - TX/R HIGH to ENTX L0W REPEATER OPERATION TIMING Delay - EN LOW to PL LOW Hold - PL HIGH to EN HIGH Delay - TX/R LOW to ENTX HIGH Master Reset Pulse Width ARINC Data Rate and Bit Timing tENPL tPLEN tTX/REN tMR 0 0 0 400 ± 1% ns ns ns ns tPL2EN tENDAT tENDAT tDTX/R tENTX/R 0 0 25 200 400 µs µs µs ns ns tPL tDWSET tDWHLD tPL12 tPL21 tTX/R 200 110 20 0 250 840 ns ns ns ns ns ns tD/R tD/R tD/REN tEND/R tSELEN tENSEL tENDATA tDATAEN tEN tENEN 240 50 0 200 20 50 200 30 16 128 µs µs ns ns ns ns ns ns ns ns tCWSTR tCWSET tCWHLD 130 140 0 ns ns ns SYMBOL LIMITS MIN TYP MAX UNITS HOLT INTEGRATED CIRCUITS 9 HI-8282 ADDITIONAL HI-8282 PIN CONFIGURATIONS (See page 1 for the 40-pin Ceramic Side-Brazed DIP Package ) 44-PIN PLASTIC PLCC 44-PIN J-LEAD CERQUAD HI-8282J-44 HI-8282JT-44 HI-8282U HI-8282UT 44-PIN CERAMIC LCC HI-8282S HI-8282ST HI-8282SM-01 HOLT INTEGRATED CIRCUITS 10 HI-8282 ORDERING INFORMATION HI - 8282 x x - xx (Ceramic) PART NUMBER TEMPERATURE RANGE BURN IN FLOW Blank T M-01 M-03 (1) PART NUMBER -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C -55°C TO +125°C PACKAGE DESCRIPTION I T M DSCC NO NO YES YES LEAD FINISH (2) C S U 40 PIN CERAMIC SIDE BRAZED DIP 44 PIN CERAMIC LEADLESS CHIP CARRIER 44 PIN CERQUAD (not available with ‘M’ flow) Gold (‘M’ flow: solder) Gold (‘M’ flow: solder) Solder HI - 8282J x x - 44 (Plastic) PART NUMBER LEAD FINISH Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN Blank T PART NUMBER -40°C TO +85°C -55°C TO +125°C PACKAGE DESCRIPTION I T NO NO 8282J 44 PIN PLASTIC J LEAD (3) (1) Only available in ‘C’ package. SMD# 5962-8688002QA (2) Gold terminal finish is Pb-Free, RoHS compliant. (3) NOT RECOMMENDED FOR NEW DESIGNS. The newer HI-8282APJI and HI-8282APJT replaces the HI-8282J-44 and HI-8282JT-44 respectively. The HI-8282A parts are rated as Moisture Sensitive Level 1 (MSL 1) and do not require any special handling. The older HI-8282J-44 and HI-8282JT-44 are rated as MSL 3 and require dry-packaging and /or bake-out in accordance with IPC/JEDEC J-STD-020A. HOLT INTEGRATED CIRCUITS 12 11 HI-8282 PACKAGE DIMENSIONS inches (millimeters) 40-PIN CERAMIC SIDE-BRAZED DIP Package Type: 40C 2.020 MAX (51.308 MAX) .610 ± .010 (15.494 ± .254) .595 ± .010 (15.113 ± .254) .225 MAX (5.715 MAX) .050 TYP (1.270 TYP) .085 ± .009 (2.159 ± .229) .600 ± .010 (15.240 ± .254) .125 MIN (3.175 MIN) .018 TYP (.457 TYP) .100 BSC (2.540 BSC) .010 + .002/- .001 (.254 + .051/- .025) 44-PIN J-LEAD CERQUAD Package Type: 44U 2 1 44 43 .688 ± .005 (17.475 ± .127) MAX. SQ. .620 ±.012 (15.748 ± .305) .650 ± .010 (16.510 ± .254) SQ. .039 ± .005 (.990 ± .127) .019 ± .002 (.483 ± .051) .050 TYP. (1.270) .200 (5.080)MAX. .100 ± .007 (2.540 ± .178) HOLT INTEGRATED CIRCUITS 12 HI-8282 PACKAGE DIMENSIONS inches (millimeters) 44-PIN PLASTIC PLCC Package Type: 44J PIN NO. 1 .045 x 45° PIN NO. 1 IDENT .045 x 45° .050 ± .005 (1.27 ± .127) .690 ± .005 (17.526 ± .127) SQ. .653 ± .004 (16.586 ± .102) SQ. .031± .005 (.787 ± .127) .017 ± .004 (.432 ± .102) SEE DETAIL A .172 ± .008 (4.369 ± .203) .610 ± .020 (15.494± .508) .009 .011 .015 ± .002 (.381 ± .051) .020 MIN (.508 MIN) R .025 .045 DETAIL A 44-PIN CERAMIC LEADLESS CHIP CARRIER Package Type: 44S .020 INDEX (.508 INDEX) PIN 1 .040 x 45° 3 PLCS (1.016 x 45° 3 PLCS) .050 ± .005 (1.270 ± .127) .075 ± .004 (1.905 ± .101) .326 ± .006 (8.280 ± .152) PIN 1 .651 ± .011 (16.535 ± .279) SQ. .050 BSC (1.270 BSC) .009R ± .006 (.229R ±.152) .025 ± .003 (.635 ±.076) .092 ± .028 (2.336 ± .711) HOLT INTEGRATED CIRCUITS 13