HI-8585PSMF

HI-8585, HI-8586 September 2011 ARINC 429 Line Driver PIN CONFIGURATION SLP1.5 1 TX0IN 2 TX1IN 3 GND 4 DESCRIPTION The HI-8585 and HI-8586 are CMOS integrated circuits designed to directly drive the ARINC 429 bus in an 8-pin package. Two logic inputs control a differential voltage between the output pins producing a +10 volt One, a -10 volt Zero, and a 0 volt Null. The CMOS/TTL control inputs are translated to ARINC specified amplitudes using on board band-gap reference. A logic input is provided to control the slope of the differential output signal. Timing is set by on-chip resistor and capacitor and tested to be within ARINC requirements. The HI-8585 has 37.5 ohms in series with each line driver output. The HI-8586 provides the option to bypass part of the output resistance so that series resistance can be used in external protection circuitry. The HI-8585 or the HI-8586 along with the HI-8588 or the Hi-8591 line receivers offer the smallest options available to get on and off the ARINC bus. 8 V+ 7 TXBOUT 6 TXAOUT 5 V- SUPPLY VOLTAGES V+ = 12V to 15V V- = -12V to -15V FUNCTION TABLE TX1IN TX0IN SLP1.5 TXAOUT 0V -5V -5V 5V 5V 0V TXBOUT 0V 5V 5V -5V -5V 0V SLOPE N/A 10ms 1.5ms 10ms 1.5ms N/A 0 0 0 0 1 1 0 0 1 X 0 1 0 1 X FEATURES ! ! ! ! ! ! ! ! Direct ARINC 429 line driver interface in a small package On-chip band-gap reference to set output levels On-chip line driver slope control and selection by logic input Low current 12 to 15 volt supplies CMOS / TTL logic pins Plastic and ceramic package options surface mount and DIP Thermally enhanced SOIC packages Industrial & extended temperature ranges 1 1 1 PIN DESCRIPTION TABLE PIN 1 2 3 4 5 6 7 8 SYMBOL SLP 1.5 TX0IN TX1IN GND VTXAOUT TXBOUT V+ FUNCTION LOGIC INPUT LOGIC INPUT LOGIC INPUT POWER POWER OUTPUT OUTPUT POWER DESCRIPTION CMOS OR TTL, V+ IS OK CMOS OR TTL CMOS OR TTL GROUND -12 TO -15 VOLTS LINE DRIVER TERMINAL A LINE DRIVER TERMINAL B +12 TO +15 VOLTS ( DS 8585 Rev. N) HOLT INTEGRATED CIRCUITS www.holtic.com 09/11 HI-8585, HI-8586 FUNCTIONAL DESCRIPTION Figure 1 is a block diagram of the line driver. The +5V and -5V levels are generated internally using a on-chip bandgap reference. Currents for slope control are set by zener voltages across on-chip resistors. The TX0IN and TX1IN inputs receive logic signals from a control transmitter chip such as the HI-6010, HI-3282 or HI-8282. TXAOUT and TXBOUT hold each side of the ARINC bus at Ground until one of the inputs becomes a One. If for example TX1IN goes high, a charging path is enabled to 5V on an “A” side internal capacitor while the “B” side is enabled to -5V. The charging current is selected by the SLP1.5 pin. If the SLP1.5 pin is high, the capacitor is nominally charged from 10% to 90% in 1.5µs. If SLP1.5 is low, the rise and fall times are 10µs. A unity gain buffer receives the internally generated slopes and differentially drives the ARINC line. Current is limited by the series output resistors at each pin. There are no fuses at the outputs of the HI-8585 as exists on the Hi-8382. The HI-8585 has 37.5 ohms in series with each output and the HI-8586 has 2 ohms in series with each output. The HI-8586 is for applications where external series resistance is required, typically for lightning protection devices. Both the HI-8585 and HI-8586 are built using high-speed CMOS technology. Care should be taken to ensure the V+ and V- supplies are locally decoupled and that the input waveforms are free from negative voltage spikes which may upset the chip’s internal slope control circuitry. 5V ONE “A” SIDE CURRENT CONTROL TXAOUT HI-8585 = 37.5 OHMS HI-8586 = 2 OHMS NULL ZERO -5V TX0IN TX1IN ESD PROTECTION AND VOLTAGE TRANSLATION CONTROL LOGIC SLP1.5 5V ONE “B” SIDE CURRENT CONTROL TXBOUT HI-8585 = 37.5 OHMS HI-8586 = 2 OHMS NULL ZERO CONTROL LOGIC -5V FIGURE 1 - LINE DRIVER BLOCK DIAGRAM 5V 1 HARDWIRED OR DRIVEN FROM LOGIC { 2 8 4 VCC TESTA TESTB ROUTA ROUTB 6 7 RXD1 RXD0 HI-8588 RINA RINB APPLICATION INFORMATION Figure 2 shows a possible application of the HI-8585/86 interfacing an ARINC transmit channel from the HI-6010. ARINC Channel 3 HI-6010 5 15V 1 6 SLP1.5 TXAOUT 8 BIT BUS 8 V+ TX1IN TX0IN V- 3 2 ARINC Channel TXD1 TXD0 7 HI-8585 TXBOUT GND 4 5 -15V FIGURE 2 - APPLICATION DIAGRAM HOLT INTEGRATED CIRCUITS 2 HI-8585, HI-8586 ABSOLUTE MAXIMUM RATINGS Voltages referenced to Ground Supply voltages V+....................................................20V V-....................................................-20V DC current per input pin................ +10mA Power dissipation at 25°C plastic DIL............1.0W, derate 10mW/°C ceramic DIL..........0.5W, derate 7mW/°C Solder Temperature ........275°C for 10 sec Storage Temperature........-65°C to +150°C RECOMMENDED OPERATING CONDITIONS Supply Voltages V+.................................+11.4V to +16.5V V-.................................. -11.4V to -16.5V Temperature Range Industrial .............-40°C to +85°C Extended ...........-55°C to +125°C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. DC ELECTRICAL CHARACTERISTICS V+ = +12V to +15V, V- = -12V to -15V, T A = Operating Temperature Range (unless otherwise stated) PARAMETERS Input voltage (TX1IN, TX0IN, SLP1.5) high low Input current (TX1IN, TX0IN, SLP1.5) source sink ARINC output voltage (Differential) one zero null ARINC output voltage (Ref. to GND) one or zero null Operating supply current V+ VARINC output impedence HI-8585 HI-8586 SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VIH VIL 2.1 - - V+ 0.5 volts volts IIH IIL VIN = 0V VIN = 5V - - 0.1 0.1 mA mA VDIFF1 VDIFF0 VDIFFN no load; TXAOUT - TXBOUT 9.00 no load; TXAOUT - TXBOUT -11.00 no load; TXAOUT - TXBOUT -0.50 10.00 -10.00 0 11.00 -9.00 0.50 volts volts volts VDOUT VNOUT no load & magnitude at pin no load SLP1.5 = V+ TX1IN & TX0IN = 0V: no load TX0IN & TX1IN = 0V: no load 4.50 -0.25 5.00 0 5.50 0.25 volts volts IDD IEE ZOUT -14.0 6.0 -6.0 14.0 - mA mA - 37.5 - 2 ohms ohms HOLT INTEGRATED CIRCUITS 3 HI-8585, HI-8586 AC ELECTRICAL CHARACTERISTICS V+ = 15.0V, V- = -15V, T A = Operating Temperature Range (unless otherwise stated) PARAMETERS Line Driver propagation delay Output high to low Output low to high Line Driver transition times High Speed Output high to low Output low to high Low Speed Output high to low Output low to high Input capacitance (1) logic Notes: 1. Guaranteed but not tested t phlx t plhx SLP 1.5 = V+ pin 1 = logic 1 pin 1 = logic 1 SLP 1.5 = GND pin 1 = logic 1 pin 1 = logic 1 SYMBOL TEST CONDITIONS defined in Figure 3, no load 500 500 ns ns MIN TYP MAX UNITS t fx t rx t fx t rx 1.0 1.0 5.0 5.0 1.5 1.5 10.0 10.0 2.0 2.0 15.0 15.0 µs µs µs µs CIN - - 10 pF pin 3 t phlx t plhx pin 2 t phlx t rx t rx VDIFF pin 6 - pin 7 90% 10% 90% 10% 10% 5V 0V t plhx 5V 0V 10V 0V -10V t fx t fx FIGURE 3 - LINE DRIVER TIMING HOLT INTEGRATED CIRCUITS 4 HI-8585, HI-8586 PACKAGE THERMAL CHARACTERISTICS MAXIMUM ARINC LOAD 9, 10 PACKAGE STYLE 1 8 Lead Plastic DIP 8 Lead Plastic ESOIC 5 8 Lead Plastic ESOIC 6 ARINC 429 DATA RATE Low Speed 3 High Speed 4 Low Speed High Speed Low Speed High Speed SUPPLY CURRENT (mA) 2 Ta = 25 C o JUNCTION TEMP, Tj (°C) Ta = 25oC Ta = 85oC Ta=125oC Ta = 85 C o Ta=125 C o 16.8 27.3 17.4 27.6 17.1 27.3 17.2 26.7 17.5 27.1 17.2 27.1 16.9 25.9 16.9 25.9 16.7 26.2 58 75 68 97 52 57 116 132 126 147 110 112 157 169 166 186 151 157 TXAOUT and TXBOUT Shorted to Ground 7, 8, 9, 10 PACKAGE STYLE 1 8 Lead Plastic DIP 8 Lead Plastic ESOIC 5 8 Lead Plastic ESOIC 6 ARINC 429 DATA RATE Low Speed 3 High Speed Low Speed Low Speed High Speed 4 SUPPLY CURRENT (mA) 2 Ta = 25 C o JUNCTION TEMP, Tj (°C) Ta = 25oC Ta = 85oC Ta=125oC Ta = 85 C o Ta=125 C o 53.6 46.9 46.4 42.1 48.5 46.8 50.7 38.7 47.6 43.8 45.6 41.1 52.2 42.5 68.1 67.1 46.1 40.5 131 135 167 177 112 116 181 181 191 212 161 168 217 219 221 223 186 197 High Speed Notes: 1. All data taken in still air on devices soldered to single layer copper PCB (3" X 4.5" X .062"). 2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8. 3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF. 4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF as this is considered unrealistic for high speed operation. 5. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink not soldered to the PCB. 6. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink soldered to the PCB. 7. Similar results would be obtained with TXAOUT shorted to TXBOUT. 8. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended. 9. Data will vary depending on air flow and the method of heat sinking employed. 10. Current values are per supply. HEAT SINK - ESOIC PACKAGES An 8-pin thermally enhanced SOIC package is used for the HI-8585/HI-8586 products. The ESOIC package includes a metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. The heat sink is electrically isolated from the chip and can be soldered to any ground or power plane. However, since the chip’s substrate is at V+, connecting the heat sink to this power plane is recommended to avoid coupling noise into the circuit. HOLT INTEGRATED CIRCUITS 5 HI-8585, HI-8586 ORDERING INFORMATION HI - 85XX xx x x PART NUMBER LEAD FINISH Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I T M PART NUMBER -40°C TO +85°C -55°C TO +125°C -55°C TO +125°C PACKAGE DESCRIPTION I T M No No Yes PD PS CR PART NUMBER 8 PIN PLASTIC DIP (8P) 8 PIN PLASTIC NARROW BODY ESOIC (8HNE) 8 PIN CERDIP (8D) not available Pb-free OUTPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY 8585 8586 37.5 Ohms 2 Ohms 0 35.5 Ohms Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC) with built-in heat sink HI - 8585 PS I - N PART NUMBER LEAD FINISH N PART NUMBER Tin / Lead (Sn / Pb) Solder - No heat-sink TEMPERATURE RANGE FLOW BURN IN I PART NUMBER -40°C TO +85°C PACKAGE DESCRIPTION I No PS PART NUMBER 8 PIN PLASTIC NARROW BODY SOIC (8HN) OUTPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY 8585 37.5 Ohms 0 Legend: SOIC - Small Outline Package (No Heat-Sink) HOLT INTEGRATED CIRCUITS 6 HI-8585, HI-8586 REVISION HISTORY P/N DS8585 Rev M N Date 05/08/08 09/09/11 Description of Change Clarified temperature ranges and added HI-8585PSI-N to Ordering Information Replaced references of setting ARINC output levels with zener diodes to using a band-gap reference circuit. HOLT INTEGRATED CIRCUITS 7 HI-8585 / HI-8586 PACKAGE DIMENSIONS 8-PIN PLASTIC SMALL OUTLINE (ESOIC) - NB (Narrow Body, Thermally Enhanced) Top View .194 ± .004 (4.92 ± .09) .0085 ± .0015 (.216 ± .038) inches (millimeters) Package Type: 8HNE Bottom View .140 ± .01 (3.56 ± .26) .236 ± .008 (5.99 ± .21) PIN 1 .154 ± .004 (3.90 ± .09) .100 ± .01 (2.54 ± .25) .0165 ± .003 (.419 ± .089) SEE DETAIL A .055 ± .005 (1.397 ± .127) Electrically isolated metal heat sink on bottom of package Connect to any ground or power plane for optimum thermal dissipation 0° to 8 ° .0025 ± .002 (.064 ± .038) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .050 BSC (1.27) .033 ± .017 (.838 ± .432) DETAIL A 8-PIN PLASTIC SMALL OUTLINE (SOIC) - NB (Narrow Body) .194 ± .004 (4.92 ± .09) inches (millimeters) Package Type: 8HN .0085 ± .0015 (.216 ± .038) .236 ± .008 (5.99 ± .21) PIN 1 .154 ± .004 (3.90 ± .09) See Detail A .0165 ± .003 (.419 ± .089) .055 ± .005 (1.397 ± .127) 0° to 8 ° BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .050 BSC (1.27) .033 ± .017 (.838 ± .432) .0069 ± .003 (.1753 ± .074) Detail A HOLT INTEGRATED CIRCUITS 8 HI-8585 / HI-8586 PACKAGE DIMENSIONS 8-PIN PLASTIC DIP inches (millimeters) Package Type: 8P .385 ±.015 (9.799 ±.381) .250 ± .010 (6.350 ±.254) .100 BSC (2.54) .300 ±.010 (7.620 ±.254) .135 ±.015 (3.429 ±.381) .1375 ±.0125 (3.493 ±.318) .019 ±.002 (.483 ±.102) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) .025 ±.010 (.635 ± .254) .0115 ±.0035 (.292 ±.089) .055 ±.010 (1.397 ±.254) .335 ±.035 (8.509 ±.889) 8-PIN CERDIP .380 ±.004 (9.652 ±.102) .005 min (.127 min) .248 ±.003 (6.299 ±.076) .039 ±.006 (.991 ±.154) .100 BSC (2.54) .015 min (.381min) inches (millimeters) Package Type: 8D .314 ±.003 (7.976 ±.076) .200 max (5.080 max) Base Plane Seating Plane .163 ±.037 (4.140 ±.940) .056 ±.006 (1.422 ±.152) .018 ±.006 (.457 ±.152) .350 ±.030 (8.890 ±.762) .010 ±.006 (.254 ±.152) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 9