HI-8596PCIF

July 2011 Single-Rail ARINC 429 Differential Line Driver PIN CONFIGURATION (TOP VIEW) AMPB 1 TXBOUT 2 TX0IN 3 TX1IN 4 CP- 5 CP+ 6 VDD2P 7 VDD 8 16 AMPA 15 TXAOUT 14 - HI-8596 GENERAL DESCRIPTION The HI-8596 bus interface product is a silicon gate CMOS device designed as a line driver in accordance with the ARINC 429 bus specifications. The part includes a dual polarity voltage doubler, allowing it to operate from a single +3.3V supply using only four external capacitors. The part also features high-impedance outputs (tri-state) when both data inputs are taken high, allowing multiple line drivers to be connected to a common bus. Logic inputs feature built-in 4kV ESD input protection (HBM) as well as 5V or 3.3V logic level compatibility. 37.5 Ohm or 5 Ohm resistors in series with each ARINC output are available to allow the use of external resistors for lightning protection. The HI-8596 line driver is intended for use where logic signals must be converted to ARINC 429 levels such as when using an FPGA or the HI-3586 ARINC 429 protocol IC. The part is available in Industrial -40 C to +85 C, or o o Extended, -55 C to +125 C temperature ranges. Optional burn-in is available on the extended temperature range. o o HI-8596PSI HI-8596PST 13 SLP 12 CN+ 11 CN10 VDD2N 9 GND 16-Pin Plastic SOIC package (Narrow Body) (See page 9 for additional package pin configurations) Table 1. Function Table TX1IN 0 0 0 1 1 1 TX0IN 0 1 1 0 0 1 SLP X 0 1 0 1 X TXAOUT 0V -5V -5V 5V 5V Hi-Z TXBOUT 0V 5V 5V -5V -5V Hi-Z SLOPE N/A 10μs 1.5μs 10μs 1.5μs N/A FEATURES • Single +3.3V supply • All ARINC 429 voltage levels generated on-chip • Digitally selectable rise and fall times • Tri-state Outputs • 5 Ohm or 37.5 Ohm output resistance • Industrial and Extended temperature ranges • Burn-in available DS8596 Rev. B. HOLT INTEGRATED CIRCUITS www.holtic.com 1 07/11 HI-8596 BLOCK DIAGRAM VDD CSUPPLY SLP TX0IN TX1IN 3.3V 5 OHMS VDD2+ ONE ESD PROTECTION & VOLTAGE TRANSLATION AMPA TXAOUT 5V CURRENT CONTROL “A” SIDE NULL ZERO CONTROL LOGIC 37.5 OHMS -5V VDD2ONE NULL 5V CURRENT CONTROL 5 OHMS AMPB TXBOUT “B” SIDE 37.5 OHMS GND VDD ZERO CONTROL LOGIC -5V VDD2+ CP+ CFLY CPCN+ CFLY CNDual Polarity Voltage Doubler VDD2- VDD2+ COUT VDD2COUT Figure 1. HI-8596 Block Diagram HOLT INTEGRATED CIRCUITS 2 HI-8596 PIN DESCRIPTIONS Table 2. Pin Descriptions Pin SLP TX0IN TX1IN VDD GND VDD2+ CP+ CPVDD2CN+ CNTXAOUT AMPA TXBOUT AMPB Function INPUT INPUT INPUT POWER POWER OUTPUT ANALOG ANALOG OUTPUT ANALOG ANALOG OUTPUT OUTPUT OUTPUT OUTPUT Description Output slew rate control. High selects ARINC 429 high-speed. Low selects ARINC 429 low-speed. Data input zero Data input one +3.3V power supply Ground supply Voltage doubler positive output (~6.6V for 3.3V supply) VDD2+ flyback capacitor, CFLY; positive terminal VDD2+ flyback capacitor, CFLY; negative terminal Voltage doubler negative output (~ -6.6V for 3.3V supply) VDD2- flyback capacitor, CFLY; positive terminal VDD2- flyback capacitor, CFLY; negative terminal ARINC high output with 37.5 Ohms series resistance ARINC high output with 5 Ohms series resistance ARINC low output with 37.5 Ohms series resistance ARINC low output with 5 Ohms series resistance HOLT INTEGRATED CIRCUITS 3 HI-8596 FUNCTIONAL DESCRIPTION Figure 1 is a block diagram of the line driver. The HI-8596 requires only a single +3.3V power supply. An integrated inverting / non-inverting voltage doubler generates the rail voltages (±6.6V) which are then used to produce the ±5V ARINC-429 output levels. The internal dual polarity charge pump circuit requires four external capacitors, two for each polarity generated by the doubler. CP+ and CP- connect the external charge transfer or “fly” capacitor, CFLY, to the positive portion of the doubler, resulting in twice VDD at the VDD2+ pin. An output “hold” capacitor, COUT, is placed between VDD2+ and GND. COUT should be ten times the size of CFLY. The inverting or negative portion of the converter works in a similar fashion, with CFLY and COUT placed between CN+ / CN- and VDD2- / GND respectively. Currents for slope control are set by on-chip resistors. The TX0IN and TX1IN inputs receive logic signals from a control transmitter chip such as the HI-3584. TXAOUT and TXBOUT hold each side of the ARINC bus at Ground until one of the inputs becomes a One. If for example TX1IN goes high, a charging path is enabled to 5V on an “A” side internal capacitor while the “B” side is enabled to -5V. The charging current is selected by the SLP pin. If the SLP pin is high, the capacitor is nominally charged from 10% to 90% in 1.5μs. If SLP is low, the rise and fall times are 10μs. A unity gain buffer receives the internally generated slopes and differentially drives the ARINC line. Current is limited by the series output resistors at each pin. There are no fuses at the outputs of the HI-8596. The HI-8596 has 37.5 ohms in series with each TXOUT output and 5 ohms in series with each AMP output. The AMP outputs are for applications where external series resistance is required, typically for lightning protection devices. Holt Application Note AN-300 describes suitable lightning protection schemes. Tri-stateable outputs allow multiple line drivers to be connected to the same ARINC 429 bus. Setting TX1IN and TX0IN both to a logic “1” puts the outputs in the high-impedance state. ABSOLUTE MAXIMUM RATINGS Supply Voltages Power Dissipation at 25 C VDD .......................................................... +5V o RECOMMENDED OPERATING CONDITIONS Supply Voltages Temperature Range VDD ................................... +3.0V to +3.6V Industrial Screening .............. -40 C to +85 C Hi-Temp Screening .............. -55 C to +125 C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. o o o o plastic SOIC ........... 1.0W, derate 10mW/ C ceramic DIP ......... 0.5W, derate 7mW/ C Solder Temperature ......................... 275 C for 10sec Storage Temperature ....................... -65 C to +150 C o o o o o Note: HEAT SINK on QFN PACKAGE The HI-8596 driver is available in a small-footprint, thermally enhanced QFN (chip-scale) package. This package includes an electrically isolated metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. HOLT INTEGRATED CIRCUITS 4 HI-8596 ELECTRICAL CHARACTERISTICS Table 3. DC Electrical Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Input Voltage (TX1IN, TX0IN, SLP) High Low Input Current (TX1IN, TX0IN, SLP) Source Sink ARINC Output Voltage (Differential) one zero null ARINC Output Voltage (Ref. to GND) one or zero null Operating Supply Current No load Max. Load ARINC Output Impedance TXOUT pins AMP pins ARINC Output Tri-State Current Symbol VIH VIL IIH IIL VDIFF1 VDIFF0 VDIFFN VDOUT VNOUT IDDNL IDDL ZOUT Test Conditions Min 0.7VDD - Typ 45 10 -10 0 5.0 0 28 65 37.5 5 Max 0.3VDD 0.1 Units V V μA μA VIN = 0V VIN = 3.3V, 7.34kΩ pulldown no load; TXAOUT - TXBOUT no load; TXAOUT - TXBOUT no load; TXAOUT - TXBOUT no load & magnitude at pin no load SLP = VDD TX1IN & TX0IN = 0V 100kHz, 400Ω load 9 -11 -0.5 4.5 -0.25 - 11 -9 0.5 5.5 0.25 40 - V V V V V mA mA Ohms Ohms IOZ TX0IN = TX1IN = VDD -5.75V < VOUT < +5.75V -1.0 0 +1.0 μA HOLT INTEGRATED CIRCUITS 5 HI-8596 Table 4. Converter Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Start-up transient (V+, V-) Operating Switching Frequency Symbol tSTART fsw CFLY Test Conditions Min - Typ 650 4.7 47 68 Max 10 - Units ms kHz μF μF μF COUT / CFLY >= 10 CSUPPLY >= COUT (connect from VDD to GND) 2.2 22 47 Recommended Capacitors COUT CSUPPLY Table 5. AC Electrical Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Line Driver Propogation Delay Output high to low Output low to high Line Driver Transition Times High Speed Output high to low Output low to high Low Speed Output high to low Output low to high Input Capacitance (Logic)1 Output Capacitance (Tri-state)1 Notes: 1. Guaranteed but not tested Symbol tphlx tplhx Test Conditions defined in Figure 2, no load Min - Typ 500 500 Max - Units ns ns SLP = V+ tfx trx tfx trx CIN COUT TX0IN = TX1IN = VDD pin 1 = logic 1 pin 1 = logic 1 SLP = V+ pin 1 = logic 0 pin 1 = logic 0 5.0 5.0 10.0 10.0 15.0 15.0 10 10 μs μs pF pF 1.0 1.0 1.5 1.5 2.0 2.0 μs μs HOLT INTEGRATED CIRCUITS 6 HI-8596 5V TX1IN 0V tphlx tplhx tplhx 5V TX0IN 0V tphlx trx trx VDIFF (TXAOUT - TXBOUT) 10% 90% 10% 90% 10% 10V 0V -10V tfx tfx Figure 2. Line Driver Timing HOLT INTEGRATED CIRCUITS 7 HI-8596 ORDERING INFORMATION HI - 8596Px x x (Plastic) PART NUMBER Blank F PART NUMBER I T M LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE -40 C to +85 C -55oC to +125oC -55 C to +125 C o o o o FLOW I T M BURN IN No No Yes LEAD FINISH Solder Solder PART NUMBER 8596PS 8596PC PACKAGE DESCRIPTION 16 PIN PLASTIC SMALL OUTLINE - NB SOIC (16HN) 16 PIN PLASTIC QFN (16PCS) HI - 8596CD x (Ceramic) PART NUMBER I T M PART NUMBER 8596CD TEMPERATURE RANGE -40oC to +85oC -55oC to +125oC -55 C to +125 C o o FLOW I T M BURN IN LEAD FINISH No No Yes Gold (Pb-free, RoHS compliant) Gold (Pb-free, RoHS compliant) Tin / Lead (Sn / Pb) Solder PACKAGE DESCRIPTION 20 PIN CERAMIC SIDE BRAISED DIP (20C) HOLT INTEGRATED CIRCUITS 8 HI-8596 ADDITIONAL PIN CONFIGURATIONS NOTE: All power and ground pins must be connected. TXBOUT 2 TX0IN 3 TX1IN 4 CP- 5 CP+ 6 VDD2P 7 VDD 8 15 TXAOUT 14 13 SLP 12 CN+ 11 CN10 VDD2N 9 GND TX0IN 1 TX1IN 2 CP- 3 CP+ 4 16 15 14 13 12 11 10 9 TXBOUT AMPB AMPA TXAOUT AMPB 1 16 AMPA SLP CN+ CN- HI-8596CD 16-PIN CERAMIC SIDE-BRAZED DIP HI-8596PC 16-LEAD 4mm x 4mm QFN HOLT INTEGRATED CIRCUITS 9 VDD2P VDD GND VDD2N 5 6 7 8 HI-8596 REVISION HISTORY Revision DS8596, Rev. NEW Rev. A Rev. B Date 11/10/10 11/11/10 7/14/11 Description of Change Initial Release Clarified connection of heat sink and updated some electrical parameters (VIH, VIL, fsw). Added operating supply current at full load (IDDL). Updated supply voltage range. Corrected dimensions on QFN heat sink. Added voltage limits for Tri-state output current. HOLT INTEGRATED CIRCUITS 10 HI-8596 PACKAGE DIMENSIONS 16-PIN PLASTIC SMALL OUTLINE (SOIC) - NB Narrow Body) .390 ± .004 (9.90 ± .10) .0087 ± .0015 (.220 ± .029) inches (millimeters) Package Type: 16HN .236 .008 (5.99 .20) Top View .1525 ± .0025 (3.87 ± .06) .0165 ± .003 (.419 ± .089) See Detail A .061 ± .007 (1.549 ± .178) .050 BSC (1.27) 0 to 8 .033 ± .017 (.838 ± .432) .0025 ± .002 (.064 ± .038) Detail A 16-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) millimeters Package Type: 16PCS 4.00 BSC Electrically isolated heat sink pad on bottom of package. 2.80 ± .10 4.00 BSC Top View 2.80 ± .10 Bottom View 0.65 BSC 0.30 ± .05 0.40 ± .05 1.00 max 0.20 typ BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 11 HI-8596 16-PIN CERAMIC SIDE-BRAZED DIP .810 max (20.574) inches (millimeters) Package Type: 16C .295 ± .010 (7.493 ± .254) .050 ± .005 (1.270 ± .127) .035 ± .010 (.889 ± .254) BASE PLANE SEATING PLANE .100 BSC (2.54) .300 ± .010 (7.620 ± .254) PIN 1 .200 max (5.080) .125 min (3.175) .010 ± .002 (.254 ± .051) .018 ± .002 (.457 ± .051) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 12