HI-8683_06

HI-8683, HI-8684 September 2006 ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 8-Bit Parallel Data APPLICATIONS ! Avionics data communication ! Serial to parallel conversion ! Parallel to serial conversion DESCRIPTION The HI-8683 and HI-8684 are system components for interfacing incoming ARINC 429 signals to 8-bit parallel data using proven +5V analog/digital CMOS technology. The HI-8683 is a digital device that requires an external analog line receiver such as the HI-8482 or HI-8588 between the ARINC bus and the device inputs. The HI-8684 incorporates the digital logic and analog line receiver circuitry in a single device. The HI-8683 is also available as a second source to the DLS-112 with the original 18 pin DIP and 28 pin PLCC package pinouts. The receivers on the HI-8684 connect directly to the ARINC 429 Bus and translate the incoming signals to normal CMOS levels. Internal comparator levels are set just below the standard 6.5 volt minimum data threshold and just above the standard 2.5 volt maximum null threshold. The -10 version of the HI-8684 allows the incorporation of an external 10KW resistance in series with each ARINC input for lightning protection without affecting ARINC level detection. Both products offer high speed 8-bit parallel bus interface, a 32-bit buffer, and error detection for word length and parity. A reset pin is also provided for power-on initialization. PIN CONFIGURATIONS (Top View) DATARDY D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 18 17 16 15 Vcc GAPCLK RESET INB INA ERROR PARITY ENB READ GND HI-8683PSI HI-8683PST 14 13 12 11 10 HI-8683 18-Pin Plastic SOIC - WB Package FEATURES Vcc 1 2 3 4 5 6 7 8 9 10 20 19 18 GAPCLK TESTA TESTB RESET RINB (-10) RINA (-10) ERROR PARITY ENB READ GND ! Automatic conversion of serial ARINC 429, 575 & 561 data to 8-bit parallel data DATARDY D7 D6 D5 D4 D3 D2 D1 D0 ! High speed parallel 8-bit data bus ! Error detection - word length and parity ! Reset input for power-on initialization ! On-chip line receiver option (HI-8684) ! Input hysteresis of at least 2 volts (HI-8684) ! Test inputs bypass analog inputs (HI-8684) ! Simplified lightning protection with the ability to add 10 Kohm external series resistors (HI-8684-10) PLCC and DIP HI-8684PSI HI-8684PST & HI-8684PSI-10 HI-8684PST-10 17 16 15 14 13 12 11 ! Plastic package options - surface mount (SOIC), ! Military processing available HI-8684 20-Pin Plastic SOIC - WB Package (See page 8 for additional pin configurations) (DS8683 Rev. H) HOLT INTEGRATED CIRCUITS www.holtic.com 09/06 HI-8683, HI-8684 PIN DESCRIPTIONS SIGNAL DATA RDY D0 to D7 GND READ PARITY ENB ERROR FUNCTION OUTPUT OUTPUT POWER INPUT INPUT OUTPUT DESCRIPTION Receiver data ready flag. A high level indicates data is available in the receive buffer. Flag goes low when the first 8-bit byte is read. 8-bit parallel data bus (tri-state) 0V Read strobe. A low level transfers receive buffer data to the data bus Parity Enable - A high level activates odd parity checking which replaces the 32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged Error Flag. A high level indicates a bit count error (number of ARINC bits was less than or greater than 32) and/or a parity error if parity detection was enabled (PARITY ENB high) Positive digital serial data input (HI-8683 only) Negative digital serial data input (HI-8683 only) Positive direct ARINC serial data input (HI-8684 & HI-8684-10 only) Negative direct ARINC serial data input (HI-8684 & HI-8684-10 only) Internal logic states are initialized with a low level Used in conjunction with the TESTB input to bypass the built-in analog line receiver circuitry (HI-8684 & HI-8684-10 only) Used in conjunction with the TESTA input to bypass the built-in analog line receiver circuitry (HI-8684 & HI-8684-10 only) Gap Clock. Determines the minimum time required between ARINC words for detection. The minimum word gap time is between 16 and 17 clock cycles of this signal. +5V ±5% supply INA INB RINA/RINA-10 RINB/RINB-10 RESET TESTA TESTB GAPCLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT Vcc POWER FUNCTIONAL DESCRIPTION The HI-8683 and HI-8684 are serial to 8-bit parallel converters. The incoming data stream is serially shifted into an input register, checked for errors, and then transferred in parallel to a 32-bit receive buffer. The receive data can be accessed using four 8-bit parallel read operations while the next serial data steam is being received. RECEIVER INPUTS Figure 1 is a block diagram of both the HI-8683 and HI-8684. The difference between the two products is the HI-8684 has a built-in line receiver whereas the HI-8683 is strictly a digital device and requires an external ARINC line receiver such as the Holt HI-8444, HI-8445, HI-8448 , HI-8482 or HI-8588 to interface to the ARINC 429 bus. HI-8684 Line Receiver Internal 35KW resistors are in series with both the RINA and RINB ARINC 429 inputs. They connect to level translators whose resistance to GND is typically 10KW. After level translation, the buffered inputs drive a differential amplifier. The differential signal is compared to levels derived from a divider between VCC and GND. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. A valid ARINC One/Zero input sets a latch and a Null input resets the latch. Since any added external series resistance will affect the voltage translation, the HI-8684-10 is available with 25KW of the 35KW series resistance required for proper ARINC 429 level detection. The remaining 10KW required that must be added can be incorporated in other external circuitry such as lightning protection. Except for the different input series resistance, the HI-8684 and HI-8684-10 are identical. HOLT INTEGRATED CIRCUITS 2 HI-8683, HI-8684 PARITY ENB INA ESD PROTECTION CLK ERROR ERROR DETECT PARITY DETECT RXA HI-8683 ONLY CLOCK & DATA DETECT INB RINA-10 RINA RINB RINB-10 TESTA TESTB HI-8684 ONLY 10KW 25KW ESD PROTECTION & LINE RECEIVER RXB DATA BIT 32 BIT 32 10KW 25KW BIT COUNT 32-BIT SHIFT REG. 32 32-BIT RECEIVE 32 BUFFER 32-BIT TO 8-BIT MUX 8 D0 - D7 GAP DETECT BYTE COUNT DATA RDY GAPCLK RESET READ Figure 1. Block Diagram FUNCTIONAL DESCRIPTION (cont.) PROTOCOL DETECTION ARINC clock and data in the HI-8683 are derived from the two streams of digital data at the INA and INB inputs and the resulting One/Zero data is shifted into a 32-bit input register as illustrated in Figure 3. In the HI-8684, the One/Zero data shifted into the input register is created from either the two digital outputs of the builtin line receiver (Figure 3) or the TESTA and TESTB inputs (Figure 4). For ARINC 561 operation, the INA and INB data streams inputs must be derived from the ARINC 561 data, clock and sync with external logic. GAP DETECTION The end of a data word is detected by an internal counter that times out when a data One or Zero is not received for a period equal to 16 cycles of the GAPCLK signal. The gap detection time may vary between 16 and 17 cycles of the GAPCLK signal since the incoming data and GAPCLK are not usually synchronous inputs. The required frequency of GAPCLK is a function of the mininum gap time specified for the type of ARINC data being received. Table 1 indicates typical frequencies that may be used for the various data rates normally encountered. DATABUS TYPE 429 BIT PERIOD (µs) 10 MINIMUM GAP (µs) 45 GAP CLOCK MHz 0.75 1.0 1.5 0.1 0.1 0.2 GAP DETECTION TIME (µs) 21.3 - 22.7 16 - 17 10.7 - 11.3 160 - 170 160 - 170 80 - 85 429 575 561 69 - 133 69 - 133 69 - 133 310 - 599 310 - 599 103 - 200 Table 1 - Typical Gap Detection Times HOLT INTEGRATED CIRCUITS 3 HI-8683, HI-8684 FUNCTIONAL DESCRIPTION (cont.) ERROR CHECKING Once a word gap is detected, the data word in the input register is transferred to the receive buffer and checked for errors. When parity detection is enabled (PARITY ENB high), the received word is checked for odd parity. If there is a parity error, the 32nd bit of the received data word is set high. If parity checking is disabled (PARITY ENB low) the 32nd bit of the data word is always the 32nd ARINC bit received. The ERROR flag output is set high upon receipt of a word gap and the number of bits received since the previous word gap is less than or greater than 32. The ERROR flag is reset low when the next valid ARINC word is written into the receive buffer or when RESET is pulsed low. READING RECEIVE BUFFER When the data word is transferred to the receive buffer, the DATA RDY pin goes high. The data word can then be read in four 8-bit bytes by pulsing the READ input low as indicated in Figure 5. The first read cycle resets DATA RDY low and increments an internal counter to the next 8-bit byte. The counter continues to increment on each read cycle until all four bytes are read. The relationship between each bit of an ARINC word received and each bit of the four 8-bit data bus bytes is specified in Figure 2. When a new ARINC word is received it always overwrites the receive buffer. If the first byte of the previous word has not been read, then previous data is lost and the receive buffer will contain the new ARINC word. However, if the DATA RDY pin goes high between the reading of the first and fourth bytes, the previous read bytes are no longer valid because the unread bytes have been overwritten by the new ARINC word. Also, the next read will be of the first byte of the new ARINC word since the internal byte counter is always reset to the first byte when new data is transferred to the receive buffer. The built-in differential line receiver on the HI-8684 can be disabled allowing the data and clock detection circuitry to be driven directly with digital signals. The logical OR function of the TESTA and TESTB is defined in Truth Table 1. The two inputs can be used for testing the receiver logic and for inputting ARINC 429 type data derived from another source / protocol. See Figure 4 for typical test input timing. The device should always be initialized with RESET immediately after entering the test mode to clear a partial word that may have been received since the last word gap. Otherwise, an ERROR condition may occur and the first 32 bits of data on the test inputs may not be properly received. Also, when entering the test mode, both TESTA and TESTB should be set high and held in that state for at least one word gap period (17 gap clocks) after RESET goes high. When exiting the test mode, both test inputs should be held low and the device initialized with RESET. Read 1st 2nd 3rd 4th Byte Byte 1 Byte 2 Byte 3 Byte 4 Data Bus Bits D0 - D7 D0 - D7 D0 - D7 D0 - D7 ARINC Bits ARINC 1 - ARINC 8 ARINC 9 - ARINC 16 ARINC 17 - ARINC 24 ARINC 25 - ARINC 32 FIGURE 2. ORDER OF RECEIVED DATA RESET A low on the RESET input sets a flip-flop which initializes the internal logic. When RESET goes high, the internal logic remains in the initialized state until the first word gap is detected preventing reception of a partial word. TEST MODE (HI-8684 only) TRUTH TABLE 1. RINA -1.50 to +1.50V -3.25V to -6.50V +3.25V to +6.50V X X X X = don't care RINB -1.50V to +1.50V +3.25V to +6.50V -3.25V to -6.50V X X X TESTA 0 0 0 0 1 1 TESTB 0 0 0 1 0 1 RXA 0 0 1 0 1 0 RXB 0 1 0 1 0 0 HOLT INTEGRATED CIRCUITS 4 HI-8683, HI-8684 TIMING DIAGRAMS 28 ARINC Data Bits 29 30 31 32 Word Gap 4 Bit Periods Min. 1 2 +5V 0V +5V INA (HI-8683 only) INB (HI-8683 only) VDIFF RINA - RINB (HI-8684 only) DERIVED DATA DERIVED CLOCK FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429 0V +10V 0V -10V 28 ARINC Data Bits 29 30 31 32 Word Gap 4 Bit Periods Min. 1 2 +5V 0V +5V 0V TESTA TESTB DERIVED DATA DERIVED CLOCK FIGURE 4 - TEST INPUT TIMING FOR ARINC 429 DERIVED DATA 32nd ARINC Bit tDRDY tRDYCLR DATA RDY tRDPW READ tRD D0 - D7 VALID 1st 8-bits tRR 2nd 8-bits 3rd 8-bits 4th 8-bits tFD VALID VALID VALID FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING H OLT INTEGRATED CIRCUITS 5 HI-8683, HI-8684 ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND Supply voltages VCC ....................................................... +7.0V Voltage on inputs RINA (-10) to RINB (-10) ......... +29V to - 29V All other input pins..................-0.3 to Vcc +0.3 DC current per input pin ....................... +10mA Power dissipation at 25°C plastic 18-pin SO..... 1.9W, derate 15.4mW/°C plastic 18-pin DIP .....1.6W, derate 13.3mW/°C plastic 20-pin SO ......1.4W, derate 11.5mW/°C plastic 20-pin PLCC .2.0W, derate 17.2mW/°C Solder Temperature Leads ................................ +280°C for 10 sec Package body .....................................+220°C Storage Temperature ............. -65°C to +150°C Supply Voltages VCC ...................................................+5V ± 5% Temperature Range Industrial Screening .............. -40°C to +85°C Hi-Temp Screening .............. -55°C to +125°C Military Screening..................-55°C to +125°C Junction Temperature, Tj ................... £+175°C RECOMMENDED OPERATING CONDITIONS NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. DC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS ARINC Bus Inputs (RINA & RINB, HI-8684 only) Differential input voltage one or zero null common mode Input resistance RINA (-10) to RINB (-10) RINA (-10) or RINB (-10) to GND or VCC Input capacitance (Guaranteed but not tested) differential to GND to VCC SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VDIN VNIN VCOM RDIFF RSUP CDIFF CG CH differential voltage " " "" with respect to GND supplies floating "" "' RINA to RINB 6.5 30 19 - 10.0 75 40 - 13.0 2.75 5.0 20 20 20 volts volts volts Kohm Kohm pF pF pF Digital Inputs (INA, INB, RESET, GAPCLK, READ & PARITY ENB) Input voltage high low Input current source sink Input capacitance VIH VIL IIH IIL CI HOLT INTEGRATED CIRCUITS 6 VIN = 5.0V VIN = 0.0V 2.0 0.0 -1.0 VCC 0.8 1.0 8.0 volts volts µA µA pF HI-8683, HI-8684 DC ELECTRICAL CHARACTERISTICS (cont.) Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS Digital Inputs (TESTA & TESTB) Input voltage high low Input current source sink Input capacitance Outputs (D0 to D7, ERROR & DATA RDY) Output voltage high low Output tri-state current (D0 - D7 only) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VIH VIL IIH IIL CI VIN = 5.0V VIN = 0.0V 2.4 0.0 -1.0 - 110 - VCC 0.8 8.0 volts volts µA µA pF VOH VOL IIH IIL IOH = -1.0 mA IOL = 1.6 mA VOH = 5.0V VOL = 0.0V 2.7 -1.0 - - 0.4 1.0 15 volts volts µA µA pF Output capacitance Operating Supply Current VCC (HI-8683 only) VCC (HI-8684 only) CO ICC1 ICC2 VIN = 0.0V, outputs open VIN = 0.0V, outputs open - - 1.0 6.5 mA mA AC ELECTRICAL CHARACTERISTICS Vcc = 5V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS READ pulse width Data delay from READ READ to data floating READ to DATA RDY clear READ pulse to next READ pulse GAPCLK frequency 32 ARINC bit to DATA RDY SYMBOL tRDPW tRD tFD tRDYCLR tRR fGC tDRDY TEST CONDITIONS MIN 50 TYP MAX UNITS ns 40 20 35 ns ns ns ns 25 1 16 17 MHz clocks HOLT INTEGRATED CIRCUITS 7 HI-8683, HI-8684 HI-8683 & HI-8684 PIN CONFIGURATIONS (See page 1 for additional pin configurations) 3 - D7 2 - DATA RDY 1 - -VCC 20 - GAPCLK 19 - N/A 3 - D7 2 - DATA RDY 1 - -VCC 20 - GAPCLK 19 - TESTA D6 - 4 D5 - 5 D4 - 6 D3 - 7 D2 - 8 HI-8684PJI HI-8684PJT & HI-8684PJI-10 HI-8684PJT-10 18 - TESTB 17 - RESET 16 - RINB (-10) 15 - RINA (-10) 14 - ERROR DATA 1 RDY D6 2 D7 3 18 17 16 15 VCC GAPCLK RESET INB INA D6 - 4 D5 - 5 D4 - 6 D3 - 7 D2 - 8 HI-8683PJI HI-8683PJT 18 - N/A 17 - RESET 16 - INB 15 - INA 14 - ERROR D5 4 D4 5 D3 6 D2 7 HI-8683PDI HI-8683PDT 14 13 D1 - 9 D0 - 10 GND - 11 READ - 12 PARITY - 13 ENB D1 8 GND 9 10 D0 HI-8683 20-Pin Plastic PLCC HI-8683 18-Pin Plastic DIP HI-8684 20-Pin Plastic PLCC ORDERING INFORMATION HI - 868xxx x x - xx PART NUMBER (1) INPUT SERIES RESISTANCE BUILT-IN REQUIRED EXTERNALLY No dash number -10 PART NUMBER 35 Kohm 25 Kohm LEAD FINISH 0 10 Kohm Blank F PART NUMBER Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE FLOW BURN IN I T PART NUMBER -40°C TO +85°C -55°C TO +125°C PACKAGE DESCRIPTION I T 8683PD 8683PJ 8683PS 8684PJ 8684PS 18 PIN PLASTIC DIP 20 PIN PLASTIC PLCC 18 PIN PLASTIC SOIC - WB 20 PIN PLASTIC PLCC 20 PIN PLASTIC SOIC - WB Legend: WB - Wide Body (1): Only available with ‘HI-8684’ HOLT INTEGRATED CIRCUITS 8 D1 - 9 D0 - 10 GND - 11 READ - 12 PARITY - 13 ENB ERROR PARITY 12 ENB 11 READ NO NO BUILT-IN LINE RECV’R NO NO NO YES YES HI-8683, HI-8684 PACKAGE DIMENSIONS inches (millimeters) 18-PIN PLASTIC DIP Package Type: 18P .905 ± .015 (22.99 ± .381) .250 ± .010 (6.350 ± .254) .300 ±.010 (7.62 ± .254) .160 ± .025 (4.064 ± .635) .135 ± .015 (3.429 ± .381) 7° TYP. 0° ~ 15° .130 ± .020 (3.302 ± .508) .100 ± .010 (2.540 ± .254) .0115 ± .0035 (.2921 ± .0889) .019 ± .004 (.483 ± .102) .055 ±.010 (1.397 ± .254) .335 ± .035 (8.509 ± .889) 18-PIN PLASTIC SMALL OUTLINE (SOIC) - WB (Wide Body) .454 ± .008 (11.531 ± .203) Package Type: 18HW .0105 ± .0015 (.2667 ± .0381) .4065 ± .0125 (10.325 ± .318) .293 ± .006 (7.442 ± .152) SEE DETAIL A .018 TYP (.457) .090 ± .010 (2.286 ± .254) 0° to 8° .050 TYP (1.27) .033 ± .017 (.838 ± .432) DETAIL A .0075 ± .0035 (.191 ± .089) HOLT INTEGRATED CIRCUITS 9 HI-8683, HI-8684 PACKAGE DIMENSIONS inches (millimeters) 20-PIN PLASTIC SMALL OUTLINE (SOIC) - WB (Wide Body) .5035 ± .0075 (12.789 ± .191) Package Type: 20HW .0105 ± .0015 (.2667 ± .0381) .4065 ± .0125 (10.325 ± .318) .296 ± .003 (7.518 ± .076) SEE DETAIL A .018 TYP (.457) .090 ± .010 (2.286 ± .254) 0° to 8° .050 TYP (1.27) .033 ± .017 (.838 ± .432) DETAIL A .0075 ± .0035 (.191 ± .089) 20-PIN PLASTIC PLCC Package Type: 20J .045 x 45° PIN NO. 1 IDENT .026 ± .003 x 30° (.660 ± .076 x 30°) .050 ± .003 (1.27 ± .075) .390 ± .005 (9.906 ± .127) SQ. .354 ± .002 (8.991 ± .051) SQ. .017 ±.004 (.432 ±.102) .152 ± .002 (.3.861 ± .051) SEE DETAIL A .010 ± .0003 (.256 ± .0076) .015 ± .002 (.381 ± .051) .020 MIN (.508 MIN) .320 ± .010 (8.128 ± .254) DETAIL A .020 MIN (.508 MIN) .035 R TYP (.889 R) HOLT INTEGRATED CIRCUITS 10