MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
1. Scope
This specification is applied to Multilayer Ceramic Chip Capacitor (MLCC) for use in electric equipment for the
voltage is ranging from 1KV (Include) to 8KV.
The MLCC support for Lead-Free wave and reflow soldering, and electrical characteristic and reliability are
same as before. (This product is compliant with the RoHS.)
2. Parts Number Code
C
1206
X
102
K
202
T
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(5)Capacitance Tolerance
(1)Product
Product Code
C
Multilayer Ceramic Chip Capacitor
(2)Chip Size
Code
0201
0402
0603
0805
1206
1210
1808
1812
1825
2208
2211
2220
2225
Length×Width
unit : mm(inch)
0.60× 0.30 (.024× .011)
1.00× 0.50 (.039× .020)
1.60× 0.80 (.063× .031)
2.00× 1.25 (.079× .049)
3.20× 1.60 (.126× .063)
3.20× 2.50 (.126× .098)
4.60× 2.00 (.181× .079)
4.60× 3.20 (.181× .125)
4.60× 6.35 (.181× .250)
5.70× 2.00 (.220× .197)
5.70× 2.80 (.220× .110)
5.70× 5.00 (.220× .197)
5.70× 6.35 (.220× .250)
(3)Temperature Characteristics
Code Temperature
Characteristic
N
L
X
B
S
Y
Z
E
NPO
SL
X7R
X5R
X6S
Y5V
Z5U
Y5U
(4)Capacitance
Code
Temperature
Range
Temperature
Coefficient
-55℃~+125℃
-25℃~+85℃
-55℃~+125℃
-55℃~+85℃
-55℃~+105℃
-30℃~+85℃
+10℃~+85℃
-30℃~+85℃
30 ppm/℃
+350~-1000ppm
± 15%
± 15%
± 22%
+22/-82%
+22/-56%
+22/-56%
unit :pico farads(pF)
Nominal Capacitance (pF)
Code
Tolerance
Nominal Capacitance
B
C
D
E
F
G
J
K
M
Z
± 0.10 pF
± 0.25 pF
± 0.50 pF
± 1.00 pF
± 1.00 %
± 2.00 %
± 5.00 %
± 10.0 %
± 20.0 %
+80/-20 %
Less Than 10 pF
(Include 10 pF)
More Than 10 pF
(6)Rated Voltage
Code
102
152
202
252
302
502
802
Rated Voltage (Vdc)
1,000
1,500
2,000
2,500
3,000
5,000
8,000
(7)Tapping
Code
T
5R0
5.0
B
120
12.0
151
150.0
102
1,000.0
103
10,000.0
474
470,000.0
105
1,000,000.0
106
10,000,000.0
※. If there is a decimal point, it shall be expressed by an
English capital letter R
Page : 1/15
Type
Tape & Reel
Bulk
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
3. Nominal Capacitance and Tolerance
3.1 Standard Combination of Nominal Capacitance and Tolerance
Class
Ⅰ
Characteristic
NPO / SL
Ⅱ
X7R/X5R/X7E
Y5V
Z5U
Y5U
Tolerance
Less Then 10 pF
B (± 0.10 pF)
C (± 0.25 pF)
D (± 0.50 pF)
E (± 1.00 pF)
More Than 10 pF
F (±1.00 %)
G (±2.00 %)
J (± 5.00 %)
K (± 10.0 %)
K (± 10.0 %), M (± 20.0 %)
M (± 20.0 %), Z(＋80/－20 %)
Nominal Capacitance
0.5,1,1.5,2,2.5,3
0.5,1,1.5,2,2.5,3,3.5,4,4.5,5
5,6,7,8,9,10
6,7,8,9,10
E-12, E-24 series
E-3, E-6 series
E- 3 series
3.2 E series(standard Number)
Standard No.
E- 3
E- 6
E-12
E-24
1.0
1.0
1.0
1.0
1.1
1.5
1.2
1.2
1.3
1.5
1.5
1.6
1.8
1.8
2.0
Application Capacitance
2.2
2.2
3.3
2.2
2.7
3.3
3.9
2.2
2.7
3.3
3.9
2.4
3.0
3.6
4.3
4. Operation Temperature Range
Class
Ⅰ
Ⅱ
Characteristic
NPO
SL
X7R
X5R
X6S
Y5V
Z5U
Y5U
Other
Temperature Range
-55℃ ~ +125℃
-55℃ ~ +125℃
-55℃ ~ +125℃
-55℃ ~ +85℃
-55℃ ~ +105℃
-30℃ ~ +85℃
+10℃ ~ +85℃
-30℃ ~ +85℃
-25℃ ~ +85℃
5. Storage Condition
Storage Temperature：5 to 40℃
Relative Humidity：20 to 70 %
Storage Time：12 months max.
Page : 2/15
Reference Temp.
25℃
25℃
25℃
25℃
25℃
25℃
25℃
25℃
25℃
4.7
4.7
4.7
4.7
5.1
6.8
5.6
5.6
6.2
6.8
6.8
7.5
8.2
8.2
9.1
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
6. Dimensions
6.1 Configuration and Dimension：
BW
B
T
W
L
TYPE
0201
0402
0603
0805
1206
1210
1808
1812
1825
2208
2211
2220
2225
L
0.60± 0.03
1.00± 0.05
1.60± 0.10
2.00± 0.20
3.20± 0.30
3.20± 0.30
4.60± 0.30
4.60± 0.30
4.60± 0.30
5.70± 0.40
5.70± 0.40
5.70± 0.40
5.70± 0.40
W
0.30± 0.03
0.50± 0.05
0.80± 0.10
1.25± 0.20
1.60± 0.20
2.50± 0.20
2.00± 0.20
3.20± 0.30
6.35± 0.40
2.00± 0.20
2.80± 0.40
5.00± 0.40
6.35± 0.40
T (max)
0.33
0.55
1.00
1.45
1.80
2.60
2.20
3.00
2.60
2.20
3.00
3.00
3.00
6.2 Termination Type：
Solder Metal
Barrier
External Electrodes
Inner Electrodes
Ceramic Body
Page : 3/15
B (min)
0.20
0.30
0.40
0.70
1.50
1.60
2.50
2.50
2.50
3.50
3.50
3.50
3.50
Unit:mm
BW (min)
0.10
0.15
0.15
0.20
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
0.30
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
7. Performance
No.
Item
1
Visual
2
3
4
Specification
No abnormal exterior appearance
Visual inspection
Dimension
See Page 3
Visual inspection
Insulation
Resistance
10,000MΩ or 500/CΩ
Product Whichever Is Smaller
V≦500V, Rated Voltage
V＞500V, Applied 500Vdc
Charge Time：60sec.
Is applied less than 50mA current.
Capacitance
Class Within The Specified Tolerance
Ⅰ
NPO/SL
Class
Ⅱ
5
Q
Tanδ
6
Test Condition
Within The Specified Tolerance
Class More Than 30pF : Q ≧1000
Ⅰ
30pF & Below: Q≧400＋20C
NPO/SL (C : Capacitance , pF)
Class
Ⅱ
Withstanding
Voltage
Char.
Maximum
X7R
2.5%
Z5U/Y5U
4.0%
No dielectric breakdown or
mechanical breakdown
ClassⅠ：
NPO/SL
Capacitance
C≦1000pF
C＞1000pF
ClassⅡ：
Frequency
1MHz±10%
1KHz±10%
Voltage
1.0±0.2Vrms
Frequency
Voltage
X7R
1KHz±10% 1.0±0.2Vrms
Z5U/Y5U
1KHz±10% 1.0±0.2Vrms
Perform a heat temperature at 150±5℃ for
30min. then place room temp. for 24±2hr.
200% /150%/120%/100% Rated Voltage
For information which product has which applied
voltage, please contact with HEC sales
representative.
Voltage ramp up rate≦500v/sec
for 1~5 sec. charge/discharge Current is less
than 50mA.
※ Withstanding voltage testing requires immersion of
the element in a isolation fluid prevent arcing on the
chip surface, at voltage over 1000Vdc.
7
8
Temperature ClassⅠ Char. Temp. Range Cap. Change(%) ClassⅠ:
Capacitance
[C2-C1/C1(T2-T1)] × 100%
NPO -55℃~+125℃
± 30 ppm/℃
Coefficient
SL
-30℃~+85℃ +350~-1000ppm ClassⅡ:
(C2-C1)/C1 × 100%
Class Char. Temp. Range Cap. Change(%)
T1: Standard temperature (25℃)
Ⅱ
X7R -55℃~+125℃
± 15%
Y5U -30℃~+85℃
+22% ~-56% T2: Test temperature
C1:Capacitance at standard temperature(25℃)
Z5U +10℃~+85℃ +22% ~-56% C2: Capacitance at test temperature (T2)
Adhesive Strength No indication of peeling shall occur on Pull force shall be applied for 10± 1 second.
of Termination
the terminal electrode.
≦0603----5N(≒ 0.5 Kg·f)
＞0603----10N(≒1.0 Kg·f)
N·f
9
Resistance Appear- No mechanical damage shall be occur. Bending shall be applied to the 1.0 mm with
to
ance
1.0 mm/sec.
R230
Flexure
C-Meter Capacitance Change
Bending
of Substrate
Limit
Char.
Cap. Change
NPO
≦ ± 5.0%
C Meter
SL
≦ ± 5.0%
45±1mm 45±1mm
X7R
≦ ± 12.5%
Y5U/Z5U
≦ ± 30.0%
Page : 4/15
MULTILAYER CERAMIC CHIP CAPACITORS
No.
10
Item
Specification
Solderability
More than 90% of the terminal surface
is to be soldered newly, so metal part
does not come out or dissolve .
11 Resistance
To
Soldering
Heat
Appearance
Capacitance
Q
ClassⅠ
Tan δ
ClassⅡ
Insulation
Resistance
Withstand
Voltage
Tempera-.
Appear12
ture
ance
Cycle
Capacitance
13
Reference sheet
Test Condition
Solder Temperature : 245± 5℃
Dip Time : 5 ± 0.5 sec.
Immersing Speed : 25±10% mm/s
Solder
: Lead Free Solder
Flux
:Rosin
Preheat : At 80~120 ℃ for 10~30sec.
No mechanical damage shall occur.
ClassⅡ capacitor shall be set for 48±4 hours at
room temperature after one hour heat treatment
Characteristic
Cap. Change at 150 +0/-10℃ before initial measure.
Preheat : At 150± 10℃ For 60~120sec.
Within ± 2.5% or
ClassⅠ
±0.25pFwhichever Dip : Solder Temperature of 260± 5℃
(NPO/SL)
Dip Time : 10 ± 1sec.
is larger of initial
Immersing Speed : 25±10% mm/s
value
Flux
:Rosin
Class
X7R
Within ± 10%
Ⅱ
Z5U/Y5U Within ± 20%
Measure at room temperature after cooling for
To satisfy the specified initial value
ClassⅠ: 24 ± 2 Hours
ClassⅡ: 48 ± 4 Hours
To satisfy the specified initial value
To satisfy the specified initial value
To satisfy the specified initial value
No mechanical damage shall occur
Characteristic
ClassⅠ
(NPO/SL)
ClassⅡ capacitor shall be set for 48± 4 hours at
room temperature after one hour heat treatment
at 150 +0/-10 ℃ before initial measure.
Cap. Change
Within ± 2.5% or
±0.25pFwhichever Capacitor shall be subjected to five cycles of the
temperature cycle as following:
is larger of initial
value
Step
Temp.(℃)
Time(min)
Class
X7R
Within ± 7.5%
1 Min Rated Temp. +0/-3
30
Ⅱ
Z5U/Y5U Within ± 20%
2
25
3
Q
To satisfy the specified initial value
3 Max Rated Temp. +3/-0
30
ClassⅠ
4
25
3
Tan δ
To satisfy the specified initial value
Measure at room temperature after cooling for
ClassⅡ
ClassⅠ:24 ± 2 Hrs
Insulation To satisfy the specified initial value
ClassⅡ:48 ± 4 Hrs
Resistance
Solder the capacitor on P.C. board shown in Fig
2. before testing.
Humidity AppearNo mechanical damage shall occur
ClassⅡ capacitor shall be set for 48± 4 hours at
ance
room temperature after one hour heat treatment
at 150+0/-10 ℃ before initial measure.
CapacitCharacteristic
Cap. Change
Temperature : 40± 2℃
ance
ClassⅠ
Within ± 5.0% or
(NPO/SL)
±0.5pF whichever is Relative Humidity : 90 ~ 95%RH
larger of initial value Test Time : 500 ＋12/－0Hr
Class
X7R
Within ± 15%
Measure at room temperature after cooling for
Ⅱ
Z5U/Y5U Within ± 30%
ClassⅠ : 24 ± 2Hrs
Q
More Than 30pF : Q ≧350
ClassⅡ : 48 ± 4Hrs
ClassⅠ 30pF & Below: Q ≧275 ＋2.5×C
Tan δ
Char.
Maximum
Solder the capacitor on P.C. board shown in Fig
ClassⅡ
X7R
5.0%
2. before testing.
Z5U/Y5U
5.0%
Insulation 1,000MΩ or 50/C Ω whichever is
Resistance smaller.
Page : 5/15
MULTILAYER CERAMIC CHIP CAPACITORS
No.
Item
Specification
Reference sheet
Test Condition
ClassⅡ capacitors applied DC voltage (following
table) is applied for one hour at maximum
Characteristic
Cap. Change operation temperature ±3℃ then shall be set for
ClassⅠ
Within ±3.0% or 48±4 hours at room temperature and the initial
(NPO/SL)
± 0.3pFwhichever measurement shall be conducted.
is larger
Voltage Conditioning :
Class
X7R
Within ± 15%
For information which product has which applied
Ⅱ
Z5U/Y5U Within ± 30%
voltage, please contact with HEC sales representative.
Q
More Than 30pF : Q ≧ 350
ClassⅠ 30pF & Below:Q ≧ 275 ＋ 2.5× C
Tan δ
Char.
maximum
Current Applied : 50 mA Max.
ClassⅡ
X7R
5.0%
Measure at room temperature after cooling for
Z5U/Y5U
5.0%
ClassⅠ: 24 ± 2 Hours
Insulation 1,000MΩ or 50/C Ω whichever is
ClassⅡ: 48 ± 4 Hours
Resistance smaller.
(C in Farad)
High
Appear14
Temperature ance
Load
Capacitance
15
Vibration
Appearance
Capacitance
No mechanical damage shall occur
No mechanical damage shall occur
Characteristic
ClassⅠ
(NPO/SL)
Solder the capacitor on P.C. Board shown in
Fig 2. before testing.
Cap. Change
Vibrate the capacitor with amplitude of 1.5mm
Within ± 2.5% or
± 0.25pFwhichever P-P changing the frequencies from 10Hz to
55Hz and back to 10Hz in about 1 min.
is larger
Class
X7R
Within ± 7.5%
Repeat this for 2 hours each in 3perpendicular
Ⅱ
Z5U/Y5U Within ± 20%
directions.
To satisfy the specified initial value
Q
ClassⅠ
Tan δ
To satisfy the specified initial value
ClassⅡ
Insulation To satisfy the specified initial value
Resistance
Page : 6/15
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
Fig.1
P.C. Board for Bending Strength Test
Solder Resist
Copper
C
40mm
Material : Glass Epoxy Substrate
A
: Copper (Thickness : 0.035mm)
B
: Solder Resist
100mm
1.6mm
Fig.2
Test Substrate
Solder Resist
Copper
C
Material : Glass Epoxy Substrate
A
40mm
B
: Copper (Thickness : 0.035mm)
: Solder Resist
Thickness : 1.6 mm
100mm
Unit:mm
Type
0201
0402
0603
0805
1206
1210
1808
1812
2208
2211
2220
A
0.2
0.5
1.0
1.2
2.2
2.2
3.5
3.5
4.5
4.5
4.5
B
0.9
1.5
3.0
4.0
5.0
5.0
7.0
7.0
8.0
8.0
8.0
Page : 7/15
C
0.4
0.6
1.0
1.6
2.0
2.9
2.5
3.7
2.5
3.0
5.6
MULTILAYER CERAMIC CHIP CAPACITORS
8. Packing
8.1 Bulk Packing
According to customer request.
8.2 Chip Capacitors Tape Packing
Chip Section
Empty Section
40mm min.
Empty Section
20mm min.
Drawing Direction
400mm min.
8.3 Material And Quantity
Tape
Material
Paper
Plastic
0201
T≦0.33mm
15,000 pcs/Reel
NA
0402
T≦0.55mm
10,000 pcs/Reel
NA
0603/0805
T≦0.90mm
T＞0.90mm
4,000 pcs/Reel
NA
NA
3,000 pcs/Reel
Tape
Material
Paper
Plastic
T≦0.90mm
4,000 pcs/Reel
NA
1206
0.90mm＜T≦1.25mm
NA
3,000 pcs/Reel
T＞1.25mm
NA
2,000 pcs/Reel
Tape
Material
Paper
Plastic
T≦1.25mm
NA
3000 pcs/Reel
1808/1210
1.25mm＜T≦2.40mm
NA
2000 pcs/Reel
T＞2.40mm
NA
500/1,000 pcs/Reel
Tape
1812/2211/2220
1825/2225
2208
Material T≦2.20mm T＞2.20mm T≦2.20mm T＞2.20mm
T≦2.20mm
Paper
NA
NA
NA
NA
NA
Plastic 1000 pcs/Reel 700 pcs/Reel 700 pcs/Reel 400 pcs/Reel 1000 pcs/Reel
NA：Not Available
8.4 Cover Tape Reel Off Force
8.4.1 Peel-Off Force
5 g·f ≦Peel-Off Force ≦70 g·f
8.4.2 Measure Method
165 to 180°
Top Tape
Bottom Tape
Page : 8/15
Reference sheet
MULTILAYER CERAMIC CHIP CAPACITORS
8.5 Paper Tape
Pitch Hold
Reference sheet
Chip Inserting Hole
I
F
A
G
B
C
t
D
H
E
Unit:mm
TYPE
0201
0402
0603
0805
1206
1210
A
0.37±
0.61±
1.10±
1.50±
1.90±
2.90±
B
0.67±
1.20±
1.90±
2.30±
3.50±
3.60±
TYPE
0201
0402
0603
0805
1206
1210
F
1.75± 0.10
0.1
0.1
0.2
0.2
0.2
0.2
0.1
0.1
0.2
0.2
0.2
0.2
G
3.50± 0.05
C
4.00± 0.1
D
2.00± 0.05
E
2.00± 0.1
4.00± 0.1
H
8.0± 0.30
I
φ 1.50 +0.10/-0
t
1.10 max.
8.6 Plastic Tape
Pitch Hold
Chip Inserting Hole
I
F
A
G
B
t
O
C
D
E
J
Type
0805
1206
1210
1808
1812
1825
2208
2211
2220
2225
H
Unit:mm
A
1.5±0.2
1.9±0.2
2.9±0.2
2.5±0.2
3.6±0.2
6.9±0.2
2.5±0.2
3.2±0.2
5.4±0.2
6.9±0.2
B
2.3±0.2
3.5±0.2
3.6±0.2
4.9±0.2
4.9±0.2
4.9±0.2
6.1±0.2
6.1±0.2
6.1±0.2
6.1±0.2
C
4.0± 0.1
D
2.0± 0.05
E
4.0± 0.1
8.0± 0.1
Page : 9/15
F
1.75± 0.1
MULTILAYER CERAMIC CHIP CAPACITORS
Type
0805
1206
1210
1808
1812
1825
2208
2211
2220
2225
G
3.5± 0.05
H
8.0± 0.3
5.5± 0.05
12.0 ± 0.3
I
φ 1.5+0.1/-0
J
3.0 max.
t
0.3 max.
4.0 max.
Reference sheet
O
1.0± 0.1
1.5± 0.1
8.7 Reel Dimensions
Reel Material：Polystyrene
E
C
B
D
A
W
Unit:mm
Type
0201
0402
0603
0805
1206
1210
1808
1812
1825
2208
2211
2220
2225
A
φ 382 max
B
φ 50 min
φ 178±0.2
φ 60±0.2
C
φ 13± 0.5
D
φ 21± 0.8
E
2.0±0.5
W
10± 0.15
13±0.3
Page : 10/15
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
Precautionary Notes:
1. Storage
Store the capacitors where the temperature and relative humidity don’t exceed 40°C and 70%RH. We
recommend that the capacitors be used within 12 months from the date of manufacturing. Store the products in
the original package and do not open the outer wrapped, polyethylene bag, till just before usage. If it is open, seal
it as soon as possible or keep it in a desiccant with a desiccation agent.
2. Construction of Board Pattern
Improper circuit layout and pad/land size may cause excessive or not enough solder amount on the PC board.
Not enough solder may create weak joint, and excessive solder may increase the potential of mechanical or
thermal cracks on the ceramic capacitor. Therefore we recommend the land size to be as shown in the following
table:
2.1 Size and recommend land dimensions for reflow soldering .
Capacitor
C
Slit
0201
0402
0603
0805
1206
1210
1808
1812
1825
2208
2211
2220
2225
E
D
B
Chip (mm)
L
W
0.60 0.30
1.00 0.50
1.60 0.80
2.00 1.25
3.20 1.60
3.20 2.50
4.60 2.00
4.60 3.20
4.60 6.35
5.70 2.00
5.70 2.80
5.70 5.00
5.70 6.35
EIA Code
Land
Solder Resistor
A
A
0.2~0.3
0.3~0.5
0.4~0.6
0.7~0.9
2.2~2.4
2.2~2.4
2.8~3.4
2.8~3.4
2.8~3.4
4.0~4.6
4.0~4.6
4.0~4.6
4.0~4.6
B
0.2~0.4
0.3~0.5
0.6~0.7
0.6~0.8
0.8~0.9
1.0~1.2
1.8~2.0
1.8~2.0
1.8~2.0
2.0~2.2
2.0~2.2
2.0~2.2
2.0~2.2
Land (mm)
C
0.2~0.4
0.4~0.6
0.6~0.8
0.8~1.1
1.0~1.4
1.8~2.3
1.5~1.8
2.3~3.0
5.1~5.8
1.5~1.8
2.0~2.6
3.5~4.8
5.1~5.8
D
----1.0~2.0
1.0~2.0
1.0~2.8
1.0~2.8
1.0~4.0
1.0~4.0
1.0~4.0
1.0~4.0
1.0~4.0
2.2 Mechanical strength varies according to location of chip capacitors on the P.C. board.
Design layout of components on the PC board such a way to minimize the stress imposed on the
components, upon flexure of the boards in depanelization or other processes.
Component layout close to the edge of the board or the “depanelization line” is not recommended.
Susceptibility to stress is in the order of: a>b>c and d>e
e
b
perforation
a
c
slit
d
Page : 11/15
E
----3.2~3.7
4.1~4.6
3.6~4.1
4.8~5.3
7.1~8.3
3.6~4.1
4.4~4.9
6.6~7.1
7.1~8.3
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
2.3 Layout Recommendation
Example
Use of Common
Solder Land
Solder With Chassis
Lead Wire
Need to Avoid
Chip
Use of Common Solder
Land With Other SMD
Chassis
Solder
Excessive
Solder
Solder Land
Adhesive
Solder Land
PCB
Recommendation
Lead Wire
Chip
α
Solder Resist
Solder Resist
Adhesive
PCB
Solder Land
β
α >β
3. Mounting
3.1 Sometimes crack is caused by the impact load due to suction nozzle in pick and place operation.
In pick and place operation, if the low dead point is too low, excessive stress is applied to component. This may
cause cracks in the ceramic capacitor, therefore it is required to move low dead point of a suction nozzle to the
higher level to minimize the board warp age and stress on the components. Nozzle pressure is typically
adjusted to 1N to 3N (static load) during the pick and place operation.
Excessive Stress
Nozzle
Warping of Board
Warping of Board
PCB
Crack
Support pin
3.2 Amount of Adhesive
b
a
a
Example : 0805 & 1206
0.2mm min.
a
b
c
c
70 ~ 100 μm
Do not touch the solder land
c
Page : 12/15
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
Temperature (C)
4. Soldering
4.1. Wave Soldering
Most of components are wave soldered with solder at 230 to 250°C. Adequate care must be taken to prevent
the potential of thermal cracks on the ceramic capacitors. Refer to the soldering methods below for optimum
soldering benefits.
Recommend flow soldering temperature Profile
Soldering
Pre-heating
Cooling
300
Soldering Method
Change in Temp.( ℃)
250
1206 and Under
Δ T ≤ 100~130 max.
230
200
ΔT
120seconds or more
60seconds or more
2 to 3 sec.
To optimize the result of soldering, proper preheating is essential:
1) Preheat temperature is too low
a. Flux flows to easily
b. Possibility of thermal cracks
2) Preheat temperature is too high
a. Flux deteriorates even when oxide film is removed
b. Causes warping of circuit board
c. Loss of reliability in chip and other components
Cooling Condition:
Natural cooling using air is recommended. If the chips are dipped into a solvent for cleaning, the temperature
difference (Δ T) between the solvent and the chips must be less than 100°C.
4.2 Reflow Soldering
Preheat and gradual increase in temperature to the reflow temperature is recommended to decrease the
potential of thermal crack on the components. The recommended heating rate depends on the size of
component, however it should not exceed 3°C/Sec.
Recommend reflow profile for Lead-Free soldering temperature Profile (MIL-STD-202G #210F)
Soldering Cooling
Pre-heating
※ The cycles of soldering : Twice (max.)
260C max./10sec.
Min.
260max.
217
Soldering Method
1206 and Under
1210 and Over
Temperature (C)
ΔT
150C /60sec. Min.
70 to 90 sec.
Page : 13/15
Change in Temp.( ℃)
Δ T ≦ 190 ℃
Δ T ≦ 130 ℃
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
4.3 Hand Soldering
Sudden temperature change in components, results in a temperature gradient recommended in the following
table, and therefore may cause internal thermal cracks in the components. In general a hand soldering method
is not recommended unless proper preheating and handling practices have been taken. Care must also be
taken not to touch the ceramic body of the capacitor with the tip of solder Iron.
350
250
200
Temperature (C)
Change in Temp.( ℃)
Δ T ≦ 150 ℃
Δ T ≦ 130 ℃
Soldering Method
1206 and Under
1210 and Over
ΔT
Within 5 seconds.
How to Solder Repair by Solder Iron
1) Selection of the soldering iron tip
The required temperature of solder iron for any type of repair depends on the type of the tip, the substrate
material, and the solder land size.
2) recommended solder iron condition
a.) Preheating Condition：Board and components should be preheated sufficiently at 150°C or over,
and soldering should be conducted with soldering iron as boards and components are maintained
at sufficient temperatures.
b.) Soldering iron power shall not exceed 30 W.
c.) Soldering iron tip diameter shall not exceed 3mm.
d.) Temperature of iron tip shall not exceed 350°C., and the process should be finished within 5 seconds.
( refer to MIL-STD-202G)
f.) Do not touch the ceramic body with the tip of solder iron. Direct contact of the soldering iron tip to ceramic
body may cause thermal cracks.
g.) After soldering operation, let the products cool down gradually in the room temperature.
5. Handling after chip mounted
5.1 Proper handling is recommended, since excessive bending and twist of the board, depends on the orientation
of the chip on the board, may induce mechanical stress and cause internal crack in the capacitor.
Higher potential of crack
Bending
Lower potential of crack
→
Twist
5.2 There is a potential of crack if board is warped due to excessive load by check pin
○
╳
Check pin
Support Pin
Check pin
Page : 14/15
MULTILAYER CERAMIC CHIP CAPACITORS
Reference sheet
5.3 Mechanical stress due to warping and torsion.
(a) Crack occurrence ratio will be increased by manual separation.
(b) Crack occurrence ratio will be increased by tensile force , rather than compressive force.
╳ :Tensile Stress
○ :Compressive Stress
Crack
6. Handling of Loose Chip Capacitor
6.1 If dropped the chip capacitor may crack.
Crack
Floor
6.2 In piling and stacking of the P.C. boards after mounting for storage or handling, the corner of the P.C. board
may hit the chip capacitor mounted on another board to cause crack.
PCB
Crack
7. Safekeeping condition and period
For safekeeping of the products, we recommend to keep the storage temperature between +5 to +40°C and
under humidity of 20 to 70% RH. The shelf life of capacitors is 12 months.
Page : 15/15
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