16910A

Agilent Technologies Measurement Modules for the 16900 Series Data Sheet Modularity is the key to the Agilent 16900 Series logic analysis systems’ long term value. You purchase only the capability you need now, then expand as your needs evolve. All modules are tightly integrated to provide time-correlated, cross domain measurements. Customize your system with the measurement capability that will meet your performance and price needs. Protect your investment by upgrading logic analyzer module memory depths or state speeds as your needs change. Measurement Capability: • Timing/State logic analyzers • Pattern Generator • Time Correlation to external scopes Timing/State Logic Analyzer Modules Agilent’s timing and state modules give you the power to: • Accurately measure precise timing relationships using 4 GHz (250 ps) timing zoom with 64 K depth. • Extend the measurement window with precision when signals transition less frequently using transitional timing. • Find anomalies separated in time with deep memory depths (up to 256 M across all channels). • Buy what you need today and upgrade in the future. 16900 Series timing/state modules come with independent upgrades for memory depth and state speed. • Sample high-speed synchronous buses accurately and confidently using eye finder. Eye finder automatically adjusts threshold and setup and hold for your highest confidence in measurements on high-speed buses. • Track problems from symptom to root cause across several measurement modes by viewing time-correlated data in waveform/chart, listing, inverse assembly, source code, or compare display. • Set up triggers quickly and confidently with intuitive simple, quick, and advanced triggering. This capability combines new trigger functionality with an intuitive user interface. • The Agilent logic analyzer modules are compatible with the industry’s widest range of probing accessories with capacitive loading down to 0.7 pF. • Monitor and correlate multiple buses using a single module with split analyzer capability. This provides single and multi-bus support using a single module (timing, state, timing/state or state/state configurations). Logic Analyzer Selection Guide for 16900 Series Mainframes Agilent Model Number Channels per module Maximum channels on single time base Timing Mode High-speed timing zoom [1] Maximum timing sample rate: half channel mode Maximum timing sample rate: full channel mode Transitional timing State Mode Maximum state clock rate Maximum state data rate Setup/hold window Adjustment resolution State clock, data rate (upgradeable) Automated threshold/sample position, Simultaneous eye diagrams, all channels Memory Depth [2] 256 M 64 M 32 M 16 M 4M 1M 256 K Memory depth (upgradeable) Other Supported signal types Probe compatibility [3] Voltage threshold Threshold Accuracy 16910A/16911A 102/68 510/340 16950B/16951B 68 340 16760A 34 170 4 GHz (250 ps) with 64 K depth 1.0 GHz (1 ns) 500 MHz (2.0 ns) 500 MHz (2.0 ns) 4 GHz (250 ps) with 64 K depth 1.2 GHz (833 ps) 600 MHz (1.67 ns) 600 MHz (1.67 ns) N/A 800 MHz 800 MHz 400 MHz 450 MHz with option 500, 250 MHz with option 250 500 Mb/s with option 500, 250 Mb/s with option 250 1.5 ns 80 ps typical Yes (Agilent E5865A for 16910A) (Agilent E5866A for 16911A) Yes 667 MHz 667 Mb/s (DDR) 1066 Mb/s (Dual Sample) 1 ns (600 ps typical), 80 ps typical No Yes 800 Mb/s (full channel), 1.5 Gb/s (half channel) 1.5 Gb/s 1 ns 10 ps No Yes Option 032 Option 016 Option 004 Option 001 Option 256 Yes (Agilent E5865A for 16910A) (Agilent E5866A for 16911A) 16951B 16950B, Option 064 16950B, Option 032 16950B, Option 016 16950B, Option 004 16950B, Option 001 Yes (Agilent E5875A) 16760A 64 M standard Single-ended 40-pin cable connector –5 V to 5 V (10 mV increments) ±50 mV + 1% of setting Single-ended and differential 90-pin cable connector –3 V to 5 V (10 mV increments) ±30 mV ±2% of setting Single-ended and differential 90-pin cable connector –3 V to 5 V (10 mV increments) ±(30 mV + 1% of setting) [1] All channels, all the time, simultaneous state and timing through same probe. [2] Specify desired memory depth using available options. [3] Probes are ordered separately. Please specify probes when ordering to ensure the correct connection between your logic analyzer and the device under test. 2 Data Acquisition and Stimulus Timing/State Modules Agilent logic analyzer modules offer the speed, features, and usability your digital development team needs to quickly debug, validate, and optimize your digital system – at a price that fits your budget. Accurately measure precise timing relationships Make accurate high-speed timing measurements with 4 GHz (250 ps) high-speed timing zoom. A parallel acquisition architecture provides high-speed timing measurements simultaneously through the same probe with other state or timing measurements. Timing zoom stays active all the time with no tradeoffs. View data at high resolution over longer periods of time with 64 K deep timing zoom. Automate measurement setup and quickly gain diagnostic clues Quickly get up and running by automating your measurement setup process. In addition, the logic analyzer’s setup/hold window (or sampling position) and threshold voltage settings are automatically determined so that data on high-speed buses is captured with the highest accuracy. Auto Threshold and Sample Position mode allows you to... • Obtain accurate and reliable measurements • Save time during measurement setup • Gain diagnostic clues and identify problem signals quickly • Scan all signals and buses simultaneously or just a few • View results as a composite display or as individual signals • See skew between signals and buses • Find and fix inappropriate clock thresholds • Measure data valid windows • Identify signal integrity problems related to rise times, fall times, data valid window widths Identify problem signals over hundreds of channels simultaneously As timing and voltage margins continue to shrink, confidence in signal integrity becomes an increasingly vital requirement in the design validation process. Eye scan lets you acquire signal integrity information on all the buses in your design, under a wide variety of operating conditions, in a matter of minutes. Identify problem signals quickly for further investigation with an oscilloscope. Results can be viewed for each individual signal or as a composite of multiple signals or buses. Figure 1. Identify problem signals quickly by viewing eye diagrams across all buses and signals simultaneously. 3 Data Acquisition and Stimulus Pattern Generation Modules Digital Stimulus and Response in a Single Instrument Configure the logic analysis system to provide both stimulus and response in a single instrument. For example, the pattern generator can simulate a circuit initialization sequence and then signal the state or timing analyzer to begin measurements. Use the compare mode on the state analyzer to determine if the circuit or subsystem is functioning as expected. Time correlate to an external oscilloscope to help locate the source of timing problems or troubleshoot signal problems due to noise, ringing, overshoot, crosstalk, or simultaneous switching. Parallel Testing of Subsystems Reduces Time to Market By testing system subcomponents before they are complete, you can fix problems earlier in the development process. Use the Agilent 16720A as a substitute for missing boards, integrated circuits (ICs), or buses instead of waiting for the missing pieces. Software engineers can create infrequently encountered test conditions and verify that their code works—before complete hardware is available. Hardware engineers can generate the patterns necessary to put their circuit in the desired state, operate the circuit at full speed or step the circuit through a series of states. Key Characteristics Agilent Model 16720A Maximum clock (full/half channel) Number of data channels (full/half channel) Memory depth (full/half channels) Maximum vector width (5 module system, full/half channel) Logic levels supported 180/300 MHz 48/24 Channels 8/16 MVectors 240/120 Bits 5V TTL, 3-state TTL, 3-state TTL/CMOS, 3-state 1.8V, 3-state 2.5V, 3-state 3.3V, ECL, 5V PECL, 3.3V LVPECL, LVDS 8/16 MVectors Editable vector size (full/half channels) 4 Data Acquisition and Stimulus Pattern Generation Modules Vectors Up To 240 Bits Wide Vectors are defined as a “row” of labeled data values, with each data value from one to 32 bits wide. Each vector is output on the rising edge of the clock. Up to five, 48-channel 16720A modules can be interconnected within a 16900 Series mainframe. This configuration supports vectors of any width up to 240 bits with excellent channel-to-channel skew characteristics (see specific data pod characteristics in Pattern Generation Modules Specifications starting on page 23). The modules operate as one time-base with one master clock pod. Multiple modules also can be configured to operate independently with individual clocks controlling each module. Depth Up to 16 MVectors With the 16720A pattern generator, you can load and run up to 16 MVectors of stimulus. Depth on this scale is most useful when coupled with powerful stimulus generated by electronic design automation tools, such as SynaptiCAD’s WaveFormer and VeriLogger. These tools create stimulus using a combination of graphically drawn signals, timing parameters that constrain edges, clock signals, and temporal and Boolean equations for describing complex signal behavior. The stimulus also can be created from design simulation waveforms. The SynaptiCAD tools allow you to convert .VCD files into .PGB files directly, offering you an integrated solution that saves you time. Synchronized Clock Output You can output data synchronized to either an internal or external clock. The external clock is input via a clock pod, and has no minimum frequency (other than a 2 ns minimum high time). The internal clock is selectable between 1 MHz and 300 MHz in 1 MHz steps. A Clock Out signal is available from the clock pod and can be used as an edge strobe with a variable delay of up to 8 ns. Initialize (INIT) Block for Repetitive Runs When running repetitively, the vectors in the initialize (init) sequence are output only once, while the main sequence is output as a continually repeating sequence. This “init” sequence is very useful when the circuit or subsystem needs to be initialized. The repetitive run capability is especially helpful when operating the stimulus module independent of the other modules in the logic analysis system. “Send Arm out to…” Coordinates System Module Activity A “Send Arm out to…” instruction acts as a trigger arming event for other logic analysis modules to begin measurements. Arm setup and trigger setup of the other logic analysis modules determine the action initiated by “Send Arm out to…”. “Wait for External Event” for Input Pattern The clock pod also accepts a 3-bit input pattern. These inputs are level-sensed so that any number of “Wait for External Event” instructions can be inserted into a stimulus program. Up to four pattern conditions can be defined from the OR-ing of the eight possible 3-bit input patterns. A “Wait for External Event” also can be defined to wait for an Arm. This Arm signal can come from any other module in the logic analysis system. Figure 2. Define your unique stimulus vectors, including an initialization sequence, in the Sequence tab. 5 Data Acquisition and Stimulus Pattern Generation Modules “User-Defined Macro” and “Loop” Simplify Creation of Stimulus Programs User macros permit you to define a pattern sequence once, then insert the macro by name wherever it is needed. Passing parameters to the macro will allow you to create a more generic macro. For each call to the macro you can specify unique values for the parameters. Loops enable you to repeat a defined block of vectors for a specified number of times. Loops and macros can be nested, except that a macro can not be nested within another macro. At compile time, loops and macros are expanded in memory to a linear sequence. Convenient Data Entry and Editing Feature You can conveniently enter patterns in hex, octal, binary, decimal, and signed decimal (two’s complement) bases. The data associated with an individual label can be viewed with multiple radixes to simplify data entry. Delete, Insert, and Copy commands are provided for easy editing. Fast and convenient Pattern Fills give the programmer useful test patterns with a few key strokes. Fixed, Count, Rotate, Toggle, and Random are available to quickly create a test pattern, such as “walking ones.” Pattern parameters, such as Step Size and Repeat Frequency, can be specified in the pattern setup. ASCII Input File Format: Your Design Tool Connection The 16720A supports an ASCII file format to facilitate connectivity to other tools in your design environment. Because the ASCII format does not support the instructions listed earlier, they cannot be edited into the ASCII file. User macros and loops also are not supported, so the vectors need to be fully expanded in the ASCII file. Many design tools will generate ASCII files and output the vectors in this linear sequence. Data must be in Hex format, and each label must represent a set of contiguous output channels. Configuration The 16720A pattern generators require a single slot in a logic analysis system frame. The pattern generator operates with the clock pods, data pods, and lead sets described later in this section. At least one clock pod and one data pod must be selected to configure a functional system. Users can select from a variety of pods to provide the signal source needed for their logic devices. The data pods, clock pods and data cables use standard connectors. The electrical characteristics of the data cables also are described for users with specialized applications who want to avoid the use of a data pod. The 16720A can be configured in systems with up to five cards for a total of 240 channels of stimulus. Direct Connection to Your Target System The pattern generator pods can be directly connected to a standard connector on your target system. Use a 3M brand #2520 Series, or similar connector. The 16720A clock or data pods will plug right in. Short, flat cable jumpers can be used if the clearance around the connector is limited. Use a 3M #3365/20, or equivalent, ribbon cable; a 3M #4620 Series, or equivalent, connector on the 16720A pod end of the cable; and a 3M #3421 Series, or equivalent, connector at your target system end of the cable. Probing Accessories The probe tips of the Agilent 10474A, 10347A, 10498A, and E8142A lead sets plug directly into any 0.1 inch grid with 0.026 inch to 0.033 inch diameter round pins or 0.025 inch square pins. These probe tips work with the Agilent 5090-4356 surface mount grabbers and with the Agilent 5959-0288 through-hole grabbers. 6 Agilent 16910A and 16911A Specifications and Characteristics Module Channel Counts 1-card module 2-card module 3-card module 4-card module 5-card module State Analysis 16910A 98 data + 4 clocks 200 data + 4 clocks 302 data + 4 clocks 404 data + 4 clocks 506 data + 4 clocks State Analysis 16911A 64 data + 4 clocks 132 data + 4 clocks 200 data + 4 clocks 268 data + 4 clocks 336 data + 4 clocks Timing Analysis 16910A 102 204 306 408 510 Timing Analysis 16911A 68 136 204 272 340 Probes A probe must be used to connect the logic analyzer to your target system. Probes are ordered separately from the logic analysis module. For specifications and characteristics of a particular probe, see the documentation that is supplied with your probe or search for the probe’s model number in this help system or at www.agilent.com or Probing Solutions for Agilent Technologies Logic Analyzers Product Overview, publication number 5968-4632E. Timing Zoom Timing analysis sample rate Time interval accuracy Within a pod pair Between pod pairs Memory depth Trigger position Minimum data pulse width 4 GHz ± (1.0 ns + 0.01% of time interval reading) ± (1.75 ns + 0.01% of time interval reading) 64 K samples Start, center, end, or user-defined 1 ns 7 Agilent 16910A and 16911A Specifications and Characteristics State (Synchronous) Analysis Mode tWidth* [1] tSetup tHold tSample range [2] tSample adjustment resolution Maximum state data rate on each channel Maximum channels on a single time base and trigger [4] Memory depth [4] (Option 256 is included in base price) Option 250 1.5 ns 0.5 tWidth 0.5 tWidth –3.2 ns to +3.2 ns 80 ps typical 250 Mb/s 16910A: 510 – (number of clocks) 16911A: 340 – (number of clocks) Option 256: Option 001: Option 004: Option 016: Option 032: 2 4 4 4.0 ns 256 K samples 1 M samples 4 M samples 16 M samples 32 M samples Option 500 1.5 ns 0.5 tWidth 0.5 tWidth –3.2 ns to +3.2 ns 80 ps typical 500 Mb/s 16910A: 510 – (number of clocks) 16911A: 340 – (number of clocks) Option 256: Option 001: Option 004: Option 016: Option 032: 1 1 N/A 2.0 ns 256 K samples 1 M samples 4 M samples 16 M samples 32 M samples Number of independent analyzers [5] Number of clocks [6] Number of clock qualifiers [6] Minimum time between active clock edges* [7] Minimum master to slave clock time Minimum slave to master clock time Minimum slave to slave clock time * [1] [2] 1 ns 1 ns 4.0 ns N/A N/A N/A [3] [4] [5] [6] [7] Items marked with an asterisk (*) are specifications. All others are characteristics. “Typical” represents the average or median value of the parameter based on measurements from a significant number of units. Minimum eye width in system under test. Sample positions are independently adjustable for each data channel input. A negative sample position causes the input to be synchronously sampled by that amount before each active clock edge. A positive sample position causes the input to be synchronously sampled by that amount after each active clock edge. A sampling position of zero causes the input to be synchronously sampled coincident with each clock edge. Use of eye finder is recommended in 450 MHz and 500 Mb/s state mode. In 250 Mb/s state mode, with all pods assigned, memory depth is half the maximum memory depth. With one pod pair (34 channels) unassigned, the memory depth is full. One pod pair (34 channels) must remain unassigned for time tags in 500 Mb/s state mode. Independent analyzers may be either state or timing. When the 500 Mb/s state mode is selected, only one analyzer may be used. In the 250 Mb/s state mode, the total number of clocks and qualifiers is 4. All clock and qualifier inputs must be on the master modules. Tested with input signal Vh = +1.3 V, Vl = +0.7 V, threshold = +1.0 V, tr/tf = 180 ps ± 30 ps (10%, 90%). tWidth Individual Data Channel vHeight Data Eye tSetup tHold Sampling Position vThreshold OV tSample Clock Channel 8 Agilent 16910A and 16911A Specifications and Characteristics State (Synchronous) Analysis Mode Minimum state clock pulse width Single edge Multiple edge Clock qualifier setup time Clock qualifier hold time Time tag resolution Maximum time count between stored states Maximum trigger sequence speed Maximum trigger sequence levels Trigger sequence level branching Trigger position Trigger resources Option 250 Option 500 1.0 ns 1.0 ns 500 ps 0 2 ns 32 days 250 MHz 16 Arbitrary 4-way if/then/else Start, center, end, or user-defined 16 patterns evaluated as =, =/, >, ≥, , ≥, , ≥, , ≥, , ≥, , ≥, , ≥, , ≥, , , , , , , , 180 MHz and ≤ 300 MHz clock Number of output channels at ≤ 180 MHz clock Number of different macros Maximum number of lines in a macro Maximum number of parameters in a macro Maximum number of macro invocations Maximum loop count in a repeat loop Maximum number of repeat loop invocations Maximum number of “Wait” event patterns Number of input lines to define a pattern Maximum number of modules in a system Maximum width of a vector (in a 5 module system) Maximum width of a label Maximum number of labels Maximum number of vectors in all formats Minimum number of vectors in binary format when loading into hardware 1000 4 3 5 240 bits 128 bits limited only by system memory 16 MVectors 4096 16 MVectors 24 48 limited only by the pattern generator’s available memory depth Lead Set Characteristics Agilent 10474A 8-channel probe lead set* Provides most cost effective lead set for the 16720A clock and data pods. Grabbers are not included. Lead wire length is 12 inches. Provides 50 Ω coaxial lead set for unterminated signals, required for 10465A ECL Data Pod (unterminated). Grabbers are not included. Provides most cost effective lead set for the 16720A clock and data pods. Grabbers are not included. Lead wire length is 6 inches. Provides lead set for the 16720A LVDS clock and data pods. Grabbers are not included. Lead wire length is 6 inches. Agilent 10347A 8-channel probe lead set Agilent 10498A 8-channel probe lead set* Agilent E8142A 8-channel probe lead set * For all clock and data pods except 10465A unterminated ECL Data Pod and E8140A/E8141A clock and data pods. 23 Agilent 16720A Pattern Generator Specifications and Characteristics Data Pod Characteristics Note: Data Pod output parametrics depend on the output driver and the impedance load of the target system. Check the device data book for the specific drivers listed for each pod. Agilent 10461A TTL Data Pod Output type Maximum clock Skew [1] 10H125 with 100 Ω series 200 MHz typical < 2 ns; worst case = 4 ns ECL/TTL 10H125 100 Ω Recommended lead set Agilent 10474A Agilent 10462A 3-State TTL/CMOS Data Pod Output type 74ACT11244 with 100 Ω series; 10H125 on non 3-state channel 7 [2] negative true, 100 KΩ to GND, enabled on no connect 100 MHz typical < 4 ns; worst case = 12 ns 74ACT11244 100 Ω 3-state enable Maximum clock Skew [1] Recommended lead set Agilent 10474A Agilent 10464A ECL Data Pod (terminated) Output type Maximum clock Skew [1] 10H115 with 330 Ω pulldown, 47 Ω series 300 MHz typical < 1 ns; worst case = 2 ns 10H115 348 Ω – 5.2 V 42 Ω Recommended lead set Agilent 10474A [1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst case skew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channel within a single or multiple module system. [2] Channel 7 on the 3-state pods has been brought out in parallel as a non 3-state signal. By looping this output back into the 3-state enable line, the channel can be used as a 3-state enable. 24 Agilent 16720A Pattern Generator Specifications and Characteristics Agilent 10465A ECL Data Pod (unterminated) Output type Maximum clock Skew [1] 10H115 (no termination) 300 MHz typical < 1 ns; worst case = 2 ns 10H115 Recommended lead set Agilent 10347A Agilent 10466A 3-State TTL/3.3 volt Data Pod Output type 74LVT244 with 100 Ω series; 10H125 on non 3-state channel 7 [2] negative true, 100 KΩ to GND, enabled on no connect 200 MHz typical < 3 ns; worst case = 7 ns 100 Ω 74LVT244 3-state enable Maximum clock Skew [1] Recommended lead set Agilent 10474A [1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst case skew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channel within a single or multiple module system. [2] Channel 7 on the 3-state pods has been brought out in parallel as a non 3-state signal. By looping this output back into the 3-state enable line, the channel can be used as a 3-state enable. 25 Agilent 16720A Pattern Generator Specifications and Characteristics Agilent 10469A 5 volt PECL Data Pod Output type 100EL90 (5V) with 348 ohm pulldown to ground and 42 ohm in series 300 MHz typical < 500 ps; worst case = 1 ns 100EL90 42 Ω 348 Ω Maximum clock Skew [1] Recommended lead set Agilent 10498A Agilent 10471A 3.3 volt LVPECL Data Pod Output type 100LVEL90 (3.3V) with 215 ohm pulldown to ground and 42 ohm in series 300 MHz typical < 500 ps; worst case = 1 ns 100LVEL90 42 Ω 215 Ω Maximum clock Skew [1] Recommended lead set Agilent 10498A Agilent 10473A 3-State 2.5 Volt Data Pod Output type 3-state enable 74AVC16244 negative true, 38 KΩ to GND, enabled on no connect 300 MHz typical < 1.5 ns; worst case = 2 ns 74AVC16244 Maximum clock Skew [1] Recommended lead set Agilent 10498A [1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst case skew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channel within a single or multiple module system. [2] Channel 7 on the 3-state pods has been brought out in parallel as a non 3-state signal. By looping this output back into the 3-state enable line, the channel can be used as a 3-state enable. 26 Agilent 16720A Pattern Generator Specifications and Characteristics Agilent 10476A 3-State 1.8 Volt Data Pod Output type 3-state enable 74AVC16244 negative true, 38 KΩ to GND, enabled on no connect 300 MHz typical < 1.5 ns; worst case = 2 ns 74AVC16244 Maximum clock Skew [1] Recommended lead set Agilent 10498A Agilent 10483A 3-State 3.3 Volt Data Pod Output type 3-state enable 74AVC16244 negative true, 38 KΩ to GND, enabled on no connect 300 MHz typical < 1.5 ns; worst case = 2 ns 74AVC16244 Maximum clock Skew [1] Recommended lead set Agilent 10498A Agilent E8141A LVDS Data Pod Output type 65LVDS389 (LVDS data lines) 10H125 (TTL non-3-state channel 7) 3.3 V 65LVDS389 ENABLE 10 KΩ LVDS DATA OUT 3-STATE IN TTL 3-state enable Maximum clock Skew positive true TTL; no connect=enabled 300 MHz typical < 1 ns; worst case = 2 ns Recommended lead set: E8142A Recommended lead set Agilent 10498A [1] Typical skew measurements made at pod connector with approximately 10 pF/50 KΩ load to GND; worst case skew numbers are a calculation of worst case conditions through circuits. Both numbers apply to any channel within a single or multiple module system. 27 Agilent 16720A Pattern Generator Specifications and Characteristics Data Cable Characteristics Without a Data Pod The Agilent 16720A data cables without a data pod provide an ECL terminated (1 KΩ to –5.2V) differential signal (from a type 10E156 or 10E154 driver). These are usable when received by a differential receiver, preferably with a 100 Ω termination across the lines. These signals should not be used single ended due to the slow fall time and shifted voltage threshold (they are not ECL compatible). 16720A –3.25 V 470 Ω 10E156 or 10E154 Differential Output 470 Ω –3.25 V 16522A –5.2 V 1 kΩ 10E156 or 10E154 Differential Output 1 kΩ –5.2 V 16720A Cable Pin Outs 28 Agilent 16720A Pattern Generator Specifications and Characteristics Clock Cable Characteristics Without a Clock Pod The Agilent 16720A clock cables without a clock pod provide an ECL terminated (1 KΩ to –5.2V) differential signal (from a type 10E164 driver). These are usable when received by a differential receiver, preferably with a 100 Ω termination across the lines. These signals should not be used single ended due to the slow fall time and shifted voltage threshold (they are not ECL compatible). 7 10E116 100 Ω 8 Clock In 11, 13, 15 10H125 100 Ω 12, 14, 16 Wait 1, 2, 3 IN –3.25 V 215 Ω 10E164 Clock Out 215 Ω –3.25 V 29 Agilent 16720A Pattern Generator Specifications and Characteristics Clock Pod Characteristics 10460A TTL Clock Pod Clock output type Clock output rate Clock out delay 10H125 with 47 Ω series; true & inverted 100 MHz maximum approximately 8 ns total in 14 steps (16720A only); 11 ns maximum in 9 steps (16522A only) TTL – 10H124 dc to 100 MHz TTL – 10H124 (no connect is logic 1) 10H125 47 Ω CLKout Clock input type Clock input rate Pattern input type Clock-in to clock-out Pattern-in to recognition approximately 30 ns approximately 15 ns + 1 clk period 10H124 WAIT CLKin Recommended lead set Agilent 10474A 10463A ECL Clock Pod Clock output type 10H116 differential unterminated; and differential with 330 Ω to –5.2V and 47 Ω series 300 MHz maximum approximately 8 ns total in 14 steps (16720A only); 11 ns maximum in 9 steps (16522A only) ECL – 10H116 with 50 KΩ to –5.2v dc to 300 MHz 10H116 CLKin VBB –5.2 V –5.2 V 50 kΩ Clock output rate Clock out delay Clock input type Clock input rate Pattern input type ECL – 10H116 with 50 KΩ (no connect is logic 0) approximately 30 ns Clock-in to clock-out Pattern-in to recognition 330 Ω approximately 15 ns + 1 clk period 10H116 47 Ω CLKout Recommended lead set Agilent 10474A 30 Agilent 16720A Pattern Generator Specifications and Characteristics 10468A 5 volt PECL Clock Pod Clock output type 100EL90 (5V) with 348 ohm pulldown to ground and 42 ohm in series 300 MHz maximum approximately 8 ns total in 14 steps (16720A only); 11 ns maximum in 9 steps (16522A only) 100EL91 PECL (5V), no termination dc to 300 MHz 100EL91 PECL (5V), no termination (no connect is logic 0) approximately 30 ns approximately 15 ns + 1 clk period 100EL91 CLKin 100EL90 42 Ω 348 Ω CLKout Clock output rate Clock out delay Clock input type Clock input rate Pattern input type Clock-in to clock-out Pattern-in to recognition Recommended lead set Agilent 10498A 10470A 3.3 volt LVPECL Clock Pod Clock output type 100LVEL90 (3.3V) with 215 ohm pulldown to ground and 42 ohm in series 300 MHz maximum approximately 8 ns total in 14 steps (16720A only); 11 ns maximum in 9 steps (16522A only) 100LVEL91 LVPECL (3.3V), no termination dc to 300 MHz 100LVEL91 LVPECL (3.3V), no termination (no connect is logic 0) approximately 30 ns approximately 15 ns + 1 clk period 100LVEL91 CLKin 100LVEL90 42 Ω 215 Ω CLKout Clock output rate Clock out delay Clock input type Clock input rate Pattern input type Clock-in to clock-out Pattern-in to recognition Recommended lead set Agilent 10498A 31 Agilent 16720A Pattern Generator Specifications and Characteristics 10472A 2.5 volt Clock Pod Clock output type Clock output rate Clock out delay 74AVC16244 200 MHz maximum approximately 8 ns total in 14 steps (16720A only); 11 ns maximum in 9 steps (16522A only) 74AVC16244 (3.6V max) dc to 200 MHz 74AVC16244 (3.6V max; no connect is logic 0) approximately 30 ns 74AVC16244 CLKout Clock input type Clock input rate Pattern input type 74AVC16244 Clock-in to clock-out Pattern-in to recognition WAIT CLKin approximately 15 ns + 1 clk period Recommended lead set Agilent 10498A 10475A 1.8 volt Clock Pod Clock output type Clock output rate Clock out delay 74AVC16244 200 MHz maximum approximately 8 ns total in 14 steps (16720A only); 11 ns maximum in 9 steps (16522A only) 74AVC16244 (3.6V max) dc to 200 MHz 74AVC16244 (3.6V max; no connect is logic 0) approximately 30 ns 74AVC16244 CLKout Clock input type Clock input rate Pattern input type 74AVC16244 Clock-in to clock-out Pattern-in to recognition WAIT CLKin approximately 15 ns + 1 clk period Recommended lead set Agilent 10498A 32 Agilent 16720A Pattern Generator Specifications and Characteristics 10477A 3.3 volt Clock Pod Clock output type Clock output rate Clock out delay 74AVC16244 200 MHz maximum approximately 8 ns total in 14 steps (16720A only); 11 ns maximum in 9 steps (16522A only) 74AVC16244 (3.6V max) dc to 200 MHz 74AVC16244 (3.6V max; no connect is logic 0) approximately 30 ns approximately 15 ns + 1 clk period Agilent 10498A 74AVC16244 CLKout Clock input type Clock input rate Pattern input type Clock-in to clock-out Pattern-in to recognition Recommended lead set 74AVC16244 WAIT CLKin E8140A LVDS Clock Pod Clock output type Clock output rate Clock out delay Clock input type Clock input rate Pattern input type Clock-in to clock-out Pattern-in to recognition Recommended lead set 65LVDS179 (LVDS) and 10H125 (TTL) 200 MHz maximum (LVDS and TTL) approximately 8 ns total in 14 steps 65LVDS179 (LVDS with 100 ohm) dc to 150 MHz (LVDS) 10H124 (TTL) (no connect = logic 1) approximately 30 ns approximately 15 ns + 1 clk period Agilent 10498A 10H125 65LBDS179 CLK OUT TTL CLK OUT LVDS CLK IN LVDS 65LVDS179 100 Ω CLK IN LVDS 10H124 WAIT IN TTL 33 Agilent Module Specifications and Characteristics Power Requirements All necessary power is supplied by the backplane connector of the logic analysis system mainframe. Environmental Characteristics Indoor use only Operating Environment Temperature 0 to 40 °C (+32 to +104 °F) when operating in a 16900A or 16902A/B mainframe. 0 to 45 °C (+32 to +113 °F) when operating in a 16901A mainframe. 0 to 50 °C (+32 to +122 °F) when operating in a 16903A mainframe. 0 to 80% relative humidity at 40 °C (+104 °F). Reliability is enhanced when operating within the range 20% to 80% non-condensing. 0 to 3000 m (10,000 ft) Random vibration 5 to 500 Hz, 10 minutes per axis, approximately 0.2 g rms Humidity Altitude Vibration Non-Operating Environment Temperature Humidity Altitude Vibration (in shipping carton) –40 to +75 °C (–40 to +167 °F). Protect the instrument from temperature extremes which cause condensation on the instrument. 0 to 90% at 65 °C (149 °F) 0 to 15,300 m (50,000 ft) Random vibration 5 to 500 Hz, 10 minutes per axis, approximately 2.41 g rms; and swept sine resonant search, 5 to 500 Hz, 0.50 g (0-peak), 5-minute resonant dwell at 4 resonances per axis. See individual probe Specifications and Characteristics for probe environmental characteristics. The 16900 Series logic analysis system also supports the following logic analysis modules. State/Timing Modules 16740A, 16741A, 16742A 16750A/B, 16751A/B, 16752A/B 16753A, 16754A, 16755A, 16756A Related literature Publication title Agilent 16900 Series Logic Analysis System Mainframes Agilent Technologies 16800 Series Portable Logic Analyzers Agilent Technologies 16800 Series Portable Logic Analyzers Agilent Technologies FPGA Dynamic Probe for Xilinx Agilent Technologies FPGA Dynamic Probe for Altera Probing Solutions for Agilent Technologies Logic Analyzers Application Support for Agilent Logic Analyzers Innovative Digital Debug Solutions CD with Videos 34 Publication type Data Sheet Brochure Data Sheet Data Sheet Data Sheet Catalog Configuration Guide CD-ROM Publication number 5989-0421EN 5989-5062EN 5989-5063EN 5989-0423EN 5989-5595EN 5968-4632E 5966-4365E 5980-0941EN Agilent Email Updates www.agilent.com/find/emailupdates Get the latest information on the products and applications you select. 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Agilent offers open connectivity for a broad range of system-ready instruments, open industry software, PC-standard I/O and global support, which are combined to more easily integrate test system development. Product specifications and descriptions in this document subject to change without notice. © Agilent Technologies, Inc. 2007 Printed in USA, November 1, 2007 5989-0422EN