74HC595D

8-Bit Shift Registers With Latched 3-State Outputs 74HC595 FEATURES • • • • • Wide Operating Voltage Range of 2.0V to 6.0V 8-Bit Serial-Input, Serial or Parallel-Out Shift Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1.0µA High Noise Immunity Characteristic of CMOS Devices SOP-16 / TSSOP-16 APPLICATIONS • • • • Network Switches Power Infrastructure LED Displays Servers DIP-16 DESCRIPTION The 74HC595 devices contain and 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type latch with parallel 3-state outputs. Separate clocks are provided for both the shift register and latch. The shift register has a direct overriding clear input, serial input, and serial outputs for cascading. This device also has an asynchronous reset for the shift register. ORDERING INFORMATION Device Package 74HC595D SOP-16 74HC595TD TSSOP-16 74HC595N DIP-16 ABSOLUTE MAXIMUM RATINGS (Note 1) CHARACTERISTIC SYMBOL MIN. MAX. UNIT DC Supply Voltage (Referenced to GND) VCC -0.5 7.0 V DC Input Voltage (Referenced to GND) VIN -0.5 VCC + 0.5 V VOUT -0.5 VCC + 0.5 V IIN - ±20 mA DC Output Current IOUT - ±35 mA DC Supply Current ICC - ±75 mA Maximum Junction Temperature TJ - 150 °C TSTG -65 150 °C DC Output Voltage (Referenced to GND) DC Input Current Storage Temperature Note1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Dec. 2019 – R1.0.3 1/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 RECOMMENDED OPERATING CONDITIONS (Note 2) CHARACTERISTIC SYMBOL MIN. MAX. UNIT Supply Voltage VCC 2.0 6.0 V DC Input Voltage VIN 0 VCC V VOUT 0 VCC V TA -55 125 °C DC Output Voltage Operating Free-Air Temperature Range Note 2. The device is not guaranteed to function outside its operating ratings. ORDERING INFORMATION Package Order No. Description Package Marking Status SOP-16 74HC595D 8-Bit Shift Resisters 74HC595 Active TSSOP-16 74HC595TD 8-Bit Shift Resisters 74HC595 Contact Us DIP-16 74HC595N 8-Bit Shift Resisters 74HC595 Active Dec. 2019 – R1.0.3 2/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 PIN CONFIGURATION SOP-16 / TSSOP-16 / DIP-16 PIN DESCRIPTION Pin No. Pin Name Pin Function SOP-16 TSSOP-16 DIP-16 1 1 1 QB Parallel Data QB Output 2 2 2 QC Parallel Data QC Output 3 3 3 QD Parallel Data QD Output 4 4 4 QE Parallel Data QE Output 5 5 5 QF Parallel Data QF Output 6 6 6 QG Parallel Data QG Output 7 7 7 QH Parallel Data QH Output 8 8 8 GND Ground 9 9 9 SQH Serial Data Output 10 10 10 RESET Shift Register Reset Input 11 11 11 SHIFT CLOCK Shift Register Clock Input. 12 12 12 LATCH CLOCK Parallel Latch Clock Input 13 13 13 OUTPUT ENABLE 14 14 14 A Serial Data Input 15 15 15 QA Parallel Data QA Output 16 16 16 VCC Dec. 2019 – R1.0.3 3/13 Output Enable Power Supply HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 BLOCK DIAGRAM Dec. 2019 – R1.0.3 4/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 DC ELECTRICAL CHARACTERISTICS Voltages referenced to ground. Limit SYMBOL VIH VIL PARAMETER Minimum High-Level Input Voltage Maximum Low-Level Input Voltage TEST CONDITION VOH VOL 1.50 1.50 4.5 V 3.15 3.15 3.15 6.0 V 4.20 4.20 4.20 2.0 V 0.50 0.50 0.50 4.5 V 1.35 1.35 1.35 6.0 V 1.80 1.80 1.80 2.0 V 1.9 1.9 1.9 4.5 V 4.4 4.4 4.4 6.0 V 5.9 5.9 5.9 |IOUT| ≤ 6.0 mA 4.5 V 3.98 3.84 3.7 |IOUT| ≤ 7.8 mA 6.0 V 5.48 5.34 5.2 2.0 V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 6.0 V 0.1 0.1 0.1 |IOUT| ≤ 6.0 mA 4.5 V 0.26 0.33 0.4 |IOUT| ≤ 7.8 mA 6.0 V 0.26 0.33 0.4 2.0 V 1.9 1.9 1.9 4.5 V 4.4 4.4 4.4 6.0 V 5.9 5.9 5.9 |IOUT| ≤ 4.0 mA 4.5 V 3.98 3.84 3.7 |IOUT| ≤ 5.2 mA 6.0 V 5.48 5.34 5.2 2.0 V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 6.0 V 0.1 0.1 0.1 |IOUT| ≤ 4.0 mA 4.5 V 0.26 0.33 0.4 |IOUT| ≤ 5.2 mA 6.0 V 0.26 0.33 0.4 VOUT = 0.1V or VCC − 0.1V |IOUT| ≤ 20 µA VIN = VIH or VIL VIN = VIH or VIL |IOUT| ≤ 20 µA VOH Minimum High-Level Output Voltage, SQH VIN = VIH or VIL |IOUT| ≤ 20 µA VOL Maximum Low-Level Output Voltage, SQH ≤ 85°C ≤ 125°C 1.50 |IOUT| ≤ 20 µA Maximum Low-Level Output Voltage, QA – QH ≤ 25°C 2.0 V VOUT = 0.1V or VCC − 0.1V |IOUT| ≤ 20 µA |IOUT| ≤ 20 µA Minimum High-Level Output Voltage, QA – QH VCC VIN = VIH or VIL UNIT V V V V V V IIN Maximum Input Leakage Current VIN = VCC or GND 6.0 V ±0.1 ±1.0 ±1.0 µA IOZ Maximum Three-State Leakage Current, QA – QH Output in High-Impedance State VIN = VIH or VIL VOUT = VCC or GND 6.0 V ±0.5 ±5.0 ±10 µA ICC Maximum Quiescent Supply Current (per Pacakge) VIN = VCC or GND IOUT = 0 µA 6.0 V 4.0 40 160 µA Dec. 2019 – R1.0.3 5/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 AC ELECTRICAL CHARACTERISTICS CL = 50 pF, Input tr = tf = 6.0 ns Limit SYMBOL PARAMETER VCC ≤ 25°C ≤ 85°C ≤ 125°C UNIT 2.0 V 6.0 4.8 4.0 4.5 V 30 24 20 6.0 V 35 28 24 2.0 V 140 175 210 4.5 V 28 35 42 6.0 V 24 30 36 2.0 V 145 180 220 4.5 V 29 36 44 6.0 V 25 31 38 2.0 V 140 175 210 4.5 V 28 35 42 6.0 V 24 30 36 2.0 V 150 190 225 4.5 V 30 38 45 6.0 V 26 33 38 2.0 V 135 170 205 4.5 V 27 34 41 6.0 V 23 29 35 2.0 V 60 75 90 4.5 V 12 15 18 6.0 V 10 13 15 2.0 V 75 95 110 4.5 V 15 19 22 6.0 V 13 16 19 Maximum Input Capacitance – 10 10 10 pF COUT Maximum Three-State Output Capacitance (Output in HighImpedance State), QA – QH – 15 15 15 pF CPD Power Dissipation Capacitance (per Package) fmax tPLH, tPHL tPHL tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL tTLH, tTHL CIN Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 7) Maximum Propagation Delay, Shift Clock to SQH (Figures 1 and 7) Maximum Propagation Delay, Reset to SQH (Figures 2 and 7) Maximum Propagation Delay, Latch Clock to QA – QH (Figures 3 and 7) Maximum Propagation Delay, Output Enable to QA – QH (Figures 4 and 8) Maximum Propagation Delay, Output Enable to QA – QH (Figures 4 and 8) Maximum Output Transition Time, QA – QH (Figures 3 and 7) Maximum Output Transition Time, SQH (Figures 1 and 7) (Note 3) Note 3. Used to determine the no-load dynamic power consumption: PD = Dec. 2019 – R1.0.3 6/13 5.0 V 2 CPDVCC f 300 @ 25°C MHz ns ns ns ns ns ns ns pF + ICCVCC. HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 TIMING REQUIREMENTS CL = 50 pF, Input tr = tf = 6.0 ns Limit SYMBOL tsu tsu th trec tw tw tw tr , tf PARAMETER VCC Minimum Setup Time, Serial Data Input A to Shift Clock (Figure 5) Minimum Setup Time, Shift Clock to Latch Clock (Figure 6) Minimum Hold Time, Shift Clock to Serial Data Input A (Figure 5) Minimum Recovery Time, Reset Inactive to Shift Clock (Figure 2) Minimum Pulse Width, Reset (Figure 2) Minimum Pulse Width, Shift Clock (Figure 1) Minimum Pulse Width, Latch Clock (Figure 6) Maximum Input Rise and Fall Times (Figure 1) Dec. 2019 – R1.0.3 7/13 ≤ 25°C ≤ 85°C ≤ 125°C 2.0 V 50 65 75 4.5 V 10 13 15 6.0 V 9 11 13 2.0 V 75 95 110 4.5 V 15 19 22 6.0 V 13 16 19 2.0 V 5 5 5 4.5 V 5 5 5 6.0 V 5 5 5 2.0 V 50 65 75 4.5 V 10 13 15 6.0 V 9 11 13 2.0 V 60 75 90 4.5 V 12 15 18 6.0 V 10 13 15 2.0 V 50 65 75 4.5 V 10 13 15 6.0 V 9 11 13 2.0 V 50 65 75 4.5 V 10 13 15 6.0 V 9 11 13 2.0 V 1000 1000 1000 4.5 V 500 500 500 6.0 V 400 400 400 UNIT MHz ns ns ns ns ns ns ns HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 FUNCTION TABLE Inputs Resulting Function Reset Serial Input A Shift Clock Latch Clock Output Enable Shift Register Contents Latch Register Contents Serial Output SQH Parallel Outputs QA – QH Reset shift register L X X L, H, ↓ L L U L U Shift data into shift register H D ↑ L, H, ↓ L D→SRA; SRN→SRN+1 U SRG→SRH U Shift register remains unchanged H X L, H, ↓ L, H, ↓ L U U U U Transfer shift register contents to latch register H X L, H, ↓ ↑ L U SRN→LRN U SRN Latch register remains unchanged X X X L, H, ↓ L * U * U Enable parallel outputs X X X X L * ** * Enabled Force outputs into high impedance state X X X X H * ** * Z Operation SR: shift register contents D: data (L, H) logic level ↑: Low-to-High LR: latch register contents U: remains unchanged ↓: High-to-Low X: don’t care *: depends on Reset and Shift Clock inputs Z: high impedance **: depends on Latch Clock input Dec. 2019 – R1.0.3 8/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 SWITCHING WAVEFORMS Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. TEST CIRCUITS Dec. 2019 – R1.0.3 9/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 TIMING DIAGRAM Dec. 2019 – R1.0.3 10/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 FUNCTIONAL LOGIC DIAGRAM Dec. 2019 – R1.0.3 11/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 TYPICAL OPERATING CHARACTERISTICS T.B.D. Dec. 2019 – R1.0.3 12/13 HTC 8-Bit Shift Registers With Latched 3-State Outputs 74HC595 REVISION NOTICE The description in this data sheet is subject to change without any notice to describe its electrical characteristics properly. Dec. 2019 – R1.0.3 13/13 HTC