CD4081BN

CMOS Quad 2-Input AND Gates CD4081B FEATURES • Wide Operating Voltage Range of 3.0V to 18.0V • Maximum Input Current of 1µA at 18V over Full Package-Temperature range, 100nA at 18V and 25°C • Standardized Symmetrical Output Characteristics • Noise Margin 1.0V min @ 5.0V supply 2.0V min @ 10.0V supply 2.5V min @ 15.0V supply SOP-14 DESCRIPTION DIP-14 The CD4081B consist of four AND gate circuits. Each circuit functions as a two-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS. Unused inputs must be connected to VDD, VSS, or another input. Unused outputs must be left open. ORDERING INFORMATION Device Package CD4081BD SOP-14 CD4081BN DIP-14 ABSOLUTE MAXIMUM RATINGS (Note 1) CHARACTERISTIC SYMBOL MIN. MAX. UNIT DC Supply Voltage (Referenced to VSS) VDD −0.5 20 V DC Input Voltage (Referenced to VSS) VIN −0.5 VDD + 0.5 V DC Input Current IIN - ±10 mA Maximum Junction Temperature TJ - 150 °C TSTG −65 150 °C Storage Temperature Note1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Feb. 2020 – R1.1 1/9 HTC CMOS Quad 2-Input AND Gates CD4081B RECOMMENDED OPERATING CONDITIONS (Note 2) CHARACTERISTIC SYMBOL MIN. MAX. UNIT Supply Voltage VDD 3 18 V DC Input Voltage VIN 0 VDD V VOUT 0 VDD V TA −55 125 °C DC Output Voltage Operating Free-Air Temperature Range Note 2. The device is not guaranteed to function outside its operating ratings. ORDERING INFORMATION Package Order No. Description Supplied As Status SOP-14 CD4081BD Quad 2-Input AND Gate Tape & Reel Active DIP-14 CD4081BN Quad 2-Input AND Gate Tube Active Feb. 2020 – R1.1 2/9 HTC CMOS Quad 2-Input AND Gates CD4081B PIN CONFIGURATION SOP-14 DIP-14 1A 1 14 VDD 1A 1 14 VDD 1B 2 13 4B 1B 2 13 4B 1Y 3 12 4A 1Y 3 12 4A 2Y 4 11 4Y 2Y 4 11 4Y 2A 5 10 3Y 2A 5 10 3Y 2B 6 9 3B 2B 6 9 3B VSS 7 8 3A VSS 7 8 3A PIN DESCRIPTION Pin No. Pin Name Pin Function SOP-14 DIP-14 1 1 1A Input 1A 2 2 1B Input 1B 3 3 1Y Output 1 4 4 2Y Output 2 5 5 2A Input 2A 6 6 2B Input 2B 7 7 VSS Ground 8 8 3A Input 3A 9 9 3B Input 3B 10 10 3Y Output 3 11 11 4Y Output 4 12 12 4A Input 4A 13 13 4B Input 4B 14 14 VDD Feb. 2020 – R1.1 Power Supply 3/9 HTC CMOS Quad 2-Input AND Gates CD4081B BLOCK DIAGRAM 1A 1Y 1B 2A 2Y 2B 3A 3Y 3B 4A 4Y 4B Feb. 2020 – R1.1 4/9 HTC CMOS Quad 2-Input AND Gates CD4081B DC ELECTRICAL CHARACTERISTICS Voltages referenced to VSS. Limit SYMBOL VIH VIL VOH VOL IIN ICC IOL IOH PARAMETER Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Maximum Low-Level Output Voltage Maximum Input Leakage Current Maximum Quiescent Supply Current Minimum Output Low (Sink) Current Minimum Output High (Source) Current Feb. 2020 – R1.1 TEST CONDITION VDD UNIT −55°C 25°C 125°C VOUT = 0.5V or VDD − 0.5V 5V 3.5 3.5 3.5 VOUT = 1.0V or VDD – 1.0V 10 V 7 7 7 VOUT = 1.5V or VDD − 1.5V 15 V 11 11 11 VOUT = 0.5V 5V 1.5 1.5 1.5 VOUT = 1.0V 10 V 3 3 3 VOUT = 1.5V 15 V 4 4 4 5V 4.95 4.95 4.95 10 V 9.95 9.95 9.95 15 V 14.95 14.95 14.95 5V 0.05 0.05 0.05 10 V 0.05 0.05 0.05 15 V 0.05 0.05 0.05 18 V ±0.1 ±0.1 ±1.0 5V 0.25 0.25 7.5 10 V 0.5 0.5 15 15 V 1.0 1.0 30 20 V 5.0 5.0 150 VOL = 0.4V 5V 0.64 0.51 0.36 VOL = 0.5V 10 V 1.6 1.3 0.9 VOL = 1.5V 15 V 4.2 3.4 2.4 VOH = 2.5V 5V −2.0 −1.6 −1.15 VOH = 4.6V 5V −0.64 −0.51 −0.36 VOH = 9.5V 10 V −1.6 −1.3 −0.9 VOH = 13.5V 15 V −4.2 −3.4 −2.4 VIN = VDD VIN = VDD or VSS VIN = VDD or VSS VIN = VDD or VSS VIN = VDD or VSS VIN = VDD or VSS 5/9 V V V V µA µA mA mA HTC CMOS Quad 2-Input AND Gates CD4081B AC ELECTRICAL CHARACTERISTICS CL = 50 pF, RL = 200kΩ, Input tr = tf = 20 ns Limit SYMBOL tPLH, tPHL tTLH, tTHL CIN PARAMETER VDD Maximum Propagation Delay, Input A or Input B to Output Y (Figure 1) Maximum Output Transition Time, Any Output (Figure 1) Maximum Input Capacitance Feb. 2020 – R1.1 25°C 125°C 5V 250 250 500 10 V 120 120 240 15 V 90 90 180 5V 200 200 400 10 V 100 100 200 15 V 80 80 160 – 6/9 UNIT −55°C 7.5 ns ns pF HTC CMOS Quad 2-Input AND Gates CD4081B FUNCTION TABLE Input (A) Input (B) Output (Y) L L L L H L H L L H H H SWITCHING CHARACTERISTICS tr tf VDD 90% VIN 50% 10% VSS tPLH tPHL VOH 90% VOUT 50% 10% VOL tTLH tTHL Fig. 1. Switching Time Waveforms Feb. 2020 – R1.1 7/9 HTC CMOS Quad 2-Input AND Gates CD4081B TYPICAL OPERATING CHARACTERISTICS T.B.D. Feb. 2020 – R1.1 8/9 HTC CMOS Quad 2-Input AND Gates CD4081B REVISION NOTICE The description in this data sheet is subject to change without any notice to describe its electrical characteristics properly. Feb. 2020 – R1.1 9/9 HTC