DS1232N

Micro-Monitor DS1232 FEATURES • Halts and restarts an out-of-control μ-processor • Holds μ-processor in check during power transients • Automatically restarts μ-processor after power failure SOP-8 • Monitors push-button for external override • Accurate 5% or 10% μ-processor power supply monitoring • Eliminates the need for discrete components DIP-8 APPLICATIONS • μ-processor Power Monitoring ORDERING INFORMATION • Intelligent Instruments • Computers and Controllers • Automotive Systems Device Package DS1232D SOP-8 DS1232N DIP-8 DESCRIPTION The DS1232 Micro-Monitor monitors three vital conditions for a microprocessor: power supply, software execution, and external override. First, a precision temperature compensated reference and comparator circuit monitors the status of VCC. When an out–of–tolerance condition occurs, an internal power fail signal is generated which forces reset to the active state. When VCC returns to an in–tolerance condition, the reset signals are kept in the active state for a minimum of 250ms to allow the power supply and processor to stabilize. the DS1232 performs is pushbutton reset control. The second function The DS1232 debounces the pushbutton input and guarantees an active reset pulse width of 250ms minimum. The third function is a watchdog timer. The DS1232 has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to time–out. The watchdog timer function can be set to operate on time–out settings of approximately 150ms, 600ms, and 1.2 seconds. ABSOLUTE MAXIMUM RATINGS CHARACTERISTIC SYMBOL MIN. MAX. UNIT VCC -0.5 7.0 V PBRST , TD, TOL, RST , RST, ST -0.5 VCC+0.5 V TA -10 70 °C TSTG -55 125 °C Supply Voltage Input / Output Voltage Operating Ambient Temperature Range Storage Temperature Oct. 2019 – Rev 1.0 1/7 HTC Micro-Monitor DS1232 RECOMMENDED OPERATIONG CONDITIONS CHARACTERISTIC SYMBOL MIN. MAX. UNIT VCC 4.5 5.5 V ST and PBRST Input High Level VIH 2.0 VCC+0.3 V ST and PBRST Input Low Level VIL -0.3 0.8 V Supply Voltage ORDERING INFORMATION Package Order No. Description Supplied As Status SOP-8 DS1232D Micro-Monitor Reel Active DIP-8 DS1232N Micro-Monitor Tube Active Oct. 2019 – Rev 1.0 2/7 HTC Micro-Monitor DS1232 PIN CONFIGURATION PBRST 1 8 VCC TD 2 7 ST TOL 3 6 RST GND 4 5 RST SOP-8 / DIP-8 PIN DESCRIPTION Pin No. Pin Name Pin Function SOP-8 DIP-8 1 1 PBRST 2 2 TD 3 3 TOL Selects 5% or 10% VCC Detect 4 4 GND Ground 5 5 RST Reset Output (Active High) 6 6 RST Reset Output (Active Low, Open Drain) 7 7 ST Strobe Input 8 8 VCC 5V Supply Power Oct. 2019 – Rev 1.0 Pushbutton Reset Input Time Delay Set 3/7 HTC Micro-Monitor DS1232 ELECTRICAL CHARACTERISTICS Specifications with standard type face are for TA = 25°C, VCC = 5V, and those with boldface type are for -10°C to 70°C unless (Note 1) otherwise noted. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT 1.0 µA DC ELECTRICAL CHARACTERISTICS Input Leakage IIL (Note 3) -1.0 Output Current @ 2.4V IOH (Note 5) -8 -10 mA Output Current @ 0.4V IOL 8 10 mA Low Level @ RST VOL (Note 1) Output Voltage @ -500µA VOH (Note 1, 7) Operating Current ICC 0.4 VCC-0.5 (Note 2) VCC Trip Point VCCTP1 TOL=GND VCC Trip Point VCCTP2 TOL=VCC (Note 1) (Note 1) VCC-0.1 V V 0.5 2.0 mA 4.50 4.62 4.74 V 4.25 4.37 4.49 V AC ELECTRICAL CHARACTERISTICS PBRST = VIL tPB 20 RESET Active Time tRST 250 ST Pulse Width tST VCC Fail Detect to RST and RST VCC Slew Rate 4.75V to 4.25V VCC Detect to RST and RST Transition VCC Slew Rate 4.25V to 4.75V PBRST Stable Low to RST and RST (Note 6, 8) 610 175 300 (Note 4) tR ms ns 100 tF 1000 20 tRPD tRPU ms µs µs 250 610 0 5 1000 ms µs tPDLY 20 ms CIN 5 pF COUT 7 pF CAPACITANCE Input Capacitance Output Capacitance Note 1. All voltages referenced to ground. Note 2. Measured with outputs open. Note 3. ��������� PBRST is internally pulled up to VCC with an internal impedance of 10K typical. Note 4. tR = 5 μs. Note 5. ����� RST is an open drain output. Note 6. Must not exceed tTD minimum. See Table 1. Note 7. RST remains within 0.5V of VCC on power–down until VCC drops below 2.0V. ����� remains within 0.5V of GND on power–down until VCC drops below 2.0V. RST Note 8. Watchdog cannot be disabled. It must be strobed to avoid resets. Oct. 2019 – Rev 1.0 4/7 HTC Micro-Monitor DS1232 TYPICAL APPLICATION INFORMATION Fig.1. Block Diagram Fig 2. Typical Application Power Monitor The DS1232 detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When VCC falls below a preset level as defined by TOL (Pin 3), the VCC comparator outputs the ����� signals become ����� (Pin 6). When TOL is connected to ground, the RST and RST signals RST (Pin 5) and RST ����� active as VCC falls below 4.75 volts. When TOL is connected to VCC, the RST and RST signals become active ����� are excellent control signals for a microprocessor, as processing as VCC falls below 4.5 volts. The RST and RST RST are kept active for a minimum is stopped at the last possible moments of valid VCC. On power-up, RST and ����� of 250 ms to allow the power supply and processor to stabilize. Pushbutton Reset The DS1232 provides an input pin for direct connection to a pushbutton. The pushbutton reset input requires an ����� signals of at least 250 active low signal. Internally, this input is debounced and timed such that RST and RST ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is released from low level. Watchdog Timer ����� signals to the active state when the ��� ST input is not stimulated for A watchdog timer function forces RST and RST a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to VCC. The watchdog timer starts timing out from the set time period as soon as RST and ����� RST are inactive. If a high-to-low transition occurs on the ��� ST input pin prior to timeout, the watchdog timer is reset and begins to timeout again. If the watchdog timer is allowed to timeout, then the RST and ����� RST signals are driven to the active state for 250 ms minimum. The ��� ST input can be derived from microprocessor address signals, data signals, and/or control Oct. 2019 – Rev 1.0 5/7 HTC Micro-Monitor DS1232 signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. To guarantee that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum shown in Table 1. Timing Diagrams Fig. 3. Power Up Timing Diagram Fig. 4. Power Down Timing Diagram Fig. 5. Pushbutton Reset Timing Diagram Fig. 6. Strobe Input Timing Diagram Table 1. Watchdog Timeouts TIME-OUT TD Pin Oct. 2019 – Rev 1.0 Min. Typ. Max. GND 62.5ms 150ms 250ms Float 250ms 600ms 1000ms Vcc 500ms 1200ms 2000ms 6/7 HTC Micro-Monitor DS1232 REVISION NOTICE The description in this data sheet is subject to change without any notice to describe its electrical characteristics properly. Oct. 2019 – Rev 1.0 7/7 HTC