LM3843A

CURRENT MODE PWM CONTROLLER FEATURES ● Automatic feed forward compensation ● ● ● ● ● Optimized for offline converter Double pulse suppression Current mode operation to 500 KHz High gain totem pole output Internally trimmed bandgap reference Compen sation Voltage Feedback Current Sense RT/CT LM3842A/3A/4A/5A 8 SOP/ 8 DIP PIN Configulation 1 2 3 4 8 7 6 5 VREF Vcc OUTPUT GND ● Undervoltage lockout with hysteresis ● Low start up current :＜ 0.3 mA ORDERING INFORMATION Device Package 8 SOP 8 DIP DESCRIPTION LM3842A/3A/4A/5A D LM3842A/3A/4A/5A N The LM3842A is fixed frequency current-mode PWM controller. It is specially designed for Off-Line and DC-to-DC converter applications with minimal external components. This integrated circuit features a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totempole output ideally suited for driving a power MOSFET. Protection circuitry includes built in under-voltage lockout and current limiting. SIMPLIFIED BLOCK DIAGRAM VREF ⑧ 5V Reference VREF Undervoltage Lockout Oscillator + Vcc Undervoltage Lockout R R RT/CT ④ VFB ② COMP ① ⑦ Vcc Latching PWM ⑥ Output ⑤ Ground ③ Current Sense Input Error Amplifie r ABSOLUTE MAXIMUM RATINGS (TA= 25℃) Characteristic Power Supply Voltage Output Current Analog Inputes Voltage Error Amp Output Sink Current Power Dissipation Storage Temperature Range Lead Temperature (soldering 5 sec) Symbol Vcc I VIN ISINK PD Tstg T Value 30 ±1 -0.3 to 5.5V 10 1 -65 to 150 260 Unit V A V mA W ℃ ℃ HTC 1 CURRENT MODE PWM CONTROLLER ELECTRICAL CHARACTERISTIC LM3842A/3A/4A/5A (Vcc=15V(Note 1), RT = 10kΩ, CT=3.3nF 0 ≤ TA ≤ 70℃ ; unless otherwise specified) Characteristic REFERENCE SECTION Reference Output Voltage Line Regulation Load Regulation Output Short Circuit Current OSCILLATOR SECTION Normal Frequency Voltage Stability Amplitude ERROR AMPLIFIER SECTION Input B Current Feedback Input Voltage Open Loop Voltage Gain Power Supplier Rejection Ratio Output Sink Current Output source Current Output Voltage High Output Voltage Low CURRENT SENSE SECTION Input Voltage Gain Maximum Input Signal Power Supply Rejection Ratio Input Bias Current OUTPUT SECTION Output Voltage Low Output Voltage High Rise Time Fail Time UNDERVOLTAGE LOCKOUT SECTION Start-up Threshold Minimum Operating Voltage (After Turn-On ) TOTAL STANDBY CURRENT Start-up Current Operating Supply Current Zener Voltage Symbol VREF Vo Vo Isc FOSC Sv Vosc IIB VFB AVOL PSRREA ISI ISO VOH VOL Av VMAX PSRRSC IIB VOL VOH T T Vth VCC(MIN) Ist ICC V Test Condition Tj = 25℃, IO=1 mA 12V ≤ Vcc ≤ 25V 1mA ≤ Io ≤ 20mA TA = 25℃ Tj = 25℃ 12V ≤ Vcc ≤ 25V Min 4.90 Typ 5.00 2 3 -85 52 0.2 1.6 -0.1 2.50 90 70 Max 5.10 20 2.5 -180 57 1 Unit V mV mV mA kHz % Vp-p μA V dB dB mA mA V V V/V V dB μA V V V V nS nS V V V V mA mA V 47 Vo=2.5V 2.42 2V≤ Vo ≤ 4V 65 60 12V ≤ Vcc ≤ 25V VFB=2.7V, Vo - 1.1V 2 V = 2.3V, Vo=5V -0.5 VFB=2.7V, RL=15kΩ to GND 5 VFB=2.7V, RL=15kΩ to VRGR (Note 2 & 3) Vo=5V (Note 2) 12V ≤ Vcc ≤ 25V 2.85 0.9 -2 2.58 7 -1.0 6 0.8 3 1 70 -2 0.1 1.5 13.5 13.0 45 35 16 8.4 10 7.6 0.17 13 38 1.1 3.15 1.1 -1.0 0.4 2.2 Isink = 20mA Isink = 20mA Isource = 20mA Isource = 20mA Tj = 25℃, CL=1nF Tj = 25℃, CL=1nF 3842A 3843A 3842A 3843A / / / / 3844A 3845A 3844A 3845A 13 12 150 150 17.5 9 11.5 8.2 0.3 17 14.5 7.8 8.5 7.0 Vcc=14V Icc = 25mA 30 Note: 1. Adjust Vcc above the start threshould before setting at 15V. 2. Parameter measured at trip point of latch with VFB - 0. 3. Comparator Gain defined as: A V = ΔV Output Compensation(pin FB) ; ΔV Current Sanseinput(pin CS) HTC 2 CURRENT MODE PWM CONTROLLER Fig.1 Open Loop Test Circuit LM3842A/3A/4A/5A VREF RT 4.7K 2N 2222 A V1 1 E/A ADJUST 1K 100K 2 ISENSE ADJUST 4.7K CT 5K 3 COMP VREF 8 0.1 VFB VC 7 1K/1W 0.1 OUTPUT LM3842A ISENSE RT/C T OUTPUT 6 5 4 GND High peak currents associated with capacitive loads necessitate careful grounding techniques Timing and bypass capacitors should be connected close to pin 5 in a single point ground. The transistor and 5KΩ potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. Fig.2 Under Voltage Lockout 7 ON/OFF COMMAND TO REST OF IC ICC LM3842A VON VOFF 16V 10V LM3843A/5A 8.4V 7.6V < 15mA < 1mA VOFF VON VCC During Under-Voltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage current. Fig.3 Error Amp Configuration 2.5V 0.5mA + VFB Zi Zf COMP 2 1 - Error amp can source or sink up to 0.5mA HTC 3 CURRENT MODE PWM CONTROLLER Fig.4 Current Sense Circuit ERROR AMP IS 2R LM3842A/3A/4A/5A 1 R COMP CURRENT SENSE R 1V CURRENT SENSE COMPARATOR 3 C RS GND 5 Peak current (IS) is determined by the formula: IS(MAX) ~ 1.0V RS A small RC filter may be required to suppress switch transients. Fig.5 Oscillator Waveforms and Maximum Duty Cycle VREF 8 RT RT/CT INTERNAL CLOCK 4 CT GND 5 INTERNAL CLOCK LARGE RT SMALL CT V4 LARGE RT SMALL CT V4 Oscillator timing capacitor, CT, is charged by VREF through RT, and discharged by an internal current source. During the discharge time, the internal clock signal blanks the output to the low state. Selection of RT and CT therefore determines both oscillator frequency and maximum duty cycle. Charge and discharge times are determined by the formulas: tc ~ 0.55 RT CT ~ td ~ RT CT ∫n( 0.0063 RT - 2.7 ) 0.0063 RT - 4 -1 Frequency, then, is: f = (tc + td) For RT>5KΩ, f~ 1.8 RT CT HTC 4 CURRENT MODE PWM CONTROLLER Fig.6 Shutdown Techniques 1K LM3842A/3A/4A/5A 8 VREF 1 COMP 330Ω 500Ω 3 ISENSE SHUTDOWN SHUTDOWN TO CURRENT SENSE-RESISTOR Shutdown of the LM3842A can be accomplished by two methods; either raise pin 3 above 1V or pull pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shoutdown condition at pins 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold. At this point the reference turns off, allowing the SCR to reset. Fig.7 Slope Compensation VREF 8 0.1μF RT LM3842A RT/CT 4 CT R1 ISENSE R2 ISENSE 3 RSENCE C A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. Note that capacitor, C, forms a filter with R2 to suppress the leading edge switch spikes. HTC 5 CURRENT MODE PWM CONTROLLER Fig.1 Output Dead Time 80 RT, Timing Resister (kΩ 50 CT=10nF CT=5.0nF 20 8.0 5.0 2.0 0.8 10k 20k 50k100k 200k 500k 1.0M 3 100 1k CT=2.0nF CT=1.0nF CT=500pF CT=200pF CT=100pF 30 100 LM3842A/3A/4A/5A Fig.2 Timing Resistor vs Frequency CT=100nF CT=47nF RT(kΩ) CT=22nF CT=10nF 10 CT=4.7nF CT=2.2nF CT=10nF fosc, Frequency (kHz) 10k 100k 1M fosc, Frequency(Hz) Fig.3 Output Saturation Characteristics Fig.4 Error Amplifier Open Loop Gain and Phase Frequency VSAT, Output Saturation Voltage (V 4 VCC=15V TA=25℃ 3 AVOL, Open-Loop Voltage Gain (d 80 Gain 60 0 Φ, Excess Phase Degree -45 2 40 Phase -90 1 SOURCE (VC-VOH) C 20 -135 SINK (V ) OL 0 -180 0 10-3 2 4 6 8 10-1 2 4 68 10 100 1K 10K 100K 1M 10M Io, Output Load Current (A) Fosc, Frequency (Hz) PIN FUNCTION DESCRIPTION Pin No. 1 2 3 4 Function Description Compensation This pin is the Error Amplifier output and is made available for loop compensation. Voltage This is the inverting input of the Error Amplitier. It is normally connected Feedback to the switching power supply output through a resister divider. Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to VREF and capacitor CT to ground. Operation to 500kHz is possible. GND This pin is the combined control circuitry and power ground. Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0A are sourced and sunk by this pin. Vcc This pin is the positive supply of the control IC. VREF This is the reference output. It provides charging current for capacitor CT through resistor RT. 5 6 7 8 HTC 6